| at91_streg.h (185265) | at91_streg.h (238376) |
|---|---|
| 1/*- 2 * Copyright (c) 2005 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 9 unchanged lines hidden (view full) --- 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 | 1/*- 2 * Copyright (c) 2005 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 9 unchanged lines hidden (view full) --- 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 |
| 26/* $FreeBSD: head/sys/arm/at91/at91_streg.h 185265 2008-11-25 00:13:26Z imp $ */ | 26/* $FreeBSD: head/sys/arm/at91/at91_streg.h 238376 2012-07-11 20:17:14Z imp $ */ |
| 27 28#ifndef ARM_AT91_AT91STREG_H 29#define ARM_AT91_AT91STREG_H 30 31#define ST_CR 0x00 /* Control register */ 32#define ST_PIMR 0x04 /* Period interval mode register */ 33#define ST_WDMR 0x08 /* Watchdog mode register */ 34#define ST_RTMR 0x0c /* Real-time mode register */ --- 15 unchanged lines hidden (view full) --- 50#define ST_SR_PITS (1U << 0) /* PITS: Period Interval Timer Status */ 51#define ST_SR_WDOVF (1U << 1) /* WDOVF: Watchdog Overflow */ 52#define ST_SR_RTTINC (1U << 2) /* RTTINC: Real-time Timer Increment */ 53#define ST_SR_ALMS (1U << 3) /* ALMS: Alarm Status */ 54 55/* ST_CRTR */ 56#define ST_CRTR_MASK 0xfffff /* 20-bit counter */ 57 | 27 28#ifndef ARM_AT91_AT91STREG_H 29#define ARM_AT91_AT91STREG_H 30 31#define ST_CR 0x00 /* Control register */ 32#define ST_PIMR 0x04 /* Period interval mode register */ 33#define ST_WDMR 0x08 /* Watchdog mode register */ 34#define ST_RTMR 0x0c /* Real-time mode register */ --- 15 unchanged lines hidden (view full) --- 50#define ST_SR_PITS (1U << 0) /* PITS: Period Interval Timer Status */ 51#define ST_SR_WDOVF (1U << 1) /* WDOVF: Watchdog Overflow */ 52#define ST_SR_RTTINC (1U << 2) /* RTTINC: Real-time Timer Increment */ 53#define ST_SR_ALMS (1U << 3) /* ALMS: Alarm Status */ 54 55/* ST_CRTR */ 56#define ST_CRTR_MASK 0xfffff /* 20-bit counter */ 57 |
| 58void at91_st_delay(int n); 59void at91_st_cpu_reset(void); 60 |
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| 58#endif /* ARM_AT91_AT91STREG_H */ | 61#endif /* ARM_AT91_AT91STREG_H */ |