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at91_st.c (238341) at91_st.c (238376)
1/*-
2 * Copyright (c) 2005 Olivier Houchard. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.

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19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2005 Olivier Houchard. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.

--- 10 unchanged lines hidden (view full) ---

19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: head/sys/arm/at91/at91_st.c 238341 2012-07-10 06:21:42Z imp $");
27__FBSDID("$FreeBSD: head/sys/arm/at91/at91_st.c 238376 2012-07-11 20:17:14Z imp $");
28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/kernel.h>
32#include <sys/module.h>
33#include <sys/time.h>
34#include <sys/bus.h>
35#include <sys/resource.h>

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40#include <machine/bus.h>
41#include <machine/cpu.h>
42#include <machine/cpufunc.h>
43#include <machine/resource.h>
44#include <machine/frame.h>
45#include <machine/intr.h>
46#include <arm/at91/at91var.h>
47#include <arm/at91/at91_streg.h>
28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/kernel.h>
32#include <sys/module.h>
33#include <sys/time.h>
34#include <sys/bus.h>
35#include <sys/resource.h>

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40#include <machine/bus.h>
41#include <machine/cpu.h>
42#include <machine/cpufunc.h>
43#include <machine/resource.h>
44#include <machine/frame.h>
45#include <machine/intr.h>
46#include <arm/at91/at91var.h>
47#include <arm/at91/at91_streg.h>
48#include <arm/at91/at91rm92reg.h>
48
49static struct at91_st_softc {
50 struct resource * sc_irq_res;
51 struct resource * sc_mem_res;
52 void * sc_intrhand;
53 eventhandler_tag sc_wet; /* watchdog event handler tag */
54} *timer_softc;
55
56static inline uint32_t
57RD4(bus_size_t off)
58{
59
49
50static struct at91_st_softc {
51 struct resource * sc_irq_res;
52 struct resource * sc_mem_res;
53 void * sc_intrhand;
54 eventhandler_tag sc_wet; /* watchdog event handler tag */
55} *timer_softc;
56
57static inline uint32_t
58RD4(bus_size_t off)
59{
60
61 if (timer_softc == NULL) {
62 uint32_t *p = (uint32_t *)(AT91_BASE + AT91RM92_ST_BASE + off);
63
64 return *p;
65 }
66
60 return (bus_read_4(timer_softc->sc_mem_res, off));
61}
62
63static inline void
64WR4(bus_size_t off, uint32_t val)
65{
66
67 return (bus_read_4(timer_softc->sc_mem_res, off));
68}
69
70static inline void
71WR4(bus_size_t off, uint32_t val)
72{
73
67 bus_write_4(timer_softc->sc_mem_res, off, val);
74 if (timer_softc == NULL) {
75 uint32_t *p = (uint32_t *)(AT91_BASE + AT91RM92_ST_BASE + off);
76
77 *p = val;
78 }
79 else
80 bus_write_4(timer_softc->sc_mem_res, off, val);
68}
69
70static void at91_st_watchdog(void *, u_int, int *);
71static void at91_st_initclocks(device_t , struct at91_st_softc *);
72
73static inline int
74st_crtr(void)
75{

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100 /* The interrupt is shared, so we have to make sure it's for us. */
101 if (RD4(ST_SR) & ST_SR_PITS) {
102 hardclock(TRAPF_USERMODE(fp), TRAPF_PC(fp));
103 return (FILTER_HANDLED);
104 }
105 return (FILTER_STRAY);
106}
107
81}
82
83static void at91_st_watchdog(void *, u_int, int *);
84static void at91_st_initclocks(device_t , struct at91_st_softc *);
85
86static inline int
87st_crtr(void)
88{

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113 /* The interrupt is shared, so we have to make sure it's for us. */
114 if (RD4(ST_SR) & ST_SR_PITS) {
115 hardclock(TRAPF_USERMODE(fp), TRAPF_PC(fp));
116 return (FILTER_HANDLED);
117 }
118 return (FILTER_STRAY);
119}
120
108static void
121void
109at91_st_delay(int n)
110{
111 uint32_t start, end, cur;
112
113 start = st_crtr();
114 n = (n * 1000) / 32768;
115 if (n <= 0)
116 n = 1;
117 end = (start + n) & ST_CRTR_MASK;
118 cur = start;
119 if (start > end) {
120 while (cur >= start || cur < end)
121 cur = st_crtr();
122 } else {
123 while (cur < end)
124 cur = st_crtr();
125 }
126}
127
122at91_st_delay(int n)
123{
124 uint32_t start, end, cur;
125
126 start = st_crtr();
127 n = (n * 1000) / 32768;
128 if (n <= 0)
129 n = 1;
130 end = (start + n) & ST_CRTR_MASK;
131 cur = start;
132 if (start > end) {
133 while (cur >= start || cur < end)
134 cur = st_crtr();
135 } else {
136 while (cur < end)
137 cur = st_crtr();
138 }
139}
140
128static void
141void
129at91_st_cpu_reset(void)
130{
131 /*
132 * Reset the CPU by programmig the watchdog timer to reset the
133 * CPU after 128 'slow' clocks, or about ~4ms. Loop until
134 * the reset happens for safety.
135 */
136 WR4(ST_WDMR, ST_WDMR_RSTEN | 2);

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204{
205 int err;
206
207 timer_softc = device_get_softc(dev);
208 err = at91_st_activate(dev);
209 if (err)
210 return err;
211
142at91_st_cpu_reset(void)
143{
144 /*
145 * Reset the CPU by programmig the watchdog timer to reset the
146 * CPU after 128 'slow' clocks, or about ~4ms. Loop until
147 * the reset happens for safety.
148 */
149 WR4(ST_WDMR, ST_WDMR_RSTEN | 2);

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217{
218 int err;
219
220 timer_softc = device_get_softc(dev);
221 err = at91_st_activate(dev);
222 if (err)
223 return err;
224
212 soc_data.delay = at91_st_delay;
213 soc_data.reset = at91_st_cpu_reset; // XXX kinda late to be setting this...
214
215 timer_softc->sc_wet = EVENTHANDLER_REGISTER(watchdog_list,
216 at91_st_watchdog, dev, 0);
217
218 device_printf(dev,
219 "watchdog registered, timeout intervall max. 64 sec\n");
220
221 at91_st_initclocks(dev, timer_softc);
222 return (0);

--- 81 unchanged lines hidden --- 		225 timer_softc->sc_wet = EVENTHANDLER_REGISTER(watchdog_list,
226 at91_st_watchdog, dev, 0);
227
228 device_printf(dev,
229 "watchdog registered, timeout intervall max. 64 sec\n");
230
231 at91_st_initclocks(dev, timer_softc);
232 return (0);

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