| at91_sscreg.h (163524) | at91_sscreg.h (163680) |
|---|---|
| 1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 8 unchanged lines hidden (view full) --- 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 | 1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 8 unchanged lines hidden (view full) --- 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 |
| 25/* $FreeBSD: head/sys/arm/at91/at91_sscreg.h 163524 2006-10-20 07:08:15Z imp $ */ | 25/* $FreeBSD: head/sys/arm/at91/at91_sscreg.h 163680 2006-10-25 07:58:18Z imp $ */ |
| 26 27#ifndef ARM_AT91_AT91_SSCREG_H 28#define ARM_AT91_AT91_SSCREG_H 29 30/* Registers */ 31#define SSC_CR 0x00 /* Control Register */ 32#define SSC_CMR 0x04 /* Clock Mode Register */ 33 /* 0x08 Reserved */ --- 93 unchanged lines hidden (view full) --- 127#define SSC_TFMR_FSOS_HIGH (4u << 20) 128#define SSC_TFMR_FSOS_TOGGLE (5u << 20) 129#define SSC_TFMR_FSLEN (0xfu << 16) /* FSLEN: Receive Frame Sync Length */ 130#define SSC_TFMR_DATNB (0xfu << 8) /* DATNB: Data Number per Frame */ 131#define SSC_TFMR_MSFBF (1u << 7) /* MSBF: Most Significant Bit First */ 132#define SSC_TFMR_DATDEF (1u << 5) /* DATDEF: Data Default Value */ 133#define SSC_TFMR_DATLEN (0x1fu << 0) /* DATLEN: Data Length */ 134 | 26 27#ifndef ARM_AT91_AT91_SSCREG_H 28#define ARM_AT91_AT91_SSCREG_H 29 30/* Registers */ 31#define SSC_CR 0x00 /* Control Register */ 32#define SSC_CMR 0x04 /* Clock Mode Register */ 33 /* 0x08 Reserved */ --- 93 unchanged lines hidden (view full) --- 127#define SSC_TFMR_FSOS_HIGH (4u << 20) 128#define SSC_TFMR_FSOS_TOGGLE (5u << 20) 129#define SSC_TFMR_FSLEN (0xfu << 16) /* FSLEN: Receive Frame Sync Length */ 130#define SSC_TFMR_DATNB (0xfu << 8) /* DATNB: Data Number per Frame */ 131#define SSC_TFMR_MSFBF (1u << 7) /* MSBF: Most Significant Bit First */ 132#define SSC_TFMR_DATDEF (1u << 5) /* DATDEF: Data Default Value */ 133#define SSC_TFMR_DATLEN (0x1fu << 0) /* DATLEN: Data Length */ 134 |
| 135/* SSC_SR */ 136#define SSC_SR_TXRDY (1u << 0) 137#define SSC_SR_TXEMPTY (1u << 1) 138#define SSC_SR_ENDTX (1u << 2) 139#define SSC_SR_TXBUFE (1u << 3) 140#define SSC_SR_RXRDY (1u << 4) 141#define SSC_SR_OVRUN (1u << 5) 142#define SSC_SR_ENDRX (1u << 6) 143#define SSC_SR_RXBUFF (1u << 7) 144#define SSC_SR_TXSYN (1u << 10) 145#define SSC_SR_RSSYN (1u << 11) 146#define SSC_SR_TXEN (1u << 16) 147#define SSC_SR_RXEN (1u << 17) 148 |
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| 135#endif /* ARM_AT91_AT91_SSCREG_H */ | 149#endif /* ARM_AT91_AT91_SSCREG_H */ |