| at91_sscreg.h (157091) | at91_sscreg.h (163524) |
|---|---|
| 1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 8 unchanged lines hidden (view full) --- 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 | 1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 8 unchanged lines hidden (view full) --- 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 |
| 25/* $FreeBSD: head/sys/arm/at91/at91_sscreg.h 157091 2006-03-24 07:42:33Z imp $ */ | 25/* $FreeBSD: head/sys/arm/at91/at91_sscreg.h 163524 2006-10-20 07:08:15Z imp $ */ |
| 26 27#ifndef ARM_AT91_AT91_SSCREG_H 28#define ARM_AT91_AT91_SSCREG_H 29 | 26 27#ifndef ARM_AT91_AT91_SSCREG_H 28#define ARM_AT91_AT91_SSCREG_H 29 |
| 30/* Registers */ 31#define SSC_CR 0x00 /* Control Register */ 32#define SSC_CMR 0x04 /* Clock Mode Register */ 33 /* 0x08 Reserved */ 34 /* 0x0c Reserved */ 35#define SSC_RCMR 0x10 /* Receive Clock Mode Register */ 36#define SSC_RFMR 0x14 /* Receive Frame Mode Register */ 37#define SSC_TCMR 0x18 /* Transmit Clock Mode Register */ 38#define SSC_TFMR 0x1c /* Transmit Frame Mode register */ 39#define SSC_RHR 0x20 /* Receive Holding Register */ 40#define SSC_THR 0x24 /* Transmit Holding Register */ 41 /* 0x28 Reserved */ 42 /* 0x2c Reserved */ 43#define SSC_RSHR 0x30 /* Receive Sync Holding Register */ 44#define SSC_TSHR 0x34 /* Transmit Sync Holding Register */ 45 /* 0x38 Reserved */ 46 /* 0x3c Reserved */ 47#define SSC_SR 0x40 /* Status Register */ 48#define SSC_IER 0x44 /* Interrupt Enable Register */ 49#define SSC_IDR 0x48 /* Interrupt Disable Register */ 50#define SSC_IMR 0x4c /* Interrupt Mask Register */ 51/* And PDC registers */ 52 53/* SSC_CR */ 54#define SSC_CR_RXEN (1u << 0) /* RXEN: Receive Enable */ 55#define SSC_CR_RXDIS (1u << 1) /* RXDIS: Receive Disable */ 56#define SSC_CR_TXEN (1u << 8) /* TXEN: Transmit Enable */ 57#define SSC_CR_TXDIS (1u << 9) /* TXDIS: Transmit Disable */ 58#define SSC_CR_SWRST (1u << 15) /* SWRST: Software Reset */ 59 60/* SSC_CMR */ 61#define SSC_CMR_DIV 0xfffu /* DIV: Clock Divider mask */ 62 63/* SSC_RCMR */ 64#define SSC_RCMR_PERIOD (0xffu << 24) /* PERIOD: Receive Period Divider sel*/ 65#define SSC_RCMR_STTDLY (0xffu << 16) /* STTDLY: Receive Start Delay */ 66#define SSC_RCMR_START (0xfu << 8) /* START: Receive Start Sel */ 67#define SSC_RCMR_START_CONT (0u << 8) 68#define SSC_RCMR_START_TX_START (1u << 8) 69#define SSC_RCMR_START_LOW_RF (2u << 8) 70#define SSC_RCMR_START_HIGH_RF (3u << 8) 71#define SSC_RCMR_START_FALL_EDGE_RF (4u << 8) 72#define SSC_RCMR_START_RISE_EDGE_RF (5u << 8) 73#define SSC_RCMR_START_LEVEL_CHANGE_RF (6u << 8) 74#define SSC_RCMR_START_ANY_EDGE_RF (7u << 8) 75#define SSC_RCMR_CKI (1u << 5) /* CKI: Receive Clock Inversion */ 76#define SSC_RCMR_CKO (7u << 2) /* CKO: Receive Clock Output Mode Sel*/ 77#define SSC_RCMR_CKO_NONE (0u << 2) 78#define SSC_RCMR_CKO_CONTINUOUS (1u << 2) 79#define SSC_RCMR_CKS (3u) /* CKS: Receive Clock Selection */ 80#define SSC_RCMR_CKS_DIVIDED (0) 81#define SSC_RCMR_CKS_TK_CLOCK (1) 82#define SSC_RCMR_CKS_RK (2) 83 84/* SSC_RFMR */ 85#define SSC_RFMR_FSEDGE (1u << 24) /* FSEDGE: Frame Sync Edge Detection */ 86#define SSC_RFMR_FSOS (7u << 20) /* FSOS: Receive frame Sync Out sel */ 87#define SSC_RFMR_FSOS_NONE (0u << 20) 88#define SSC_RFMR_FSOS_NEG_PULSE (1u << 20) 89#define SSC_RFMR_FSOS_POS_PULSE (2u << 20) 90#define SSC_RFMR_FSOS_LOW (3u << 20) 91#define SSC_RFMR_FSOS_HIGH (4u << 20) 92#define SSC_RFMR_FSOS_TOGGLE (5u << 20) 93#define SSC_RFMR_FSLEN (0xfu << 16) /* FSLEN: Receive Frame Sync Length */ 94#define SSC_RFMR_DATNB (0xfu << 8) /* DATNB: Data Number per Frame */ 95#define SSC_RFMR_MSFBF (1u << 7) /* MSBF: Most Significant Bit First */ 96#define SSC_RFMR_LOOP (1u << 5) /* LOOP: Loop Mode */ 97#define SSC_RFMR_DATLEN (0x1fu << 0) /* DATLEN: Data Length */ 98 99/* SSC_TCMR */ 100#define SSC_TCMR_PERIOD (0xffu << 24) /* PERIOD: Receive Period Divider sel*/ 101#define SSC_TCMR_STTDLY (0xffu << 16) /* STTDLY: Receive Start Delay */ 102#define SSC_TCMR_START (0xfu << 8) /* START: Receive Start Sel */ 103#define SSC_TCMR_START_CONT (0u << 8) 104#define SSC_TCMR_START_RX_START (1u << 8) 105#define SSC_TCMR_START_LOW_RF (2u << 8) 106#define SSC_TCMR_START_HIGH_RF (3u << 8) 107#define SSC_TCMR_START_FALL_EDGE_RF (4u << 8) 108#define SSC_TCMR_START_RISE_EDGE_RF (5u << 8) 109#define SSC_TCMR_START_LEVEL_CHANGE_RF (6u << 8) 110#define SSC_TCMR_START_ANY_EDGE_RF (7u << 8) 111#define SSC_TCMR_CKI (1u << 5) /* CKI: Receive Clock Inversion */ 112#define SSC_TCMR_CKO (7u << 2) /* CKO: Receive Clock Output Mode Sel*/ 113#define SSC_TCMR_CKO_NONE (0u << 2) 114#define SSC_TCMR_CKO_CONTINUOUS (1u << 2) 115#define SSC_TCMR_CKS (3u) /* CKS: Receive Clock Selection */ 116#define SSC_TCMR_CKS_DIVIDED (0) 117#define SSC_TCMR_CKS_RK_CLOCK (1) 118#define SSC_TCMR_CKS_TK (2) 119 120/* SSC_TFMR */ 121#define SSC_TFMR_FSEDGE (1u << 24) /* FSEDGE: Frame Sync Edge Detection */ 122#define SSC_TFMR_FSOS (7u << 20) /* FSOS: Receive frame Sync Out sel */ 123#define SSC_TFMR_FSOS_NONE (0u << 20) 124#define SSC_TFMR_FSOS_NEG_PULSE (1u << 20) 125#define SSC_TFMR_FSOS_POS_PULSE (2u << 20) 126#define SSC_TFMR_FSOS_LOW (3u << 20) 127#define SSC_TFMR_FSOS_HIGH (4u << 20) 128#define SSC_TFMR_FSOS_TOGGLE (5u << 20) 129#define SSC_TFMR_FSLEN (0xfu << 16) /* FSLEN: Receive Frame Sync Length */ 130#define SSC_TFMR_DATNB (0xfu << 8) /* DATNB: Data Number per Frame */ 131#define SSC_TFMR_MSFBF (1u << 7) /* MSBF: Most Significant Bit First */ 132#define SSC_TFMR_DATDEF (1u << 5) /* DATDEF: Data Default Value */ 133#define SSC_TFMR_DATLEN (0x1fu << 0) /* DATLEN: Data Length */ 134 |
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| 30#endif /* ARM_AT91_AT91_SSCREG_H */ | 135#endif /* ARM_AT91_AT91_SSCREG_H */ |