1/*-
2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
--- 8 unchanged lines hidden (view full) ---
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 */
24
25/* $FreeBSD: head/sys/arm/at91/at91_spireg.h 160358 2006-07-14 21:35:59Z imp $ */
26
27#ifndef ARM_AT91_AT91_SPIREG_H
28#define ARM_AT91_AT91_SPIREG_H
29
30#define SPI_CR 0x00 /* CR: Control Register */
31#define SPI_CR_SPIEN 0x1
32#define SPI_CR_SPIDIS 0x2
33#define SPI_CR_SWRST 0x8
34#define SPI_MR 0x04 /* MR: Mode Register */
35#define SPI_MR_MSTR 0x01
36#define SPI_MR_PS 0x02
37#define SPI_MR_PCSDEC 0x04
38#define SPI_MR_DIV32 0x08
39#define SPI_MR_MODFDIS 0x10
40#define SPI_MR_LLB 0x80
41#define SPI_MR_PSC_CS0 0xe0000
42#define SPI_MR_PSC_CS1 0xd0000
43#define SPI_MR_PSC_CS2 0xb0000
44#define SPI_MR_PSC_CS3 0x70000
45#define SPI_RDR 0x08 /* RDR: Receive Data Register */
46#define SPI_TDR 0x0c /* TDR: Transmit Data Register */
47#define SPI_SR 0x10 /* SR: Status Register */
48#define SPI_SR_RDRF 0x00001
49#define SPI_SR_TDRE 0x00002
50#define SPI_SR_MODF 0x00004
51#define SPI_SR_OVRES 0x00008
52#define SPI_SR_ENDRX 0x00010
53#define SPI_SR_ENDTX 0x00020
54#define SPI_SR_RXBUFE 0x00040
55#define SPI_SR_TXBUFE 0x00080
56#define SPI_SR_SPIENS 0x10000
57#define SPI_IER 0x14 /* IER: Interrupt Enable Regsiter */
58#define SPI_IDR 0x18 /* IDR: Interrupt Disable Regsiter */
59#define SPI_IMR 0x1c /* IMR: Interrupt Mask Regsiter */
60#define SPI_CSR0 0x30 /* CS0: Chip Select 0 */
61#define SPI_CSR_CPOL 0x01
62#define SPI_CSR1 0x34 /* CS1: Chip Select 1 */
63#define SPI_CSR2 0x38 /* CS2: Chip Select 2 */
64#define SPI_CSR3 0x3c /* CS3: Chip Select 3 */
65
66#endif /* ARM_AT91_AT91_SPIREG_H */
2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
--- 8 unchanged lines hidden (view full) ---
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 */
24
25/* $FreeBSD: head/sys/arm/at91/at91_spireg.h 160358 2006-07-14 21:35:59Z imp $ */
26
27#ifndef ARM_AT91_AT91_SPIREG_H
28#define ARM_AT91_AT91_SPIREG_H
29
30#define SPI_CR 0x00 /* CR: Control Register */
31#define SPI_CR_SPIEN 0x1
32#define SPI_CR_SPIDIS 0x2
33#define SPI_CR_SWRST 0x8
34#define SPI_MR 0x04 /* MR: Mode Register */
35#define SPI_MR_MSTR 0x01
36#define SPI_MR_PS 0x02
37#define SPI_MR_PCSDEC 0x04
38#define SPI_MR_DIV32 0x08
39#define SPI_MR_MODFDIS 0x10
40#define SPI_MR_LLB 0x80
41#define SPI_MR_PSC_CS0 0xe0000
42#define SPI_MR_PSC_CS1 0xd0000
43#define SPI_MR_PSC_CS2 0xb0000
44#define SPI_MR_PSC_CS3 0x70000
45#define SPI_RDR 0x08 /* RDR: Receive Data Register */
46#define SPI_TDR 0x0c /* TDR: Transmit Data Register */
47#define SPI_SR 0x10 /* SR: Status Register */
48#define SPI_SR_RDRF 0x00001
49#define SPI_SR_TDRE 0x00002
50#define SPI_SR_MODF 0x00004
51#define SPI_SR_OVRES 0x00008
52#define SPI_SR_ENDRX 0x00010
53#define SPI_SR_ENDTX 0x00020
54#define SPI_SR_RXBUFE 0x00040
55#define SPI_SR_TXBUFE 0x00080
56#define SPI_SR_SPIENS 0x10000
57#define SPI_IER 0x14 /* IER: Interrupt Enable Regsiter */
58#define SPI_IDR 0x18 /* IDR: Interrupt Disable Regsiter */
59#define SPI_IMR 0x1c /* IMR: Interrupt Mask Regsiter */
60#define SPI_CSR0 0x30 /* CS0: Chip Select 0 */
61#define SPI_CSR_CPOL 0x01
62#define SPI_CSR1 0x34 /* CS1: Chip Select 1 */
63#define SPI_CSR2 0x38 /* CS2: Chip Select 2 */
64#define SPI_CSR3 0x3c /* CS3: Chip Select 3 */
65
66#endif /* ARM_AT91_AT91_SPIREG_H */