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at91_machdep.c (238403) at91_machdep.c (238788)
1/*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without

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39 * Machine dependant functions for kernel setup
40 *
41 * This file needs a lot of work.
42 *
43 * Created : 17/09/94
44 */
45
46#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without

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39 * Machine dependant functions for kernel setup
40 *
41 * This file needs a lot of work.
42 *
43 * Created : 17/09/94
44 */
45
46#include <sys/cdefs.h>
47__FBSDID("$FreeBSD: head/sys/arm/at91/at91_machdep.c 238403 2012-07-12 19:11:37Z imp $");
47__FBSDID("$FreeBSD: head/sys/arm/at91/at91_machdep.c 238788 2012-07-26 08:01:25Z andrew $");
48
49#define _ARM32_BUS_DMA_PRIVATE
50#include <sys/param.h>
51#include <sys/systm.h>
52#include <sys/sysproto.h>
53#include <sys/signalvar.h>
54#include <sys/imgact.h>
55#include <sys/kernel.h>

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89#include <sys/reboot.h>
90
91#include <arm/at91/at91board.h>
92#include <arm/at91/at91var.h>
93#include <arm/at91/at91soc.h>
94#include <arm/at91/at91_usartreg.h>
95#include <arm/at91/at91rm92reg.h>
96#include <arm/at91/at91sam9g20reg.h>
48
49#define _ARM32_BUS_DMA_PRIVATE
50#include <sys/param.h>
51#include <sys/systm.h>
52#include <sys/sysproto.h>
53#include <sys/signalvar.h>
54#include <sys/imgact.h>
55#include <sys/kernel.h>

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89#include <sys/reboot.h>
90
91#include <arm/at91/at91board.h>
92#include <arm/at91/at91var.h>
93#include <arm/at91/at91soc.h>
94#include <arm/at91/at91_usartreg.h>
95#include <arm/at91/at91rm92reg.h>
96#include <arm/at91/at91sam9g20reg.h>
97#include <arm/at91/at91sam9g45reg.h>
97
98/* Page table for mapping proc0 zero page */
99#define KERNEL_PT_SYS 0
100#define KERNEL_PT_KERN 1
101#define KERNEL_PT_KERN_NUM 22
102/* L2 table for mapping after kernel */
103#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM
104#define KERNEL_PT_AFKERNEL_NUM 5

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196 {
197 /* EBI CS3 256MB */
198 AT91SAM9G20_NAND_BASE,
199 AT91SAM9G20_NAND_PA_BASE,
200 AT91SAM9G20_NAND_SIZE,
201 VM_PROT_READ|VM_PROT_WRITE,
202 PTE_NOCACHE,
203 },
98
99/* Page table for mapping proc0 zero page */
100#define KERNEL_PT_SYS 0
101#define KERNEL_PT_KERN 1
102#define KERNEL_PT_KERN_NUM 22
103/* L2 table for mapping after kernel */
104#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM
105#define KERNEL_PT_AFKERNEL_NUM 5

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197 {
198 /* EBI CS3 256MB */
199 AT91SAM9G20_NAND_BASE,
200 AT91SAM9G20_NAND_PA_BASE,
201 AT91SAM9G20_NAND_SIZE,
202 VM_PROT_READ|VM_PROT_WRITE,
203 PTE_NOCACHE,
204 },
205 /*
206 * The next should be good for the 9G45.
207 */
208 {
209 /* Internal Memory 1MB */
210 AT91SAM9G45_OHCI_BASE,
211 AT91SAM9G45_OHCI_PA_BASE,
212 0x00100000,
213 VM_PROT_READ|VM_PROT_WRITE,
214 PTE_NOCACHE,
215 },
204 { 0, 0, 0, 0, 0, }
205};
206
207#ifdef LINUX_BOOT_ABI
208extern int membanks;
209extern int memstart[];
210extern int memsize[];
211#endif
212
213long
214at91_ramsize(void)
215{
216 { 0, 0, 0, 0, 0, }
217};
218
219#ifdef LINUX_BOOT_ABI
220extern int membanks;
221extern int memstart[];
222extern int memsize[];
223#endif
224
225long
226at91_ramsize(void)
227{
216 uint32_t cr, mr, *SDRAMC;
228 uint32_t cr, mdr, mr, *SDRAMC;
217 int banks, rows, cols, bw;
218#ifdef LINUX_BOOT_ABI
219 /*
220 * If we found any ATAGs that were for memory, return the first bank.
221 */
222 if (membanks > 0)
223 return (memsize[0]);
224#endif
225
226 if (at91_is_rm92()) {
227 SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
228 cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
229 mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
230 banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
231 rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
232 cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
233 bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
229 int banks, rows, cols, bw;
230#ifdef LINUX_BOOT_ABI
231 /*
232 * If we found any ATAGs that were for memory, return the first bank.
233 */
234 if (membanks > 0)
235 return (memsize[0]);
236#endif
237
238 if (at91_is_rm92()) {
239 SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
240 cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
241 mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
242 banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
243 rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
244 cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
245 bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
246 } else if (at91_cpu_is(AT91_T_SAM9G45)) {
247 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G45_DDRSDRC0_BASE);
248 cr = SDRAMC[AT91SAM9G45_DDRSDRC_CR / 4];
249 mdr = SDRAMC[AT91SAM9G45_DDRSDRC_MDR / 4];
250 banks = 0;
251 rows = ((cr & AT91SAM9G45_DDRSDRC_CR_NR_MASK) >> 2) + 11;
252 cols = (cr & AT91SAM9G45_DDRSDRC_CR_NC_MASK) + 8;
253 bw = (mdr & AT91SAM9G45_DDRSDRC_MDR_DBW_16) ? 1 : 2;
254
255 /* Fix the calculation for DDR memory */
256 mdr &= AT91SAM9G45_DDRSDRC_MDR_MASK;
257 if (mdr & AT91SAM9G45_DDRSDRC_MDR_LPDDR1 ||
258 mdr & AT91SAM9G45_DDRSDRC_MDR_DDR2) {
259 /* The cols value is 1 higher for DDR */
260 cols += 1;
261 /* DDR has 4 internal banks. */
262 banks = 2;
263 }
234 } else {
235 /*
236 * This should be good for the 9260, 9261, 9G20, 9G35 and 9X25
237 * as addresses and registers are the same.
238 */
239 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE);
240 cr = SDRAMC[AT91SAM9G20_SDRAMC_CR / 4];
241 mr = SDRAMC[AT91SAM9G20_SDRAMC_MR / 4];

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265 /*
266 * This should be good for the 9260, 9261, 9G20, 9G35 and 9X25
267 * as addresses and registers are the same.
268 */
269 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE);
270 cr = SDRAMC[AT91SAM9G20_SDRAMC_CR / 4];
271 mr = SDRAMC[AT91SAM9G20_SDRAMC_MR / 4];

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