1/*-
2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@gmail.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/arm/allwinner/timer.c 247463 2013-02-28 13:46:03Z mav $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/kernel.h>
34#include <sys/module.h>
35#include <sys/malloc.h>
36#include <sys/rman.h>

--- 10 unchanged lines hidden (view full) ---

47#include <dev/ofw/ofw_bus.h>
48#include <dev/ofw/ofw_bus_subr.h>
49
50#include <machine/bus.h>
51#include <machine/fdt.h>
52
53#include <sys/kdb.h>
54
55/**
56 * Timer registers addr
57 *
58 */
59#define SW_TIMER_IRQ_EN_REG 0x00
60#define SW_TIMER_IRQ_STA_REG 0x04
61#define SW_TIMER0_CTRL_REG 0x10
62#define SW_TIMER0_INT_VALUE_REG 0x14

--- 16 unchanged lines hidden (view full) ---

79 device_t sc_dev;
80 struct resource *res[2];
81 bus_space_tag_t sc_bst;
82 bus_space_handle_t sc_bsh;
83 void *sc_ih; /* interrupt handler */
84 uint32_t sc_period;
85 uint32_t timer0_freq;
86 struct eventtimer et;
87};
88
89int a10_timer_get_timerfreq(struct a10_timer_softc *);
90
91#define timer_read_4(sc, reg) \
92 bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg)
93#define timer_write_4(sc, reg, val) \
94 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val)

--- 26 unchanged lines hidden (view full) ---

121 { -1, 0 }
122};
123
124static uint64_t
125timer_read_counter64(void)
126{
127 uint32_t lo, hi;
128
129 /* Latch counter, wait for it to be ready to read. */
130 timer_write_4(a10_timer_sc, CNT64_CTRL_REG, CNT64_RL_EN);
131 while (timer_read_4(a10_timer_sc, CNT64_CTRL_REG) & CNT64_RL_EN)
132 continue;
133
134 hi = timer_read_4(a10_timer_sc, SW_COUNTER64HI_REG);
135 lo = timer_read_4(a10_timer_sc, SW_COUNTER64LO_REG);
136
137 return (((uint64_t)hi << 32) | lo);
138}
139
140static int
141a10_timer_probe(device_t dev)
142{
143
144 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-timer"))
145 return (ENXIO);
146
147 device_set_desc(dev, "Allwinner A10 timer");
148 return (BUS_PROBE_DEFAULT);
149}
150
151static int
152a10_timer_attach(device_t dev)
153{
154 struct a10_timer_softc *sc;
155 int err;

--- 215 unchanged lines hidden ---