1/*-
2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@gmail.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/arm/allwinner/timer.c 254056 2013-08-07 11:07:56Z ganbold $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/kernel.h>
34#include <sys/module.h>
35#include <sys/malloc.h>
36#include <sys/rman.h>

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47#include <dev/ofw/ofw_bus.h>
48#include <dev/ofw/ofw_bus_subr.h>
49
50#include <machine/bus.h>
51#include <machine/fdt.h>
52
53#include <sys/kdb.h>
54
55#include "a20/a20_cpu_cfg.h"
56
57/**
58 * Timer registers addr
59 *
60 */
61#define SW_TIMER_IRQ_EN_REG 0x00
62#define SW_TIMER_IRQ_STA_REG 0x04
63#define SW_TIMER0_CTRL_REG 0x10
64#define SW_TIMER0_INT_VALUE_REG 0x14

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81 device_t sc_dev;
82 struct resource *res[2];
83 bus_space_tag_t sc_bst;
84 bus_space_handle_t sc_bsh;
85 void *sc_ih; /* interrupt handler */
86 uint32_t sc_period;
87 uint32_t timer0_freq;
88 struct eventtimer et;
89 uint8_t sc_timer_type; /* 0 for A10, 1 for A20 */
90};
91
92int a10_timer_get_timerfreq(struct a10_timer_softc *);
93
94#define timer_read_4(sc, reg) \
95 bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg)
96#define timer_write_4(sc, reg, val) \
97 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val)

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124 { -1, 0 }
125};
126
127static uint64_t
128timer_read_counter64(void)
129{
130 uint32_t lo, hi;
131
132 /* In case of A20 get appropriate counter info */
133 if (a10_timer_sc->sc_timer_type)
134 return (a20_read_counter64());
135
136 /* Latch counter, wait for it to be ready to read. */
137 timer_write_4(a10_timer_sc, CNT64_CTRL_REG, CNT64_RL_EN);
138 while (timer_read_4(a10_timer_sc, CNT64_CTRL_REG) & CNT64_RL_EN)
139 continue;
140
141 hi = timer_read_4(a10_timer_sc, SW_COUNTER64HI_REG);
142 lo = timer_read_4(a10_timer_sc, SW_COUNTER64LO_REG);
143
144 return (((uint64_t)hi << 32) | lo);
145}
146
147static int
148a10_timer_probe(device_t dev)
149{
150 struct a10_timer_softc *sc;
151
152 sc = device_get_softc(dev);
153
154 if (ofw_bus_is_compatible(dev, "allwinner,sun4i-timer"))
155 sc->sc_timer_type = 0;
156 else if (ofw_bus_is_compatible(dev, "allwinner,sun7i-timer"))
157 sc->sc_timer_type = 1;
158 else
159 return (ENXIO);
160
161 device_set_desc(dev, "Allwinner A10/A20 timer");
162 return (BUS_PROBE_DEFAULT);
163}
164
165static int
166a10_timer_attach(device_t dev)
167{
168 struct a10_timer_softc *sc;
169 int err;

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