| vmcb.h (271346) | vmcb.h (271348) |
|---|---|
| 1/*- 2 * Copyright (c) 2013 Anish Gupta (akgupt3@gmail.com) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2013 Anish Gupta (akgupt3@gmail.com) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: projects/bhyve_svm/sys/amd64/vmm/amd/vmcb.h 271346 2014-09-10 02:35:19Z neel $ | 26 * $FreeBSD: projects/bhyve_svm/sys/amd64/vmm/amd/vmcb.h 271348 2014-09-10 03:13:40Z neel $ |
| 27 */ 28 29#ifndef _VMCB_H_ 30#define _VMCB_H_ 31 32/* 33 * Secure Virtual Machine: AMD64 Programmer's Manual Vol2, Chapter 15 34 * Layout of VMCB: AMD64 Programmer's Manual Vol2, Appendix B 35 */ 36 | 27 */ 28 29#ifndef _VMCB_H_ 30#define _VMCB_H_ 31 32/* 33 * Secure Virtual Machine: AMD64 Programmer's Manual Vol2, Chapter 15 34 * Layout of VMCB: AMD64 Programmer's Manual Vol2, Appendix B 35 */ 36 |
| 37/* VMCB Control offset 0xC */ | 37/* vmcb_ctrl->intercept[] array indices */ 38#define VMCB_CR_INTCPT 0 39#define VMCB_DR_INTCPT 1 40#define VMCB_EXC_INTCPT 2 41#define VMCB_CTRL1_INTCPT 3 42#define VMCB_CTRL2_INTCPT 4 43 44/* intercept[VMCB_CTRL1_INTCPT] fields */ |
| 38#define VMCB_INTCPT_INTR BIT(0) 39#define VMCB_INTCPT_NMI BIT(1) 40#define VMCB_INTCPT_SMI BIT(2) 41#define VMCB_INTCPT_INIT BIT(3) 42#define VMCB_INTCPT_VINTR BIT(4) 43#define VMCB_INTCPT_CR0_WRITE BIT(5) 44#define VMCB_INTCPT_IDTR_READ BIT(6) 45#define VMCB_INTCPT_GDTR_READ BIT(7) --- 17 unchanged lines hidden (view full) --- 63#define VMCB_INTCPT_INVPG BIT(25) 64#define VMCB_INTCPT_INVPGA BIT(26) 65#define VMCB_INTCPT_IO BIT(27) 66#define VMCB_INTCPT_MSR BIT(28) 67#define VMCB_INTCPT_TASK_SWITCH BIT(29) 68#define VMCB_INTCPT_FERR_FREEZE BIT(30) 69#define VMCB_INTCPT_SHUTDOWN BIT(31) 70 | 45#define VMCB_INTCPT_INTR BIT(0) 46#define VMCB_INTCPT_NMI BIT(1) 47#define VMCB_INTCPT_SMI BIT(2) 48#define VMCB_INTCPT_INIT BIT(3) 49#define VMCB_INTCPT_VINTR BIT(4) 50#define VMCB_INTCPT_CR0_WRITE BIT(5) 51#define VMCB_INTCPT_IDTR_READ BIT(6) 52#define VMCB_INTCPT_GDTR_READ BIT(7) --- 17 unchanged lines hidden (view full) --- 70#define VMCB_INTCPT_INVPG BIT(25) 71#define VMCB_INTCPT_INVPGA BIT(26) 72#define VMCB_INTCPT_IO BIT(27) 73#define VMCB_INTCPT_MSR BIT(28) 74#define VMCB_INTCPT_TASK_SWITCH BIT(29) 75#define VMCB_INTCPT_FERR_FREEZE BIT(30) 76#define VMCB_INTCPT_SHUTDOWN BIT(31) 77 |
| 71/* VMCB Control offset 0x10 */ | 78/* intercept[VMCB_CTRL2_INTCPT] fields */ |
| 72#define VMCB_INTCPT_VMRUN BIT(0) 73#define VMCB_INTCPT_VMMCALL BIT(1) 74#define VMCB_INTCPT_VMLOAD BIT(2) 75#define VMCB_INTCPT_VMSAVE BIT(3) 76#define VMCB_INTCPT_STGI BIT(4) 77#define VMCB_INTCPT_CLGI BIT(5) 78#define VMCB_INTCPT_SKINIT BIT(6) 79#define VMCB_INTCPT_RDTSCP BIT(7) --- 6 unchanged lines hidden (view full) --- 86 87/* VMCB TLB control */ 88#define VMCB_TLB_FLUSH_NOTHING 0 /* Flush nothing */ 89#define VMCB_TLB_FLUSH_ALL 1 /* Flush entire TLB */ 90#define VMCB_TLB_FLUSH_GUEST 3 /* Flush all guest entries */ 91#define VMCB_TLB_FLUSH_GUEST_NONGLOBAL 7 /* Flush guest non-PG entries */ 92 93/* VMCB state caching */ | 79#define VMCB_INTCPT_VMRUN BIT(0) 80#define VMCB_INTCPT_VMMCALL BIT(1) 81#define VMCB_INTCPT_VMLOAD BIT(2) 82#define VMCB_INTCPT_VMSAVE BIT(3) 83#define VMCB_INTCPT_STGI BIT(4) 84#define VMCB_INTCPT_CLGI BIT(5) 85#define VMCB_INTCPT_SKINIT BIT(6) 86#define VMCB_INTCPT_RDTSCP BIT(7) --- 6 unchanged lines hidden (view full) --- 93 94/* VMCB TLB control */ 95#define VMCB_TLB_FLUSH_NOTHING 0 /* Flush nothing */ 96#define VMCB_TLB_FLUSH_ALL 1 /* Flush entire TLB */ 97#define VMCB_TLB_FLUSH_GUEST 3 /* Flush all guest entries */ 98#define VMCB_TLB_FLUSH_GUEST_NONGLOBAL 7 /* Flush guest non-PG entries */ 99 100/* VMCB state caching */ |
| 94#define VMCB_CACHE_NONE 0 /* No caching */ 95#define VMCB_CACHE_I BIT(0) /* Cache vectors, TSC offset */ 96#define VMCB_CACHE_IOPM BIT(1) /* I/O and MSR permission */ 97#define VMCB_CACHE_ASID BIT(2) /* ASID */ 98#define VMCB_CACHE_TPR BIT(3) /* V_TPR to V_INTR_VECTOR */ 99#define VMCB_CACHE_NP BIT(4) /* Nested Paging */ 100#define VMCB_CACHE_CR BIT(5) /* CR0, CR3, CR4 & EFER */ 101#define VMCB_CACHE_DR BIT(6) /* Debug registers */ 102#define VMCB_CACHE_DT BIT(7) /* GDT/IDT */ 103#define VMCB_CACHE_SEG BIT(8) /* User segments, CPL */ 104#define VMCB_CACHE_CR2 BIT(9) /* page fault address */ 105#define VMCB_CACHE_LBR BIT(10) /* Last branch */ | 101#define VMCB_CACHE_NONE 0 /* No caching */ 102#define VMCB_CACHE_I BIT(0) /* Intercept, TSC off, Pause filter */ 103#define VMCB_CACHE_IOPM BIT(1) /* I/O and MSR permission */ 104#define VMCB_CACHE_ASID BIT(2) /* ASID */ 105#define VMCB_CACHE_TPR BIT(3) /* V_TPR to V_INTR_VECTOR */ 106#define VMCB_CACHE_NP BIT(4) /* Nested Paging */ 107#define VMCB_CACHE_CR BIT(5) /* CR0, CR3, CR4 & EFER */ 108#define VMCB_CACHE_DR BIT(6) /* Debug registers */ 109#define VMCB_CACHE_DT BIT(7) /* GDT/IDT */ 110#define VMCB_CACHE_SEG BIT(8) /* User segments, CPL */ 111#define VMCB_CACHE_CR2 BIT(9) /* page fault address */ 112#define VMCB_CACHE_LBR BIT(10) /* Last branch */ |
| 106 107/* VMCB control event injection */ 108#define VMCB_EVENTINJ_EC_VALID BIT(11) /* Error Code valid */ 109#define VMCB_EVENTINJ_VALID BIT(31) /* Event valid */ 110 111/* Event types that can be injected */ 112#define VMCB_EVENTINJ_TYPE_INTR 0 113#define VMCB_EVENTINJ_TYPE_NMI 2 --- 56 unchanged lines hidden (view full) --- 170/* 171 * The VMCB is divided into two areas - the first one contains various 172 * control bits including the intercept vector and the second one contains 173 * the guest state. 174 */ 175 176/* VMCB control area - padded up to 1024 bytes */ 177struct vmcb_ctrl { | 113 114/* VMCB control event injection */ 115#define VMCB_EVENTINJ_EC_VALID BIT(11) /* Error Code valid */ 116#define VMCB_EVENTINJ_VALID BIT(31) /* Event valid */ 117 118/* Event types that can be injected */ 119#define VMCB_EVENTINJ_TYPE_INTR 0 120#define VMCB_EVENTINJ_TYPE_NMI 2 --- 56 unchanged lines hidden (view full) --- 177/* 178 * The VMCB is divided into two areas - the first one contains various 179 * control bits including the intercept vector and the second one contains 180 * the guest state. 181 */ 182 183/* VMCB control area - padded up to 1024 bytes */ 184struct vmcb_ctrl { |
| 178 uint16_t cr_read; /* Offset 0, CR0-15 read/write */ 179 uint16_t cr_write; 180 uint16_t dr_read; /* Offset 4, DR0-DR15 */ 181 uint16_t dr_write; 182 uint32_t exception; /* Offset 8, bit mask for exceptions. */ 183 uint32_t ctrl1; /* Offset 0xC, intercept events1 */ 184 uint32_t ctrl2; /* Offset 0x10, intercept event2 */ | 185 uint32_t intercept[5]; /* all intercepts */ |
| 185 uint8_t pad1[0x28]; /* Offsets 0x14-0x3B are reserved. */ 186 uint16_t pause_filthresh; /* Offset 0x3C, PAUSE filter threshold */ 187 uint16_t pause_filcnt; /* Offset 0x3E, PAUSE filter count */ 188 uint64_t iopm_base_pa; /* 0x40: IOPM_BASE_PA */ 189 uint64_t msrpm_base_pa; /* 0x48: MSRPM_BASE_PA */ 190 uint64_t tsc_offset; /* 0x50: TSC_OFFSET */ 191 uint32_t asid; /* 0x58: Guest ASID */ 192 uint8_t tlb_ctrl; /* 0x5C: TLB_CONTROL */ --- 92 unchanged lines hidden --- | 186 uint8_t pad1[0x28]; /* Offsets 0x14-0x3B are reserved. */ 187 uint16_t pause_filthresh; /* Offset 0x3C, PAUSE filter threshold */ 188 uint16_t pause_filcnt; /* Offset 0x3E, PAUSE filter count */ 189 uint64_t iopm_base_pa; /* 0x40: IOPM_BASE_PA */ 190 uint64_t msrpm_base_pa; /* 0x48: MSRPM_BASE_PA */ 191 uint64_t tsc_offset; /* 0x50: TSC_OFFSET */ 192 uint32_t asid; /* 0x58: Guest ASID */ 193 uint8_t tlb_ctrl; /* 0x5C: TLB_CONTROL */ --- 92 unchanged lines hidden --- |