| specialreg.h (34031) | specialreg.h (40003) |
|---|---|
| 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 |
| 34 * $Id: specialreg.h,v 1.14 1997/07/21 17:53:51 fsmp Exp $ | 34 * $Id: specialreg.h,v 1.15 1998/03/04 11:39:16 kato Exp $ |
| 35 */ 36 37#ifndef _MACHINE_SPECIALREG_H_ 38#define _MACHINE_SPECIALREG_H_ 39 40/* 41 * Bits in 386 special registers: 42 */ --- 210 unchanged lines hidden (view full) --- 253#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 254#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 255#define RCR_WWO 0x02 /* Weak write ordering. */ 256#define RCR_WL 0x04 /* Weak locking. */ 257#define RCR_WG 0x08 /* Write gathering. */ 258#define RCR_WT 0x10 /* Write-through. */ 259#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 260 | 35 */ 36 37#ifndef _MACHINE_SPECIALREG_H_ 38#define _MACHINE_SPECIALREG_H_ 39 40/* 41 * Bits in 386 special registers: 42 */ --- 210 unchanged lines hidden (view full) --- 253#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 254#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 255#define RCR_WWO 0x02 /* Weak write ordering. */ 256#define RCR_WL 0x04 /* Weak locking. */ 257#define RCR_WG 0x08 /* Write gathering. */ 258#define RCR_WT 0x10 /* Write-through. */ 259#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 260 |
| 261/* AMD Write Allocate Top-Of-Memory and Control Register */ 262#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 263#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 264#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ |
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| 261 | 265 |
| 266 |
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| 262#ifndef LOCORE 263static __inline u_char 264read_cyrix_reg(u_char reg) 265{ 266 outb(0x22, reg); 267 return inb(0x23); 268} 269 270static __inline void 271write_cyrix_reg(u_char reg, u_char data) 272{ 273 outb(0x22, reg); 274 outb(0x23, data); 275} 276#endif 277 278#endif /* !_MACHINE_SPECIALREG_H_ */ | 267#ifndef LOCORE 268static __inline u_char 269read_cyrix_reg(u_char reg) 270{ 271 outb(0x22, reg); 272 return inb(0x23); 273} 274 275static __inline void 276write_cyrix_reg(u_char reg, u_char data) 277{ 278 outb(0x22, reg); 279 outb(0x23, data); 280} 281#endif 282 283#endif /* !_MACHINE_SPECIALREG_H_ */ |