| pmc.sandybridge.3 (233628) | pmc.sandybridge.3 (240164) |
|---|---|
| 1.\" Copyright (c) 2012 Davide Italiano <davide@FreeBSD.org> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. --- 8 unchanged lines hidden (view full) --- 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" | 1.\" Copyright (c) 2012 Davide Italiano <davide@FreeBSD.org> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. --- 8 unchanged lines hidden (view full) --- 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" |
| 25.\" $FreeBSD: head/lib/libpmc/pmc.sandybridge.3 233628 2012-03-28 20:58:30Z fabient $ | 25.\" $FreeBSD: head/lib/libpmc/pmc.sandybridge.3 240164 2012-09-06 13:54:01Z fabient $ |
| 26.\" 27.Dd February 12, 2012 28.Dt PMC.SANDYBRIDGE 3 29.Os 30.Sh NAME 31.Nm pmc.sandybridge 32.Nd measurement events for 33.Tn Intel --- 54 unchanged lines hidden (view full) --- 88.El 89.Ss Event Qualifiers 90Event specifiers for these PMCs support the following common 91qualifiers: 92.Bl -tag -width indent 93.It Li rsp= Ns Ar value 94Configure the Off-core Response bits. 95.Bl -tag -width indent | 26.\" 27.Dd February 12, 2012 28.Dt PMC.SANDYBRIDGE 3 29.Os 30.Sh NAME 31.Nm pmc.sandybridge 32.Nd measurement events for 33.Tn Intel --- 54 unchanged lines hidden (view full) --- 88.El 89.Ss Event Qualifiers 90Event specifiers for these PMCs support the following common 91qualifiers: 92.Bl -tag -width indent 93.It Li rsp= Ns Ar value 94Configure the Off-core Response bits. 95.Bl -tag -width indent |
| 96.It Li DMND_DATA_RD 97Counts the number of demand and DCU prefetch data reads of full 98and partial cachelines as well as demand data page table entry 99cacheline reads. 100Does not count L2 data read prefetches or instruction fetches. 101.It Li DMND_RFO 102Counts the number of demand and DCU prefetch reads for ownership 103(RFO) requests generated by a write to data cacheline. 104Does not count L2 RFO. 105.It Li DMND_IFETCH 106Counts the number of demand and DCU prefetch instruction cacheline 107reads. | 96.It Li REQ_DMND_DATA_RD 97Counts the number of demand and DCU prefetch data reads of full and partial 98cachelines as well as demand data page table entry cacheline reads. Does not 99count L2 data read prefetches or instruction fetches. 100.It Li REQ_DMND_RFO 101Counts the number of demand and DCU prefetch reads for ownership (RFO) 102requests generated by a write to data cacheline. Does not count L2 RFO 103prefetches. 104.It Li REQ_DMND_IFETCH 105Counts the number of demand and DCU prefetch instruction cacheline reads. |
| 108Does not count L2 code read prefetches. | 106Does not count L2 code read prefetches. |
| 109.It Li WB | 107.It Li REQ_WB |
| 110Counts the number of writeback (modified to exclusive) transactions. | 108Counts the number of writeback (modified to exclusive) transactions. |
| 111.It Li PF_DATA_RD | 109.It Li REQ_PF_DATA_RD |
| 112Counts the number of data cacheline reads generated by L2 prefetchers. | 110Counts the number of data cacheline reads generated by L2 prefetchers. |
| 113.It Li PF_RFO | 111.It Li REQ_PF_RFO |
| 114Counts the number of RFO requests generated by L2 prefetchers. | 112Counts the number of RFO requests generated by L2 prefetchers. |
| 115.It Li PF_IFETCH | 113.It Li REQ_PF_IFETCH |
| 116Counts the number of code reads generated by L2 prefetchers. | 114Counts the number of code reads generated by L2 prefetchers. |
| 117.It Li OTHER 118Counts one of the following transaction types, including L3 invalidate, 119I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, 120lock, unlock, split lock. 121.It Li UNCORE_HIT 122L3 Hit: local or remote home requests that hit L3 cache in the uncore 123with no coherency actions required (snooping). 124.It Li OTHER_CORE_HIT_SNP 125L3 Hit: local or remote home requests that hit L3 cache in the uncore 126and was serviced by another core with a cross core snoop where no modified 127copies were found (clean). 128.It Li OTHER_CORE_HITM 129L3 Hit: local or remote home requests that hit L3 cache in the uncore 130and was serviced by another core with a cross core snoop where modified 131copies were found (HITM). 132.It Li REMOTE_CACHE_FWD 133L3 Miss: local homed requests that missed the L3 cache and was serviced 134by forwarded data following a cross package snoop where no modified 135copies found. 136(Remote home requests are not counted) 137.It Li REMOTE_DRAM 138L3 Miss: remote home requests that missed the L3 cache and were serviced 139by remote DRAM. 140.It Li LOCAL_DRAM 141L3 Miss: local home requests that missed the L3 cache and were serviced 142by local DRAM. 143.It Li NON_DRAM 144Non-DRAM requests that were serviced by IOH. | 115.It Li REQ_PF_LLC_DATA_RD 116L2 prefetcher to L3 for loads. 117.It Li REQ_PF_LLC_RFO 118RFO requests generated by L2 prefetcher 119.It Li REQ_PF_LLC_IFETCH 120L2 prefetcher to L3 for instruction fetches. 121.It Li REQ_BUS_LOCKS 122Bus lock and split lock requests. 123.It Li REQ_STRM_ST 124Streaming store requests. 125.It Li REQ_OTHER 126Any other request that crosses IDI, including I/O. 127.It Li RES_ANY 128Catch all value for any response types. 129.It Li RES_SUPPLIER_NO_SUPP 130No Supplier Information available. 131.It Li RES_SUPPLIER_LLC_HITM 132M-state initial lookup stat in L3. 133.It Li RES_SUPPLIER_LLC_HITE 134E-state. 135.It Li RES_SUPPLIER_LLC_HITS 136S-state. 137.It Li RES_SUPPLIER_LLC_HITF 138F-state. 139.It Li RES_SUPPLIER_LOCAL 140Local DRAM Controller. 141.It Li RES_SNOOP_SNPI_NONE 142No details on snoop-related information. 143.It Li RES_SNOOP_SNP_NO_NEEDED 144No snoop was needed to satisfy the request. 145.It Li RES_SNOOP_SNP_MISS 146A snoop was needed and it missed all snooped caches: 147-For LLC Hit, ReslHitl was returned by all cores 148-For LLC Miss, Rspl was returned by all sockets and data was returned from 149DRAM. 150.It Li RES_SNOOP_HIT_NO_FWD 151A snoop was needed and it hits in at least one snooped cache. Hit denotes a 152cache-line was valid before snoop effect. This includes: 153-Snoop Hit w/ Invalidation (LLC Hit, RFO) 154-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 155-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 156In the LLC Miss case, data is returned from DRAM. 157.It Li RES_SNOOP_HIT_FWD 158A snoop was needed and data was forwarded from a remote socket. 159This includes: 160-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 161.It Li RES_SNOOP_HITM 162A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a 163cache-line was in modified state before effect as a results of snoop. This 164includes: 165-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) 166-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 167-Snoop MtoS (LLC Hit, IFetch/Data_RD). 168.It Li RES_NON_DRAM 169Target was non-DRAM system address. This includes MMIO transactions. |
| 145.El 146.It Li cmask= Ns Ar value 147Configure the PMC to increment only if the number of configured 148events measured in a cycle is greater than or equal to 149.Ar value . 150.It Li edge 151Configure the PMC to count the number of de-asserted to asserted 152transitions of the conditions expressed by the other qualifiers. --- 780 unchanged lines hidden --- | 170.El 171.It Li cmask= Ns Ar value 172Configure the PMC to increment only if the number of configured 173events measured in a cycle is greater than or equal to 174.Ar value . 175.It Li edge 176Configure the PMC to count the number of de-asserted to asserted 177transitions of the conditions expressed by the other qualifiers. --- 780 unchanged lines hidden --- |