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libpmc.c (204635) libpmc.c (206089)
1/*-
2 * Copyright (c) 2003-2008 Joseph Koshy
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2003-2008 Joseph Koshy
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/lib/libpmc/libpmc.c 204635 2010-03-03 15:05:58Z gnn $");
28__FBSDID("$FreeBSD: head/lib/libpmc/libpmc.c 206089 2010-04-02 13:23:49Z fabient $");
29
30#include <sys/types.h>
31#include <sys/module.h>
32#include <sys/pmc.h>
33#include <sys/syscall.h>
34
35#include <ctype.h>
36#include <errno.h>

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49static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
50 struct pmc_op_pmcallocate *_pmc_config);
51#endif
52#if defined(__amd64__) || defined(__i386__)
53static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
54 struct pmc_op_pmcallocate *_pmc_config);
55static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
56 struct pmc_op_pmcallocate *_pmc_config);
29
30#include <sys/types.h>
31#include <sys/module.h>
32#include <sys/pmc.h>
33#include <sys/syscall.h>
34
35#include <ctype.h>
36#include <errno.h>

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49static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
50 struct pmc_op_pmcallocate *_pmc_config);
51#endif
52#if defined(__amd64__) || defined(__i386__)
53static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
54 struct pmc_op_pmcallocate *_pmc_config);
55static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
56 struct pmc_op_pmcallocate *_pmc_config);
57static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
58 struct pmc_op_pmcallocate *_pmc_config);
59static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
60 struct pmc_op_pmcallocate *_pmc_config);
57static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
58 struct pmc_op_pmcallocate *_pmc_config);
59static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
60 struct pmc_op_pmcallocate *_pmc_config);
61#endif
62#if defined(__i386__)
63static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
64 struct pmc_op_pmcallocate *_pmc_config);

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139PMC_CLASSDEP_TABLE(iaf, IAF);
140PMC_CLASSDEP_TABLE(k7, K7);
141PMC_CLASSDEP_TABLE(k8, K8);
142PMC_CLASSDEP_TABLE(p4, P4);
143PMC_CLASSDEP_TABLE(p5, P5);
144PMC_CLASSDEP_TABLE(p6, P6);
145PMC_CLASSDEP_TABLE(xscale, XSCALE);
146PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
61static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
62 struct pmc_op_pmcallocate *_pmc_config);
63static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
64 struct pmc_op_pmcallocate *_pmc_config);
65#endif
66#if defined(__i386__)
67static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
68 struct pmc_op_pmcallocate *_pmc_config);

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143PMC_CLASSDEP_TABLE(iaf, IAF);
144PMC_CLASSDEP_TABLE(k7, K7);
145PMC_CLASSDEP_TABLE(k8, K8);
146PMC_CLASSDEP_TABLE(p4, P4);
147PMC_CLASSDEP_TABLE(p5, P5);
148PMC_CLASSDEP_TABLE(p6, P6);
149PMC_CLASSDEP_TABLE(xscale, XSCALE);
150PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
151PMC_CLASSDEP_TABLE(ucf, UCF);
147
148#undef __PMC_EV_ALIAS
149#define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE },
150
151static const struct pmc_event_descr atom_event_table[] =
152{
153 __PMC_EV_ALIAS_ATOM()
154};

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164 __PMC_EV_ALIAS_CORE2()
165};
166
167static const struct pmc_event_descr corei7_event_table[] =
168{
169 __PMC_EV_ALIAS_COREI7()
170};
171
152
153#undef __PMC_EV_ALIAS
154#define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE },
155
156static const struct pmc_event_descr atom_event_table[] =
157{
158 __PMC_EV_ALIAS_ATOM()
159};

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169 __PMC_EV_ALIAS_CORE2()
170};
171
172static const struct pmc_event_descr corei7_event_table[] =
173{
174 __PMC_EV_ALIAS_COREI7()
175};
176
177static const struct pmc_event_descr westmere_event_table[] =
178{
179 __PMC_EV_ALIAS_WESTMERE()
180};
181
182static const struct pmc_event_descr corei7uc_event_table[] =
183{
184 __PMC_EV_ALIAS_COREI7UC()
185};
186
187static const struct pmc_event_descr westmereuc_event_table[] =
188{
189 __PMC_EV_ALIAS_WESTMEREUC()
190};
191
172/*
173 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...)
174 *
175 * Map a CPU to the PMC classes it supports.
176 */
177#define PMC_MDEP_TABLE(N,C,...) \
178 static const enum pmc_class N##_pmc_classes[] = { \
179 PMC_CLASS_##C, __VA_ARGS__ \
180 }
181
182PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC);
183PMC_MDEP_TABLE(core, IAP, PMC_CLASS_TSC);
184PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC);
192/*
193 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...)
194 *
195 * Map a CPU to the PMC classes it supports.
196 */
197#define PMC_MDEP_TABLE(N,C,...) \
198 static const enum pmc_class N##_pmc_classes[] = { \
199 PMC_CLASS_##C, __VA_ARGS__ \
200 }
201
202PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC);
203PMC_MDEP_TABLE(core, IAP, PMC_CLASS_TSC);
204PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC);
185PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC);
205PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
206PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
186PMC_MDEP_TABLE(k7, K7, PMC_CLASS_TSC);
187PMC_MDEP_TABLE(k8, K8, PMC_CLASS_TSC);
188PMC_MDEP_TABLE(p4, P4, PMC_CLASS_TSC);
189PMC_MDEP_TABLE(p5, P5, PMC_CLASS_TSC);
190PMC_MDEP_TABLE(p6, P6, PMC_CLASS_TSC);
191PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_XSCALE);
192PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_MIPS24K);
193

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210 }
211
212#if defined(__i386__) || defined(__amd64__)
213PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf);
214PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
215PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
216PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
217PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
207PMC_MDEP_TABLE(k7, K7, PMC_CLASS_TSC);
208PMC_MDEP_TABLE(k8, K8, PMC_CLASS_TSC);
209PMC_MDEP_TABLE(p4, P4, PMC_CLASS_TSC);
210PMC_MDEP_TABLE(p5, P5, PMC_CLASS_TSC);
211PMC_MDEP_TABLE(p6, P6, PMC_CLASS_TSC);
212PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_XSCALE);
213PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_MIPS24K);
214

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231 }
232
233#if defined(__i386__) || defined(__amd64__)
234PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf);
235PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
236PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
237PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
238PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
239PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
240PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
241PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
242PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
218#endif
219#if defined(__i386__)
220PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
221#endif
222#if defined(__i386__) || defined(__amd64__)
223PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
224PMC_CLASS_TABLE_DESC(p4, P4, p4, p4);
225#endif

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297static struct pmc_cpuinfo cpu_info; /* filled in by pmc_init() */
298
299/* Event masks for events */
300struct pmc_masks {
301 const char *pm_name;
302 const uint32_t pm_value;
303};
304#define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) }
243#endif
244#if defined(__i386__)
245PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
246#endif
247#if defined(__i386__) || defined(__amd64__)
248PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
249PMC_CLASS_TABLE_DESC(p4, P4, p4, p4);
250#endif

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322static struct pmc_cpuinfo cpu_info; /* filled in by pmc_init() */
323
324/* Event masks for events */
325struct pmc_masks {
326 const char *pm_name;
327 const uint32_t pm_value;
328};
329#define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) }
305#define NULLMASK PMCMASK(NULL,0)
330#define NULLMASK { .pm_name = NULL }
306
307#if defined(__amd64__) || defined(__i386__)
308static int
309pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint32_t *evmask)
310{
311 const struct pmc_masks *pm;
312 char *q, *r;
313 int c;

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490 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"),
491 EV_ALIAS(NULL, NULL)
492};
493
494#define atom_aliases core2_aliases
495#define atom_aliases_without_iaf core2_aliases_without_iaf
496#define corei7_aliases core2_aliases
497#define corei7_aliases_without_iaf core2_aliases_without_iaf
331
332#if defined(__amd64__) || defined(__i386__)
333static int
334pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint32_t *evmask)
335{
336 const struct pmc_masks *pm;
337 char *q, *r;
338 int c;

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515 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"),
516 EV_ALIAS(NULL, NULL)
517};
518
519#define atom_aliases core2_aliases
520#define atom_aliases_without_iaf core2_aliases_without_iaf
521#define corei7_aliases core2_aliases
522#define corei7_aliases_without_iaf core2_aliases_without_iaf
523#define westmere_aliases core2_aliases
524#define westmere_aliases_without_iaf core2_aliases_without_iaf
498
499#define IAF_KW_OS "os"
500#define IAF_KW_USR "usr"
501#define IAF_KW_ANYTHREAD "anythread"
502
503/*
504 * Parse an event specifier for Intel fixed function counters.
505 */

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540#define IAP_KW_EDGE "edge"
541#define IAP_KW_INV "inv"
542#define IAP_KW_OS "os"
543#define IAP_KW_PREFETCH "prefetch"
544#define IAP_KW_SNOOPRESPONSE "snoopresponse"
545#define IAP_KW_SNOOPTYPE "snooptype"
546#define IAP_KW_TRANSITION "trans"
547#define IAP_KW_USR "usr"
525
526#define IAF_KW_OS "os"
527#define IAF_KW_USR "usr"
528#define IAF_KW_ANYTHREAD "anythread"
529
530/*
531 * Parse an event specifier for Intel fixed function counters.
532 */

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567#define IAP_KW_EDGE "edge"
568#define IAP_KW_INV "inv"
569#define IAP_KW_OS "os"
570#define IAP_KW_PREFETCH "prefetch"
571#define IAP_KW_SNOOPRESPONSE "snoopresponse"
572#define IAP_KW_SNOOPTYPE "snooptype"
573#define IAP_KW_TRANSITION "trans"
574#define IAP_KW_USR "usr"
575#define IAP_KW_RSP "rsp"
548
549static struct pmc_masks iap_core_mask[] = {
550 PMCMASK(all, (0x3 << 14)),
551 PMCMASK(this, (0x1 << 14)),
552 NULLMASK
553};
554
555static struct pmc_masks iap_agent_mask[] = {

--- 31 unchanged lines hidden (view full) ---

587};
588
589static struct pmc_masks iap_transition_mask[] = {
590 PMCMASK(any, 0x00),
591 PMCMASK(frequency, 0x10),
592 NULLMASK
593};
594
576
577static struct pmc_masks iap_core_mask[] = {
578 PMCMASK(all, (0x3 << 14)),
579 PMCMASK(this, (0x1 << 14)),
580 NULLMASK
581};
582
583static struct pmc_masks iap_agent_mask[] = {

--- 31 unchanged lines hidden (view full) ---

615};
616
617static struct pmc_masks iap_transition_mask[] = {
618 PMCMASK(any, 0x00),
619 PMCMASK(frequency, 0x10),
620 NULLMASK
621};
622
623static struct pmc_masks iap_rsp_mask[] = {
624 PMCMASK(DMND_DATA_RD, (1 << 0)),
625 PMCMASK(DMND_RFO, (1 << 1)),
626 PMCMASK(DMND_IFETCH, (1 << 2)),
627 PMCMASK(WB, (1 << 3)),
628 PMCMASK(PF_DATA_RD, (1 << 4)),
629 PMCMASK(PF_RFO, (1 << 5)),
630 PMCMASK(PF_IFETCH, (1 << 6)),
631 PMCMASK(OTHER, (1 << 7)),
632 PMCMASK(UNCORE_HIT, (1 << 8)),
633 PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)),
634 PMCMASK(OTHER_CORE_HITM, (1 << 10)),
635 PMCMASK(REMOTE_CACHE_FWD, (1 << 12)),
636 PMCMASK(REMOTE_DRAM, (1 << 13)),
637 PMCMASK(LOCAL_DRAM, (1 << 14)),
638 PMCMASK(NON_DRAM, (1 << 15)),
639 NULLMASK
640};
641
595static int
596iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
597 struct pmc_op_pmcallocate *pmc_config)
598{
599 char *e, *p, *q;
642static int
643iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
644 struct pmc_op_pmcallocate *pmc_config)
645{
646 char *e, *p, *q;
600 uint32_t cachestate, evmask;
647 uint32_t cachestate, evmask, rsp;
601 int count, n;
602
603 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
604 PMC_CAP_QUALIFIER);
605 pmc_config->pm_md.pm_iap.pm_iap_config = 0;
606
648 int count, n;
649
650 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
651 PMC_CAP_QUALIFIER);
652 pmc_config->pm_md.pm_iap.pm_iap_config = 0;
653
607 cachestate = evmask = 0;
654 cachestate = evmask = rsp = 0;
608
609 /* Parse additional modifiers if present */
610 while ((p = strsep(&ctrspec, ",")) != NULL) {
611
612 n = 0;
613 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) {
614 q = strchr(p, '=');
615 if (*++q == '\0') /* skip '=' */

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646 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate);
647 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE &&
648 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) {
649 n = pmc_parse_mask(iap_transition_mask, p, &evmask);
650 if (n != 1)
651 return (-1);
652 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM ||
653 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 ||
655
656 /* Parse additional modifiers if present */
657 while ((p = strsep(&ctrspec, ",")) != NULL) {
658
659 n = 0;
660 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) {
661 q = strchr(p, '=');
662 if (*++q == '\0') /* skip '=' */

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693 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate);
694 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE &&
695 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) {
696 n = pmc_parse_mask(iap_transition_mask, p, &evmask);
697 if (n != 1)
698 return (-1);
699 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM ||
700 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 ||
654 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME ||
655 cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7) {
701 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) {
656 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) {
657 n = pmc_parse_mask(iap_snoopresponse_mask, p,
658 &evmask);
659 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) {
660 n = pmc_parse_mask(iap_snooptype_mask, p,
661 &evmask);
662 } else
663 return (-1);
702 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) {
703 n = pmc_parse_mask(iap_snoopresponse_mask, p,
704 &evmask);
705 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) {
706 n = pmc_parse_mask(iap_snooptype_mask, p,
707 &evmask);
708 } else
709 return (-1);
710 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 ||
711 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) {
712 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
713 n = pmc_parse_mask(iap_rsp_mask, p, &rsp);
714 } else
715 return (-1);
664 } else
665 return (-1);
666
667 if (n < 0) /* Parsing failed. */
668 return (-1);
669 }
670
671 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask;

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688 case PMC_EV_IAP_EVENT_77H: /* Core */
689 if (cachestate == 0)
690 cachestate = (0xF << 8);
691 default:
692 break;
693 }
694
695 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate;
716 } else
717 return (-1);
718
719 if (n < 0) /* Parsing failed. */
720 return (-1);
721 }
722
723 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask;

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740 case PMC_EV_IAP_EVENT_77H: /* Core */
741 if (cachestate == 0)
742 cachestate = (0xF << 8);
743 default:
744 break;
745 }
746
747 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate;
748 pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp;
696
697 return (0);
698}
699
700/*
749
750 return (0);
751}
752
753/*
754 * Intel Uncore.
755 */
756
757static int
758ucf_allocate_pmc(enum pmc_event pe, char *ctrspec,
759 struct pmc_op_pmcallocate *pmc_config)
760{
761 (void) pe;
762 (void) ctrspec;
763
764 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
765 pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0;
766
767 return (0);
768}
769
770#define UCP_KW_CMASK "cmask"
771#define UCP_KW_EDGE "edge"
772#define UCP_KW_INV "inv"
773
774static int
775ucp_allocate_pmc(enum pmc_event pe, char *ctrspec,
776 struct pmc_op_pmcallocate *pmc_config)
777{
778 char *e, *p, *q;
779 int count, n;
780
781 (void) pe;
782
783 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
784 PMC_CAP_QUALIFIER);
785 pmc_config->pm_md.pm_ucp.pm_ucp_config = 0;
786
787 /* Parse additional modifiers if present */
788 while ((p = strsep(&ctrspec, ",")) != NULL) {
789
790 n = 0;
791 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) {
792 q = strchr(p, '=');
793 if (*++q == '\0') /* skip '=' */
794 return (-1);
795 count = strtol(q, &e, 0);
796 if (e == q || *e != '\0')
797 return (-1);
798 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
799 pmc_config->pm_md.pm_ucp.pm_ucp_config |=
800 UCP_CMASK(count);
801 } else if (KWMATCH(p, UCP_KW_EDGE)) {
802 pmc_config->pm_caps |= PMC_CAP_EDGE;
803 } else if (KWMATCH(p, UCP_KW_INV)) {
804 pmc_config->pm_caps |= PMC_CAP_INVERT;
805 } else
806 return (-1);
807
808 if (n < 0) /* Parsing failed. */
809 return (-1);
810 }
811
812 return (0);
813}
814
815/*
701 * AMD K8 PMCs.
702 *
703 * These are very similar to AMD K7 PMCs, but support more kinds of
704 * events.
705 */
706
707static struct pmc_event_alias k8_aliases[] = {
708 EV_ALIAS("branches", "k8-fr-retired-taken-branches"),

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2387 case PMC_CPU_INTEL_CORE2EXTREME:
2388 ev = core2_event_table;
2389 count = PMC_EVENT_TABLE_SIZE(core2);
2390 break;
2391 case PMC_CPU_INTEL_COREI7:
2392 ev = corei7_event_table;
2393 count = PMC_EVENT_TABLE_SIZE(corei7);
2394 break;
816 * AMD K8 PMCs.
817 *
818 * These are very similar to AMD K7 PMCs, but support more kinds of
819 * events.
820 */
821
822static struct pmc_event_alias k8_aliases[] = {
823 EV_ALIAS("branches", "k8-fr-retired-taken-branches"),

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2502 case PMC_CPU_INTEL_CORE2EXTREME:
2503 ev = core2_event_table;
2504 count = PMC_EVENT_TABLE_SIZE(core2);
2505 break;
2506 case PMC_CPU_INTEL_COREI7:
2507 ev = corei7_event_table;
2508 count = PMC_EVENT_TABLE_SIZE(corei7);
2509 break;
2510 case PMC_CPU_INTEL_WESTMERE:
2511 ev = westmere_event_table;
2512 count = PMC_EVENT_TABLE_SIZE(westmere);
2513 break;
2395 }
2396 break;
2514 }
2515 break;
2516 case PMC_CLASS_UCF:
2517 ev = ucf_event_table;
2518 count = PMC_EVENT_TABLE_SIZE(ucf);
2519 break;
2520 case PMC_CLASS_UCP:
2521 /*
2522 * Return the most appropriate set of event name
2523 * spellings for the current CPU.
2524 */
2525 switch (cpu_info.pm_cputype) {
2526 default:
2527 case PMC_CPU_INTEL_COREI7:
2528 ev = corei7uc_event_table;
2529 count = PMC_EVENT_TABLE_SIZE(corei7uc);
2530 break;
2531 case PMC_CPU_INTEL_WESTMERE:
2532 ev = westmereuc_event_table;
2533 count = PMC_EVENT_TABLE_SIZE(westmereuc);
2534 break;
2535 }
2536 break;
2397 case PMC_CLASS_TSC:
2398 ev = tsc_event_table;
2399 count = PMC_EVENT_TABLE_SIZE(tsc);
2400 break;
2401 case PMC_CLASS_K7:
2402 ev = k7_event_table;
2403 count = PMC_EVENT_TABLE_SIZE(k7);
2404 break;

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2600 PMC_MDEP_INIT(core);
2601 pmc_class_table[n] = &core_class_table_descr;
2602 break;
2603 case PMC_CPU_INTEL_CORE2:
2604 case PMC_CPU_INTEL_CORE2EXTREME:
2605 PMC_MDEP_INIT_INTEL_V2(core2);
2606 break;
2607 case PMC_CPU_INTEL_COREI7:
2537 case PMC_CLASS_TSC:
2538 ev = tsc_event_table;
2539 count = PMC_EVENT_TABLE_SIZE(tsc);
2540 break;
2541 case PMC_CLASS_K7:
2542 ev = k7_event_table;
2543 count = PMC_EVENT_TABLE_SIZE(k7);
2544 break;

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2740 PMC_MDEP_INIT(core);
2741 pmc_class_table[n] = &core_class_table_descr;
2742 break;
2743 case PMC_CPU_INTEL_CORE2:
2744 case PMC_CPU_INTEL_CORE2EXTREME:
2745 PMC_MDEP_INIT_INTEL_V2(core2);
2746 break;
2747 case PMC_CPU_INTEL_COREI7:
2748 pmc_class_table[n++] = &ucf_class_table_descr;
2749 pmc_class_table[n++] = &corei7uc_class_table_descr;
2608 PMC_MDEP_INIT_INTEL_V2(corei7);
2609 break;
2750 PMC_MDEP_INIT_INTEL_V2(corei7);
2751 break;
2752 case PMC_CPU_INTEL_WESTMERE:
2753 pmc_class_table[n++] = &ucf_class_table_descr;
2754 pmc_class_table[n++] = &westmereuc_class_table_descr;
2755 PMC_MDEP_INIT_INTEL_V2(westmere);
2756 break;
2610 case PMC_CPU_INTEL_PIV:
2611 PMC_MDEP_INIT(p4);
2612 pmc_class_table[n] = &p4_class_table_descr;
2613 break;
2614#endif
2615#if defined(__XSCALE__)
2616 case PMC_CPU_INTEL_XSCALE:
2617 PMC_MDEP_INIT(xscale);

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2714 case PMC_CPU_INTEL_CORE2EXTREME:
2715 ev = core2_event_table;
2716 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2);
2717 break;
2718 case PMC_CPU_INTEL_COREI7:
2719 ev = corei7_event_table;
2720 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
2721 break;
2757 case PMC_CPU_INTEL_PIV:
2758 PMC_MDEP_INIT(p4);
2759 pmc_class_table[n] = &p4_class_table_descr;
2760 break;
2761#endif
2762#if defined(__XSCALE__)
2763 case PMC_CPU_INTEL_XSCALE:
2764 PMC_MDEP_INIT(xscale);

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2861 case PMC_CPU_INTEL_CORE2EXTREME:
2862 ev = core2_event_table;
2863 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2);
2864 break;
2865 case PMC_CPU_INTEL_COREI7:
2866 ev = corei7_event_table;
2867 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
2868 break;
2869 case PMC_CPU_INTEL_WESTMERE:
2870 ev = westmere_event_table;
2871 evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere);
2872 break;
2722 default: /* Unknown CPU type. */
2723 break;
2724 }
2873 default: /* Unknown CPU type. */
2874 break;
2875 }
2725 } if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) {
2876 } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) {
2877 ev = ucf_event_table;
2878 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf);
2879 } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) {
2880 switch (cpu) {
2881 case PMC_CPU_INTEL_COREI7:
2882 ev = corei7uc_event_table;
2883 evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc);
2884 break;
2885 case PMC_CPU_INTEL_WESTMERE:
2886 ev = westmereuc_event_table;
2887 evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc);
2888 break;
2889 default: /* Unknown CPU type. */
2890 break;
2891 }
2892 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) {
2726 ev = k7_event_table;
2727 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7);
2728 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
2729 ev = k8_event_table;
2730 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
2731 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) {
2732 ev = p4_event_table;
2733 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4);

--- 220 unchanged lines hidden --- 		2893 ev = k7_event_table;
2894 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7);
2895 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
2896 ev = k8_event_table;
2897 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
2898 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) {
2899 ev = p4_event_table;
2900 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4);

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