Cross Reference: /freebsd-10.2-release/contrib/llvm/lib/Target/X86/X86InstrMMX.td

1//====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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67// MMX Multiclasses
68//===----------------------------------------------------------------------===//
69
70let Constraints = "$src1 = $dst" in {
71 // MMXI_binop_rm - Simple MMX binary operator.
72 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
73 ValueType OpVT, bit Commutable = 0> {
74 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),

75 (ins VR64:$src1, VR64:$src2),

76 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
77 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
78 let isCommutable = Commutable;
79 }
80 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),

81 (ins VR64:$src1, i64mem:$src2),

82 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
83 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
84 (bitconvert
85 (load_mmx addr:$src2)))))]>;
86 }
87
88 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
89 bit Commutable = 0> {
90 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),

91 (ins VR64:$src1, VR64:$src2),

92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
94 let isCommutable = Commutable;
95 }
96 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),

97 (ins VR64:$src1, i64mem:$src2),

98 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
99 [(set VR64:$dst, (IntId VR64:$src1,
100 (bitconvert (load_mmx addr:$src2))))]>;
101 }
102
103 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
104 //
105 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew

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139 }
140}
141
142//===----------------------------------------------------------------------===//
143// MMX EMMS & FEMMS Instructions
144//===----------------------------------------------------------------------===//
145
146def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms",

147 [(int_x86_mmx_emms)]>;

148def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms",

149 [(int_x86_mmx_femms)]>;

150
151//===----------------------------------------------------------------------===//
152// MMX Scalar Instructions
153//===----------------------------------------------------------------------===//
154
155// Data Transfer Instructions
156def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
157 "movd\t{$src, $dst|$dst, $src}",

158 [(set VR64:$dst,
159 (v2i32 (scalar_to_vector GR32:$src)))]>;

160let canFoldAsLoad = 1, isReMaterializable = 1 in
161def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
162 "movd\t{$src, $dst|$dst, $src}",
163 [(set VR64:$dst,

164 (v2i32 (scalar_to_vector (loadi32 addr:$src))))]>;

165let mayStore = 1 in
166def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
167 "movd\t{$src, $dst|$dst, $src}", []>;

168def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs), (ins GR32:$dst, VR64:$src),
169 "movd\t{$src, $dst|$dst, $src}", []>;
170def MMX_MOVQ64gmr : MMXRI<0x7E, MRMDestMem, (outs),
171 (ins i64mem:$dst, VR64:$src),
172 "movq\t{$src, $dst|$dst, $src}", []>;

168
169let neverHasSideEffects = 1 in
170def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
171 "movd\t{$src, $dst|$dst, $src}",
172 []>;
173
174let neverHasSideEffects = 1 in
175// These are 64 bit moves, but since the OS X assembler doesn't
176// recognize a register-register movq, we write them as
177// movd.
178def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
179 (outs GR64:$dst), (ins VR64:$src),
180 "movd\t{$src, $dst|$dst, $src}", []>;
181def MMX_MOVD64rrv164 : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
182 "movd\t{$src, $dst|$dst, $src}",
183 [(set VR64:$dst,

173
174let neverHasSideEffects = 1 in
175def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
176 "movd\t{$src, $dst|$dst, $src}",
177 []>;
178
179let neverHasSideEffects = 1 in
180// These are 64 bit moves, but since the OS X assembler doesn't
181// recognize a register-register movq, we write them as
182// movd.
183def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
184 (outs GR64:$dst), (ins VR64:$src),
185 "movd\t{$src, $dst|$dst, $src}", []>;
186def MMX_MOVD64rrv164 : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
187 "movd\t{$src, $dst|$dst, $src}",
188 [(set VR64:$dst,

184 (v1i64 (scalar_to_vector GR64:$src)))]>;

189 (v1i64 (scalar_to_vector GR64:$src)))]>;

185
186let neverHasSideEffects = 1 in
187def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
188 "movq\t{$src, $dst|$dst, $src}", []>;
189let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
190def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
191 "movq\t{$src, $dst|$dst, $src}",
192 [(set VR64:$dst, (load_mmx addr:$src))]>;

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218let AddedComplexity = 15 in
219// movd to MMX register zero-extends
220def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
221 "movd\t{$src, $dst|$dst, $src}",
222 [(set VR64:$dst,
223 (v2i32 (X86vzmovl (v2i32 (scalar_to_vector GR32:$src)))))]>;
224let AddedComplexity = 20 in
225def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst),

190
191let neverHasSideEffects = 1 in
192def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
193 "movq\t{$src, $dst|$dst, $src}", []>;
194let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
195def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
196 "movq\t{$src, $dst|$dst, $src}",
197 [(set VR64:$dst, (load_mmx addr:$src))]>;

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223let AddedComplexity = 15 in
224// movd to MMX register zero-extends
225def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
226 "movd\t{$src, $dst|$dst, $src}",
227 [(set VR64:$dst,
228 (v2i32 (X86vzmovl (v2i32 (scalar_to_vector GR32:$src)))))]>;
229let AddedComplexity = 20 in
230def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst),

226 (ins i32mem:$src),

231 (ins i32mem:$src),

227 "movd\t{$src, $dst|$dst, $src}",
228 [(set VR64:$dst,
229 (v2i32 (X86vzmovl (v2i32
230 (scalar_to_vector (loadi32 addr:$src))))))]>;
231
232// Arithmetic Instructions
233
234// -- Addition

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427 (undef)))]>;
428
429// -- Conversion Instructions
430let neverHasSideEffects = 1 in {
431def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
432 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
433let mayLoad = 1 in
434def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst),

232 "movd\t{$src, $dst|$dst, $src}",
233 [(set VR64:$dst,
234 (v2i32 (X86vzmovl (v2i32
235 (scalar_to_vector (loadi32 addr:$src))))))]>;
236
237// Arithmetic Instructions
238
239// -- Addition

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432 (undef)))]>;
433
434// -- Conversion Instructions
435let neverHasSideEffects = 1 in {
436def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
437 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
438let mayLoad = 1 in
439def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst),

435 (ins f128mem:$src),

440 (ins f128mem:$src),

436 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
437
438def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
439 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
440let mayLoad = 1 in
441def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst),

441 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
442
443def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
444 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
445let mayLoad = 1 in
446def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst),

442 (ins i64mem:$src),

447 (ins i64mem:$src),

443 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
444
445def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
446 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
447let mayLoad = 1 in
448def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst),

448 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
449
450def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
451 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
452let mayLoad = 1 in
453def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst),

449 (ins i64mem:$src),

454 (ins i64mem:$src),

450 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
451
452def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
453 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
454let mayLoad = 1 in
455def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
456 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
457
458def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
459 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
460let mayLoad = 1 in
461def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst),

455 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
456
457def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
458 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
459let mayLoad = 1 in
460def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
461 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
462
463def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
464 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
465let mayLoad = 1 in
466def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst),

462 (ins f128mem:$src),

467 (ins f128mem:$src),

463 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
464
465def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
466 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
467let mayLoad = 1 in
468def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
469 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
470} // end neverHasSideEffects

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476
477def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
478 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
479 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
480 [(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
481 (iPTR imm:$src2)))]>;
482let Constraints = "$src1 = $dst" in {
483 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,

468 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
469
470def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
471 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
472let mayLoad = 1 in
473def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
474 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
475} // end neverHasSideEffects

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481
482def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
483 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
484 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
485 [(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
486 (iPTR imm:$src2)))]>;
487let Constraints = "$src1 = $dst" in {
488 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,

484 (outs VR64:$dst), (ins VR64:$src1, GR32:$src2,
485 i16i8imm:$src3),

489 (outs VR64:$dst),
490 (ins VR64:$src1, GR32:$src2,i16i8imm:$src3),

486 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
487 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
488 GR32:$src2,(iPTR imm:$src3))))]>;
489 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,

491 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
492 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
493 GR32:$src2,(iPTR imm:$src3))))]>;
494 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,

490 (outs VR64:$dst), (ins VR64:$src1, i16mem:$src2,
491 i16i8imm:$src3),

495 (outs VR64:$dst),
496 (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),