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X86InstrMMX.td (193323) X86InstrMMX.td (193574)
1//====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 MMX instruction set, defining the instructions,
11// and properties of the instructions which are needed for code generation,
12// machine code emission, and analysis.
13//
14//===----------------------------------------------------------------------===//
15
16//===----------------------------------------------------------------------===//
17// MMX Pattern Fragments
18//===----------------------------------------------------------------------===//
19
20def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
21
22def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
23def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
24def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
25def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
26
27//===----------------------------------------------------------------------===//
28// MMX Masks
29//===----------------------------------------------------------------------===//
30
31// MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
32// PSHUFW imm.
33def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
34 return getI8Imm(X86::getShuffleSHUFImmediate(N));
35}]>;
36
37// Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
38def mmx_unpckh : PatFrag<(ops node:$lhs, node:$rhs),
39 (vector_shuffle node:$lhs, node:$rhs), [{
40 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
41}]>;
42
43// Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
44def mmx_unpckl : PatFrag<(ops node:$lhs, node:$rhs),
45 (vector_shuffle node:$lhs, node:$rhs), [{
46 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
47}]>;
48
49// Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
50def mmx_unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
51 (vector_shuffle node:$lhs, node:$rhs), [{
52 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
53}]>;
54
55// Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
56def mmx_unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
57 (vector_shuffle node:$lhs, node:$rhs), [{
58 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
59}]>;
60
61def mmx_pshufw : PatFrag<(ops node:$lhs, node:$rhs),
62 (vector_shuffle node:$lhs, node:$rhs), [{
63 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
64}], MMX_SHUFFLE_get_shuf_imm>;
65
66//===----------------------------------------------------------------------===//
67// MMX Multiclasses
68//===----------------------------------------------------------------------===//
69
70let isTwoAddress = 1 in {
71 // MMXI_binop_rm - Simple MMX binary operator.
72 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
73 ValueType OpVT, bit Commutable = 0> {
74 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
75 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
76 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
77 let isCommutable = Commutable;
78 }
79 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
80 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
81 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
82 (bitconvert
83 (load_mmx addr:$src2)))))]>;
84 }
85
86 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
87 bit Commutable = 0> {
88 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
89 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
90 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
91 let isCommutable = Commutable;
92 }
93 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
94 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
95 [(set VR64:$dst, (IntId VR64:$src1,
96 (bitconvert (load_mmx addr:$src2))))]>;
97 }
98
99 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
100 //
101 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
102 // to collapse (bitconvert VT to VT) into its operand.
103 //
104 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
105 bit Commutable = 0> {
106 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
107 (ins VR64:$src1, VR64:$src2),
108 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
109 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
110 let isCommutable = Commutable;
111 }
112 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
113 (ins VR64:$src1, i64mem:$src2),
114 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
115 [(set VR64:$dst,
116 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
117 }
118
119 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
120 string OpcodeStr, Intrinsic IntId,
121 Intrinsic IntId2> {
122 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
123 (ins VR64:$src1, VR64:$src2),
124 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
125 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
126 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
127 (ins VR64:$src1, i64mem:$src2),
128 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
129 [(set VR64:$dst, (IntId VR64:$src1,
130 (bitconvert (load_mmx addr:$src2))))]>;
131 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
132 (ins VR64:$src1, i32i8imm:$src2),
133 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
134 [(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))]>;
135 }
136}
137
138//===----------------------------------------------------------------------===//
139// MMX EMMS & FEMMS Instructions
140//===----------------------------------------------------------------------===//
141
142def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
143def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
144
145//===----------------------------------------------------------------------===//
146// MMX Scalar Instructions
147//===----------------------------------------------------------------------===//
148
149// Data Transfer Instructions
150def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
151 "movd\t{$src, $dst|$dst, $src}",
152 [(set VR64:$dst, (v2i32 (scalar_to_vector GR32:$src)))]>;
153let canFoldAsLoad = 1, isReMaterializable = 1 in
154def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
155 "movd\t{$src, $dst|$dst, $src}",
156 [(set VR64:$dst, (v2i32 (scalar_to_vector (loadi32 addr:$src))))]>;
157let mayStore = 1 in
158def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
159 "movd\t{$src, $dst|$dst, $src}", []>;
160
161let neverHasSideEffects = 1 in
162def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
163 "movd\t{$src, $dst|$dst, $src}",
164 []>;
165
166let neverHasSideEffects = 1 in
167def MMX_MOVD64from64rr : MMXRI<0x7E, MRMSrcReg,
168 (outs GR64:$dst), (ins VR64:$src),
169 "movd\t{$src, $dst|$dst, $src}", []>;
170
171let neverHasSideEffects = 1 in
172def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
173 "movq\t{$src, $dst|$dst, $src}", []>;
174let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
175def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
176 "movq\t{$src, $dst|$dst, $src}",
177 [(set VR64:$dst, (load_mmx addr:$src))]>;
178def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
179 "movq\t{$src, $dst|$dst, $src}",
180 [(store (v1i64 VR64:$src), addr:$dst)]>;
181
182def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
183 "movdq2q\t{$src, $dst|$dst, $src}",
184 [(set VR64:$dst,
185 (v1i64 (bitconvert
186 (i64 (vector_extract (v2i64 VR128:$src),
187 (iPTR 0))))))]>;
188
189def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
190 "movq2dq\t{$src, $dst|$dst, $src}",
191 [(set VR128:$dst,
192 (movl immAllZerosV,
193 (v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src))))))]>;
194
195let neverHasSideEffects = 1 in
196def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMDestMem, (outs FR64:$dst), (ins VR64:$src),
197 "movq2dq\t{$src, $dst|$dst, $src}", []>;
198
199def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
200 "movntq\t{$src, $dst|$dst, $src}",
201 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
202
203let AddedComplexity = 15 in
204// movd to MMX register zero-extends
205def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
206 "movd\t{$src, $dst|$dst, $src}",
207 [(set VR64:$dst,
208 (v2i32 (X86vzmovl (v2i32 (scalar_to_vector GR32:$src)))))]>;
209let AddedComplexity = 20 in
210def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
211 "movd\t{$src, $dst|$dst, $src}",
212 [(set VR64:$dst,
213 (v2i32 (X86vzmovl (v2i32
214 (scalar_to_vector (loadi32 addr:$src))))))]>;
215
216// Arithmetic Instructions
217
218// -- Addition
219defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
220defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
221defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
222defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>;
223
224defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
225defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
226
227defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
228defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
229
230// -- Subtraction
231defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
232defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
233defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
234defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>;
235
236defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
237defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
238
239defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
240defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
241
242// -- Multiplication
243defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
244
245defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
246defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
247defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
248
249// -- Miscellanea
250defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
251
252defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
253defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
254
255defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
256defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
257
258defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
259defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
260
261defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 1>;
262
263// Logical Instructions
264defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
265defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
266defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
267
268let isTwoAddress = 1 in {
269 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
270 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
271 "pandn\t{$src2, $dst|$dst, $src2}",
272 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
273 VR64:$src2)))]>;
274 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
275 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
276 "pandn\t{$src2, $dst|$dst, $src2}",
277 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
278 (load addr:$src2))))]>;
279}
280
281// Shift Instructions
282defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
283 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>;
284defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
285 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>;
286defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
287 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>;
288
289defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
290 int_x86_mmx_psll_w, int_x86_mmx_pslli_w>;
291defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
292 int_x86_mmx_psll_d, int_x86_mmx_pslli_d>;
293defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
294 int_x86_mmx_psll_q, int_x86_mmx_pslli_q>;
295
296defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
297 int_x86_mmx_psra_w, int_x86_mmx_psrai_w>;
298defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
299 int_x86_mmx_psra_d, int_x86_mmx_psrai_d>;
300
301// Shift up / down and insert zero's.
302def : Pat<(v1i64 (X86vshl VR64:$src, (i8 imm:$amt))),
303 (v1i64 (MMX_PSLLQri VR64:$src, imm:$amt))>;
304def : Pat<(v1i64 (X86vshr VR64:$src, (i8 imm:$amt))),
305 (v1i64 (MMX_PSRLQri VR64:$src, imm:$amt))>;
306
307// Comparison Instructions
308defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
309defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
310defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
311
312defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
313defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
314defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
315
316// Conversion Instructions
317
318// -- Unpack Instructions
319let isTwoAddress = 1 in {
320 // Unpack High Packed Data Instructions
321 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
322 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
323 "punpckhbw\t{$src2, $dst|$dst, $src2}",
324 [(set VR64:$dst,
325 (v8i8 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
326 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
327 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
328 "punpckhbw\t{$src2, $dst|$dst, $src2}",
329 [(set VR64:$dst,
330 (v8i8 (mmx_unpckh VR64:$src1,
331 (bc_v8i8 (load_mmx addr:$src2)))))]>;
332
333 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
334 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
335 "punpckhwd\t{$src2, $dst|$dst, $src2}",
336 [(set VR64:$dst,
337 (v4i16 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
338 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
339 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
340 "punpckhwd\t{$src2, $dst|$dst, $src2}",
341 [(set VR64:$dst,
342 (v4i16 (mmx_unpckh VR64:$src1,
343 (bc_v4i16 (load_mmx addr:$src2)))))]>;
344
345 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
346 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
347 "punpckhdq\t{$src2, $dst|$dst, $src2}",
348 [(set VR64:$dst,
349 (v2i32 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
350 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
351 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
352 "punpckhdq\t{$src2, $dst|$dst, $src2}",
353 [(set VR64:$dst,
354 (v2i32 (mmx_unpckh VR64:$src1,
355 (bc_v2i32 (load_mmx addr:$src2)))))]>;
356
357 // Unpack Low Packed Data Instructions
358 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
359 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
360 "punpcklbw\t{$src2, $dst|$dst, $src2}",
361 [(set VR64:$dst,
362 (v8i8 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
363 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
364 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
365 "punpcklbw\t{$src2, $dst|$dst, $src2}",
366 [(set VR64:$dst,
367 (v8i8 (mmx_unpckl VR64:$src1,
368 (bc_v8i8 (load_mmx addr:$src2)))))]>;
369
370 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
371 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
372 "punpcklwd\t{$src2, $dst|$dst, $src2}",
373 [(set VR64:$dst,
374 (v4i16 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
375 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
376 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
377 "punpcklwd\t{$src2, $dst|$dst, $src2}",
378 [(set VR64:$dst,
379 (v4i16 (mmx_unpckl VR64:$src1,
380 (bc_v4i16 (load_mmx addr:$src2)))))]>;
381
382 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
383 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
384 "punpckldq\t{$src2, $dst|$dst, $src2}",
385 [(set VR64:$dst,
386 (v2i32 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
387 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
388 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
389 "punpckldq\t{$src2, $dst|$dst, $src2}",
390 [(set VR64:$dst,
391 (v2i32 (mmx_unpckl VR64:$src1,
392 (bc_v2i32 (load_mmx addr:$src2)))))]>;
393}
394
395// -- Pack Instructions
396defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
397defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
398defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
399
400// -- Shuffle Instructions
401def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
402 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
403 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
404 [(set VR64:$dst,
405 (v4i16 (mmx_pshufw:$src2 VR64:$src1, (undef))))]>;
406def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
407 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
408 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
409 [(set VR64:$dst,
410 (mmx_pshufw:$src2 (bc_v4i16 (load_mmx addr:$src1)),
411 (undef)))]>;
412
413// -- Conversion Instructions
414let neverHasSideEffects = 1 in {
415def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
416 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
417let mayLoad = 1 in
418def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
419 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
420
421def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
422 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
423let mayLoad = 1 in
424def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
425 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
426
427def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
428 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
429let mayLoad = 1 in
430def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
431 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
432
433def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
434 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
435let mayLoad = 1 in
436def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
437 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
438
439def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
440 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
441let mayLoad = 1 in
442def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
443 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
444
445def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
446 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
447let mayLoad = 1 in
448def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
449 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
450} // end neverHasSideEffects
451
452
453// Extract / Insert
454def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
455def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
456
457def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
458 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
459 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
460 [(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
461 (iPTR imm:$src2)))]>;
462let isTwoAddress = 1 in {
463 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
464 (outs VR64:$dst), (ins VR64:$src1, GR32:$src2, i16i8imm:$src3),
465 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
466 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
467 GR32:$src2, (iPTR imm:$src3))))]>;
468 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
469 (outs VR64:$dst), (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
470 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
471 [(set VR64:$dst,
472 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
473 (i32 (anyext (loadi16 addr:$src2))),
474 (iPTR imm:$src3))))]>;
475}
476
477// Mask creation
478def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
479 "pmovmskb\t{$src, $dst|$dst, $src}",
480 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
481
482// Misc.
483let Uses = [EDI] in
484def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
485 "maskmovq\t{$mask, $src|$src, $mask}",
486 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
487let Uses = [RDI] in
488def MMX_MASKMOVQ64: MMXI64<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
489 "maskmovq\t{$mask, $src|$src, $mask}",
490 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
491
492//===----------------------------------------------------------------------===//
493// Alias Instructions
494//===----------------------------------------------------------------------===//
495
496// Alias instructions that map zero vector to pxor.
497let isReMaterializable = 1 in {
498 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins),
499 "pxor\t$dst, $dst",
500 [(set VR64:$dst, (v2i32 immAllZerosV))]>;
501 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins),
502 "pcmpeqd\t$dst, $dst",
503 [(set VR64:$dst, (v2i32 immAllOnesV))]>;
504}
505
506let Predicates = [HasMMX] in {
507 def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
508 def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
509 def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
510}
511
512//===----------------------------------------------------------------------===//
513// Non-Instruction Patterns
514//===----------------------------------------------------------------------===//
515
516// Store 64-bit integer vector values.
517def : Pat<(store (v8i8 VR64:$src), addr:$dst),
518 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
519def : Pat<(store (v4i16 VR64:$src), addr:$dst),
520 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
521def : Pat<(store (v2i32 VR64:$src), addr:$dst),
522 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
523def : Pat<(store (v2f32 VR64:$src), addr:$dst),
524 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
525def : Pat<(store (v1i64 VR64:$src), addr:$dst),
526 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
527
528// Bit convert.
529def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
530def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
531def : Pat<(v8i8 (bitconvert (v2f32 VR64:$src))), (v8i8 VR64:$src)>;
532def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
533def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
534def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
535def : Pat<(v4i16 (bitconvert (v2f32 VR64:$src))), (v4i16 VR64:$src)>;
536def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
537def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
538def : Pat<(v2i32 (bitconvert (v2f32 VR64:$src))), (v2i32 VR64:$src)>;
539def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
540def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
541def : Pat<(v2f32 (bitconvert (v1i64 VR64:$src))), (v2f32 VR64:$src)>;
542def : Pat<(v2f32 (bitconvert (v2i32 VR64:$src))), (v2f32 VR64:$src)>;
543def : Pat<(v2f32 (bitconvert (v4i16 VR64:$src))), (v2f32 VR64:$src)>;
544def : Pat<(v2f32 (bitconvert (v8i8 VR64:$src))), (v2f32 VR64:$src)>;
545def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
546def : Pat<(v1i64 (bitconvert (v2f32 VR64:$src))), (v1i64 VR64:$src)>;
547def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
548def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
549
550// 64-bit bit convert.
551def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
552 (MMX_MOVD64to64rr GR64:$src)>;
553def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
554 (MMX_MOVD64to64rr GR64:$src)>;
555def : Pat<(v2f32 (bitconvert (i64 GR64:$src))),
556 (MMX_MOVD64to64rr GR64:$src)>;
557def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
558 (MMX_MOVD64to64rr GR64:$src)>;
559def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
560 (MMX_MOVD64to64rr GR64:$src)>;
561def : Pat<(i64 (bitconvert (v1i64 VR64:$src))),
562 (MMX_MOVD64from64rr VR64:$src)>;
563def : Pat<(i64 (bitconvert (v2i32 VR64:$src))),
564 (MMX_MOVD64from64rr VR64:$src)>;
565def : Pat<(i64 (bitconvert (v2f32 VR64:$src))),
566 (MMX_MOVD64from64rr VR64:$src)>;
567def : Pat<(i64 (bitconvert (v4i16 VR64:$src))),
568 (MMX_MOVD64from64rr VR64:$src)>;
569def : Pat<(i64 (bitconvert (v8i8 VR64:$src))),
570 (MMX_MOVD64from64rr VR64:$src)>;
571def : Pat<(f64 (bitconvert (v1i64 VR64:$src))),
572 (MMX_MOVQ2FR64rr VR64:$src)>;
573def : Pat<(f64 (bitconvert (v2i32 VR64:$src))),
574 (MMX_MOVQ2FR64rr VR64:$src)>;
575def : Pat<(f64 (bitconvert (v4i16 VR64:$src))),
576 (MMX_MOVQ2FR64rr VR64:$src)>;
577def : Pat<(f64 (bitconvert (v8i8 VR64:$src))),
578 (MMX_MOVQ2FR64rr VR64:$src)>;
579
1//====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 MMX instruction set, defining the instructions,
11// and properties of the instructions which are needed for code generation,
12// machine code emission, and analysis.
13//
14//===----------------------------------------------------------------------===//
15
16//===----------------------------------------------------------------------===//
17// MMX Pattern Fragments
18//===----------------------------------------------------------------------===//
19
20def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
21
22def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
23def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
24def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
25def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
26
27//===----------------------------------------------------------------------===//
28// MMX Masks
29//===----------------------------------------------------------------------===//
30
31// MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
32// PSHUFW imm.
33def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
34 return getI8Imm(X86::getShuffleSHUFImmediate(N));
35}]>;
36
37// Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
38def mmx_unpckh : PatFrag<(ops node:$lhs, node:$rhs),
39 (vector_shuffle node:$lhs, node:$rhs), [{
40 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
41}]>;
42
43// Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
44def mmx_unpckl : PatFrag<(ops node:$lhs, node:$rhs),
45 (vector_shuffle node:$lhs, node:$rhs), [{
46 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
47}]>;
48
49// Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
50def mmx_unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
51 (vector_shuffle node:$lhs, node:$rhs), [{
52 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
53}]>;
54
55// Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
56def mmx_unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
57 (vector_shuffle node:$lhs, node:$rhs), [{
58 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
59}]>;
60
61def mmx_pshufw : PatFrag<(ops node:$lhs, node:$rhs),
62 (vector_shuffle node:$lhs, node:$rhs), [{
63 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
64}], MMX_SHUFFLE_get_shuf_imm>;
65
66//===----------------------------------------------------------------------===//
67// MMX Multiclasses
68//===----------------------------------------------------------------------===//
69
70let isTwoAddress = 1 in {
71 // MMXI_binop_rm - Simple MMX binary operator.
72 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
73 ValueType OpVT, bit Commutable = 0> {
74 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
75 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
76 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
77 let isCommutable = Commutable;
78 }
79 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
80 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
81 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
82 (bitconvert
83 (load_mmx addr:$src2)))))]>;
84 }
85
86 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
87 bit Commutable = 0> {
88 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
89 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
90 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
91 let isCommutable = Commutable;
92 }
93 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
94 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
95 [(set VR64:$dst, (IntId VR64:$src1,
96 (bitconvert (load_mmx addr:$src2))))]>;
97 }
98
99 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
100 //
101 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
102 // to collapse (bitconvert VT to VT) into its operand.
103 //
104 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
105 bit Commutable = 0> {
106 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
107 (ins VR64:$src1, VR64:$src2),
108 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
109 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
110 let isCommutable = Commutable;
111 }
112 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
113 (ins VR64:$src1, i64mem:$src2),
114 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
115 [(set VR64:$dst,
116 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
117 }
118
119 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
120 string OpcodeStr, Intrinsic IntId,
121 Intrinsic IntId2> {
122 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
123 (ins VR64:$src1, VR64:$src2),
124 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
125 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
126 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
127 (ins VR64:$src1, i64mem:$src2),
128 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
129 [(set VR64:$dst, (IntId VR64:$src1,
130 (bitconvert (load_mmx addr:$src2))))]>;
131 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
132 (ins VR64:$src1, i32i8imm:$src2),
133 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
134 [(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))]>;
135 }
136}
137
138//===----------------------------------------------------------------------===//
139// MMX EMMS & FEMMS Instructions
140//===----------------------------------------------------------------------===//
141
142def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
143def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
144
145//===----------------------------------------------------------------------===//
146// MMX Scalar Instructions
147//===----------------------------------------------------------------------===//
148
149// Data Transfer Instructions
150def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
151 "movd\t{$src, $dst|$dst, $src}",
152 [(set VR64:$dst, (v2i32 (scalar_to_vector GR32:$src)))]>;
153let canFoldAsLoad = 1, isReMaterializable = 1 in
154def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
155 "movd\t{$src, $dst|$dst, $src}",
156 [(set VR64:$dst, (v2i32 (scalar_to_vector (loadi32 addr:$src))))]>;
157let mayStore = 1 in
158def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
159 "movd\t{$src, $dst|$dst, $src}", []>;
160
161let neverHasSideEffects = 1 in
162def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
163 "movd\t{$src, $dst|$dst, $src}",
164 []>;
165
166let neverHasSideEffects = 1 in
167def MMX_MOVD64from64rr : MMXRI<0x7E, MRMSrcReg,
168 (outs GR64:$dst), (ins VR64:$src),
169 "movd\t{$src, $dst|$dst, $src}", []>;
170
171let neverHasSideEffects = 1 in
172def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
173 "movq\t{$src, $dst|$dst, $src}", []>;
174let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
175def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
176 "movq\t{$src, $dst|$dst, $src}",
177 [(set VR64:$dst, (load_mmx addr:$src))]>;
178def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
179 "movq\t{$src, $dst|$dst, $src}",
180 [(store (v1i64 VR64:$src), addr:$dst)]>;
181
182def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
183 "movdq2q\t{$src, $dst|$dst, $src}",
184 [(set VR64:$dst,
185 (v1i64 (bitconvert
186 (i64 (vector_extract (v2i64 VR128:$src),
187 (iPTR 0))))))]>;
188
189def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
190 "movq2dq\t{$src, $dst|$dst, $src}",
191 [(set VR128:$dst,
192 (movl immAllZerosV,
193 (v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src))))))]>;
194
195let neverHasSideEffects = 1 in
196def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMDestMem, (outs FR64:$dst), (ins VR64:$src),
197 "movq2dq\t{$src, $dst|$dst, $src}", []>;
198
199def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
200 "movntq\t{$src, $dst|$dst, $src}",
201 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
202
203let AddedComplexity = 15 in
204// movd to MMX register zero-extends
205def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
206 "movd\t{$src, $dst|$dst, $src}",
207 [(set VR64:$dst,
208 (v2i32 (X86vzmovl (v2i32 (scalar_to_vector GR32:$src)))))]>;
209let AddedComplexity = 20 in
210def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
211 "movd\t{$src, $dst|$dst, $src}",
212 [(set VR64:$dst,
213 (v2i32 (X86vzmovl (v2i32
214 (scalar_to_vector (loadi32 addr:$src))))))]>;
215
216// Arithmetic Instructions
217
218// -- Addition
219defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
220defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
221defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
222defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>;
223
224defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
225defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
226
227defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
228defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
229
230// -- Subtraction
231defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
232defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
233defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
234defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>;
235
236defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
237defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
238
239defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
240defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
241
242// -- Multiplication
243defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
244
245defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
246defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
247defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
248
249// -- Miscellanea
250defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
251
252defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
253defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
254
255defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
256defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
257
258defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
259defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
260
261defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 1>;
262
263// Logical Instructions
264defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
265defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
266defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
267
268let isTwoAddress = 1 in {
269 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
270 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
271 "pandn\t{$src2, $dst|$dst, $src2}",
272 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
273 VR64:$src2)))]>;
274 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
275 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
276 "pandn\t{$src2, $dst|$dst, $src2}",
277 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
278 (load addr:$src2))))]>;
279}
280
281// Shift Instructions
282defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
283 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>;
284defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
285 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>;
286defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
287 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>;
288
289defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
290 int_x86_mmx_psll_w, int_x86_mmx_pslli_w>;
291defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
292 int_x86_mmx_psll_d, int_x86_mmx_pslli_d>;
293defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
294 int_x86_mmx_psll_q, int_x86_mmx_pslli_q>;
295
296defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
297 int_x86_mmx_psra_w, int_x86_mmx_psrai_w>;
298defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
299 int_x86_mmx_psra_d, int_x86_mmx_psrai_d>;
300
301// Shift up / down and insert zero's.
302def : Pat<(v1i64 (X86vshl VR64:$src, (i8 imm:$amt))),
303 (v1i64 (MMX_PSLLQri VR64:$src, imm:$amt))>;
304def : Pat<(v1i64 (X86vshr VR64:$src, (i8 imm:$amt))),
305 (v1i64 (MMX_PSRLQri VR64:$src, imm:$amt))>;
306
307// Comparison Instructions
308defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
309defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
310defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
311
312defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
313defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
314defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
315
316// Conversion Instructions
317
318// -- Unpack Instructions
319let isTwoAddress = 1 in {
320 // Unpack High Packed Data Instructions
321 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
322 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
323 "punpckhbw\t{$src2, $dst|$dst, $src2}",
324 [(set VR64:$dst,
325 (v8i8 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
326 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
327 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
328 "punpckhbw\t{$src2, $dst|$dst, $src2}",
329 [(set VR64:$dst,
330 (v8i8 (mmx_unpckh VR64:$src1,
331 (bc_v8i8 (load_mmx addr:$src2)))))]>;
332
333 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
334 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
335 "punpckhwd\t{$src2, $dst|$dst, $src2}",
336 [(set VR64:$dst,
337 (v4i16 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
338 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
339 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
340 "punpckhwd\t{$src2, $dst|$dst, $src2}",
341 [(set VR64:$dst,
342 (v4i16 (mmx_unpckh VR64:$src1,
343 (bc_v4i16 (load_mmx addr:$src2)))))]>;
344
345 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
346 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
347 "punpckhdq\t{$src2, $dst|$dst, $src2}",
348 [(set VR64:$dst,
349 (v2i32 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
350 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
351 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
352 "punpckhdq\t{$src2, $dst|$dst, $src2}",
353 [(set VR64:$dst,
354 (v2i32 (mmx_unpckh VR64:$src1,
355 (bc_v2i32 (load_mmx addr:$src2)))))]>;
356
357 // Unpack Low Packed Data Instructions
358 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
359 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
360 "punpcklbw\t{$src2, $dst|$dst, $src2}",
361 [(set VR64:$dst,
362 (v8i8 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
363 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
364 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
365 "punpcklbw\t{$src2, $dst|$dst, $src2}",
366 [(set VR64:$dst,
367 (v8i8 (mmx_unpckl VR64:$src1,
368 (bc_v8i8 (load_mmx addr:$src2)))))]>;
369
370 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
371 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
372 "punpcklwd\t{$src2, $dst|$dst, $src2}",
373 [(set VR64:$dst,
374 (v4i16 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
375 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
376 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
377 "punpcklwd\t{$src2, $dst|$dst, $src2}",
378 [(set VR64:$dst,
379 (v4i16 (mmx_unpckl VR64:$src1,
380 (bc_v4i16 (load_mmx addr:$src2)))))]>;
381
382 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
383 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
384 "punpckldq\t{$src2, $dst|$dst, $src2}",
385 [(set VR64:$dst,
386 (v2i32 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
387 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
388 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
389 "punpckldq\t{$src2, $dst|$dst, $src2}",
390 [(set VR64:$dst,
391 (v2i32 (mmx_unpckl VR64:$src1,
392 (bc_v2i32 (load_mmx addr:$src2)))))]>;
393}
394
395// -- Pack Instructions
396defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
397defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
398defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
399
400// -- Shuffle Instructions
401def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
402 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
403 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
404 [(set VR64:$dst,
405 (v4i16 (mmx_pshufw:$src2 VR64:$src1, (undef))))]>;
406def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
407 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
408 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
409 [(set VR64:$dst,
410 (mmx_pshufw:$src2 (bc_v4i16 (load_mmx addr:$src1)),
411 (undef)))]>;
412
413// -- Conversion Instructions
414let neverHasSideEffects = 1 in {
415def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
416 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
417let mayLoad = 1 in
418def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
419 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
420
421def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
422 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
423let mayLoad = 1 in
424def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
425 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
426
427def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
428 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
429let mayLoad = 1 in
430def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
431 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
432
433def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
434 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
435let mayLoad = 1 in
436def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
437 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
438
439def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
440 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
441let mayLoad = 1 in
442def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
443 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
444
445def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
446 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
447let mayLoad = 1 in
448def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
449 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
450} // end neverHasSideEffects
451
452
453// Extract / Insert
454def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
455def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
456
457def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
458 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
459 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
460 [(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
461 (iPTR imm:$src2)))]>;
462let isTwoAddress = 1 in {
463 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
464 (outs VR64:$dst), (ins VR64:$src1, GR32:$src2, i16i8imm:$src3),
465 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
466 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
467 GR32:$src2, (iPTR imm:$src3))))]>;
468 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
469 (outs VR64:$dst), (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
470 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
471 [(set VR64:$dst,
472 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
473 (i32 (anyext (loadi16 addr:$src2))),
474 (iPTR imm:$src3))))]>;
475}
476
477// Mask creation
478def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
479 "pmovmskb\t{$src, $dst|$dst, $src}",
480 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
481
482// Misc.
483let Uses = [EDI] in
484def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
485 "maskmovq\t{$mask, $src|$src, $mask}",
486 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
487let Uses = [RDI] in
488def MMX_MASKMOVQ64: MMXI64<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
489 "maskmovq\t{$mask, $src|$src, $mask}",
490 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
491
492//===----------------------------------------------------------------------===//
493// Alias Instructions
494//===----------------------------------------------------------------------===//
495
496// Alias instructions that map zero vector to pxor.
497let isReMaterializable = 1 in {
498 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins),
499 "pxor\t$dst, $dst",
500 [(set VR64:$dst, (v2i32 immAllZerosV))]>;
501 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins),
502 "pcmpeqd\t$dst, $dst",
503 [(set VR64:$dst, (v2i32 immAllOnesV))]>;
504}
505
506let Predicates = [HasMMX] in {
507 def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
508 def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
509 def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
510}
511
512//===----------------------------------------------------------------------===//
513// Non-Instruction Patterns
514//===----------------------------------------------------------------------===//
515
516// Store 64-bit integer vector values.
517def : Pat<(store (v8i8 VR64:$src), addr:$dst),
518 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
519def : Pat<(store (v4i16 VR64:$src), addr:$dst),
520 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
521def : Pat<(store (v2i32 VR64:$src), addr:$dst),
522 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
523def : Pat<(store (v2f32 VR64:$src), addr:$dst),
524 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
525def : Pat<(store (v1i64 VR64:$src), addr:$dst),
526 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
527
528// Bit convert.
529def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
530def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
531def : Pat<(v8i8 (bitconvert (v2f32 VR64:$src))), (v8i8 VR64:$src)>;
532def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
533def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
534def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
535def : Pat<(v4i16 (bitconvert (v2f32 VR64:$src))), (v4i16 VR64:$src)>;
536def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
537def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
538def : Pat<(v2i32 (bitconvert (v2f32 VR64:$src))), (v2i32 VR64:$src)>;
539def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
540def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
541def : Pat<(v2f32 (bitconvert (v1i64 VR64:$src))), (v2f32 VR64:$src)>;
542def : Pat<(v2f32 (bitconvert (v2i32 VR64:$src))), (v2f32 VR64:$src)>;
543def : Pat<(v2f32 (bitconvert (v4i16 VR64:$src))), (v2f32 VR64:$src)>;
544def : Pat<(v2f32 (bitconvert (v8i8 VR64:$src))), (v2f32 VR64:$src)>;
545def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
546def : Pat<(v1i64 (bitconvert (v2f32 VR64:$src))), (v1i64 VR64:$src)>;
547def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
548def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
549
550// 64-bit bit convert.
551def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
552 (MMX_MOVD64to64rr GR64:$src)>;
553def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
554 (MMX_MOVD64to64rr GR64:$src)>;
555def : Pat<(v2f32 (bitconvert (i64 GR64:$src))),
556 (MMX_MOVD64to64rr GR64:$src)>;
557def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
558 (MMX_MOVD64to64rr GR64:$src)>;
559def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
560 (MMX_MOVD64to64rr GR64:$src)>;
561def : Pat<(i64 (bitconvert (v1i64 VR64:$src))),
562 (MMX_MOVD64from64rr VR64:$src)>;
563def : Pat<(i64 (bitconvert (v2i32 VR64:$src))),
564 (MMX_MOVD64from64rr VR64:$src)>;
565def : Pat<(i64 (bitconvert (v2f32 VR64:$src))),
566 (MMX_MOVD64from64rr VR64:$src)>;
567def : Pat<(i64 (bitconvert (v4i16 VR64:$src))),
568 (MMX_MOVD64from64rr VR64:$src)>;
569def : Pat<(i64 (bitconvert (v8i8 VR64:$src))),
570 (MMX_MOVD64from64rr VR64:$src)>;
571def : Pat<(f64 (bitconvert (v1i64 VR64:$src))),
572 (MMX_MOVQ2FR64rr VR64:$src)>;
573def : Pat<(f64 (bitconvert (v2i32 VR64:$src))),
574 (MMX_MOVQ2FR64rr VR64:$src)>;
575def : Pat<(f64 (bitconvert (v4i16 VR64:$src))),
576 (MMX_MOVQ2FR64rr VR64:$src)>;
577def : Pat<(f64 (bitconvert (v8i8 VR64:$src))),
578 (MMX_MOVQ2FR64rr VR64:$src)>;
579
580// Move scalar to MMX zero-extended
581// movd to MMX register zero-extends
582let AddedComplexity = 15 in {
583 def : Pat<(v8i8 (X86vzmovl (bc_v8i8 (v2i32 (scalar_to_vector GR32:$src))))),
584 (MMX_MOVZDI2PDIrr GR32:$src)>;
585 def : Pat<(v4i16 (X86vzmovl (bc_v4i16 (v2i32 (scalar_to_vector GR32:$src))))),
586 (MMX_MOVZDI2PDIrr GR32:$src)>;
587}
588
589let AddedComplexity = 20 in {
580let AddedComplexity = 20 in {
590 def : Pat<(v8i8 (X86vzmovl (bc_v8i8 (load_mmx addr:$src)))),
591 (MMX_MOVZDI2PDIrm addr:$src)>;
592 def : Pat<(v4i16 (X86vzmovl (bc_v4i16 (load_mmx addr:$src)))),
593 (MMX_MOVZDI2PDIrm addr:$src)>;
594 def : Pat<(v2i32 (X86vzmovl (bc_v2i32 (load_mmx addr:$src)))),
595 (MMX_MOVZDI2PDIrm addr:$src)>;
596}
597
598// Clear top half.
599let AddedComplexity = 15 in {
581 def : Pat<(v2i32 (X86vzmovl (bc_v2i32 (load_mmx addr:$src)))),
582 (MMX_MOVZDI2PDIrm addr:$src)>;
583}
584
585// Clear top half.
586let AddedComplexity = 15 in {
600 def : Pat<(v8i8 (X86vzmovl VR64:$src)),
601 (MMX_PUNPCKLDQrr VR64:$src, (MMX_V_SET0))>;
602 def : Pat<(v4i16 (X86vzmovl VR64:$src)),
603 (MMX_PUNPCKLDQrr VR64:$src, (MMX_V_SET0))>;
604 def : Pat<(v2i32 (X86vzmovl VR64:$src)),
605 (MMX_PUNPCKLDQrr VR64:$src, (MMX_V_SET0))>;
606}
607
587 def : Pat<(v2i32 (X86vzmovl VR64:$src)),
588 (MMX_PUNPCKLDQrr VR64:$src, (MMX_V_SET0))>;
589}
590
608// Scalar to v4i16 / v8i8. The source may be a GR32, but only the lower
609// 8 or 16-bits matter.
610def : Pat<(bc_v8i8 (v2i32 (scalar_to_vector GR32:$src))),
611 (MMX_MOVD64rr GR32:$src)>;
612def : Pat<(bc_v4i16 (v2i32 (scalar_to_vector GR32:$src))),
613 (MMX_MOVD64rr GR32:$src)>;
614
615// Patterns to perform canonical versions of vector shuffling.
616let AddedComplexity = 10 in {
617 def : Pat<(v8i8 (mmx_unpckl_undef VR64:$src, (undef))),
618 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
619 def : Pat<(v4i16 (mmx_unpckl_undef VR64:$src, (undef))),
620 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
621 def : Pat<(v2i32 (mmx_unpckl_undef VR64:$src, (undef))),
622 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
623}
624
625let AddedComplexity = 10 in {
626 def : Pat<(v8i8 (mmx_unpckh_undef VR64:$src, (undef))),
627 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
628 def : Pat<(v4i16 (mmx_unpckh_undef VR64:$src, (undef))),
629 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
630 def : Pat<(v2i32 (mmx_unpckh_undef VR64:$src, (undef))),
631 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
632}
633
634// Patterns to perform vector shuffling with a zeroed out vector.
635let AddedComplexity = 20 in {
636 def : Pat<(bc_v2i32 (mmx_unpckl immAllZerosV,
637 (v2i32 (scalar_to_vector (load_mmx addr:$src))))),
638 (MMX_PUNPCKLDQrm VR64:$src, VR64:$src)>;
639}
640
641// Some special case PANDN patterns.
642// FIXME: Get rid of these.
643def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
644 VR64:$src2)),
645 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
646def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
647 VR64:$src2)),
648 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
649def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
650 VR64:$src2)),
651 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
652
653def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
654 (load addr:$src2))),
655 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
656def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
657 (load addr:$src2))),
658 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
659def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
660 (load addr:$src2))),
661 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
662
663// Move MMX to lower 64-bit of XMM
664def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v8i8 VR64:$src))))),
665 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
666def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v4i16 VR64:$src))))),
667 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
668def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v2i32 VR64:$src))))),
669 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
670def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v1i64 VR64:$src))))),
671 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
672
673// Move lower 64-bit of XMM to MMX.
674def : Pat<(v2i32 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
675 (iPTR 0))))),
676 (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
677def : Pat<(v4i16 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
678 (iPTR 0))))),
679 (v4i16 (MMX_MOVDQ2Qrr VR128:$src))>;
680def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
681 (iPTR 0))))),
682 (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
683
684// CMOV* - Used to implement the SELECT DAG operation. Expanded by the
685// scheduler into a branch sequence.
686// These are expanded by the scheduler.
687let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
688 def CMOV_V1I64 : I<0, Pseudo,
689 (outs VR64:$dst), (ins VR64:$t, VR64:$f, i8imm:$cond),
690 "#CMOV_V1I64 PSEUDO!",
691 [(set VR64:$dst,
692 (v1i64 (X86cmov VR64:$t, VR64:$f, imm:$cond,
693 EFLAGS)))]>;
694}
591// Patterns to perform canonical versions of vector shuffling.
592let AddedComplexity = 10 in {
593 def : Pat<(v8i8 (mmx_unpckl_undef VR64:$src, (undef))),
594 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
595 def : Pat<(v4i16 (mmx_unpckl_undef VR64:$src, (undef))),
596 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
597 def : Pat<(v2i32 (mmx_unpckl_undef VR64:$src, (undef))),
598 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
599}
600
601let AddedComplexity = 10 in {
602 def : Pat<(v8i8 (mmx_unpckh_undef VR64:$src, (undef))),
603 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
604 def : Pat<(v4i16 (mmx_unpckh_undef VR64:$src, (undef))),
605 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
606 def : Pat<(v2i32 (mmx_unpckh_undef VR64:$src, (undef))),
607 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
608}
609
610// Patterns to perform vector shuffling with a zeroed out vector.
611let AddedComplexity = 20 in {
612 def : Pat<(bc_v2i32 (mmx_unpckl immAllZerosV,
613 (v2i32 (scalar_to_vector (load_mmx addr:$src))))),
614 (MMX_PUNPCKLDQrm VR64:$src, VR64:$src)>;
615}
616
617// Some special case PANDN patterns.
618// FIXME: Get rid of these.
619def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
620 VR64:$src2)),
621 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
622def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
623 VR64:$src2)),
624 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
625def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
626 VR64:$src2)),
627 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
628
629def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
630 (load addr:$src2))),
631 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
632def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
633 (load addr:$src2))),
634 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
635def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
636 (load addr:$src2))),
637 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
638
639// Move MMX to lower 64-bit of XMM
640def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v8i8 VR64:$src))))),
641 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
642def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v4i16 VR64:$src))))),
643 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
644def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v2i32 VR64:$src))))),
645 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
646def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v1i64 VR64:$src))))),
647 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
648
649// Move lower 64-bit of XMM to MMX.
650def : Pat<(v2i32 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
651 (iPTR 0))))),
652 (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
653def : Pat<(v4i16 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
654 (iPTR 0))))),
655 (v4i16 (MMX_MOVDQ2Qrr VR128:$src))>;
656def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
657 (iPTR 0))))),
658 (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
659
660// CMOV* - Used to implement the SELECT DAG operation. Expanded by the
661// scheduler into a branch sequence.
662// These are expanded by the scheduler.
663let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
664 def CMOV_V1I64 : I<0, Pseudo,
665 (outs VR64:$dst), (ins VR64:$t, VR64:$f, i8imm:$cond),
666 "#CMOV_V1I64 PSEUDO!",
667 [(set VR64:$dst,
668 (v1i64 (X86cmov VR64:$t, VR64:$f, imm:$cond,
669 EFLAGS)))]>;
670}