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X86ISelDAGToDAG.cpp (193323) X86ISelDAGToDAG.cpp (193399)
1//===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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108}
109
110namespace {
111 //===--------------------------------------------------------------------===//
112 /// ISel - X86 specific code to select X86 machine instructions for
113 /// SelectionDAG operations.
114 ///
115 class VISIBILITY_HIDDEN X86DAGToDAGISel : public SelectionDAGISel {
1//===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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108}
109
110namespace {
111 //===--------------------------------------------------------------------===//
112 /// ISel - X86 specific code to select X86 machine instructions for
113 /// SelectionDAG operations.
114 ///
115 class VISIBILITY_HIDDEN X86DAGToDAGISel : public SelectionDAGISel {
116 /// TM - Keep a reference to X86TargetMachine.
117 ///
118 X86TargetMachine &TM;
119
120 /// X86Lowering - This object fully describes how to lower LLVM code to an
121 /// X86-specific SelectionDAG.
122 X86TargetLowering &X86Lowering;
123
124 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
125 /// make the right decision when generating code for different targets.
126 const X86Subtarget *Subtarget;
127
128 /// CurBB - Current BB being isel'd.
129 ///
130 MachineBasicBlock *CurBB;
131
132 /// OptForSize - If true, selector should try to optimize for code size
133 /// instead of performance.
134 bool OptForSize;
135
136 public:
137 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
138 : SelectionDAGISel(tm, OptLevel),
116 /// X86Lowering - This object fully describes how to lower LLVM code to an
117 /// X86-specific SelectionDAG.
118 X86TargetLowering &X86Lowering;
119
120 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
121 /// make the right decision when generating code for different targets.
122 const X86Subtarget *Subtarget;
123
124 /// CurBB - Current BB being isel'd.
125 ///
126 MachineBasicBlock *CurBB;
127
128 /// OptForSize - If true, selector should try to optimize for code size
129 /// instead of performance.
130 bool OptForSize;
131
132 public:
133 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
134 : SelectionDAGISel(tm, OptLevel),
139 TM(tm), X86Lowering(*TM.getTargetLowering()),
140 Subtarget(&TM.getSubtarget<X86Subtarget>()),
135 X86Lowering(*tm.getTargetLowering()),
136 Subtarget(&tm.getSubtarget<X86Subtarget>()),
141 OptForSize(false) {}
142
143 virtual const char *getPassName() const {
144 return "X86 DAG->DAG Instruction Selection";
145 }
146
147 /// InstructionSelect - This callback is invoked by
148 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.

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238 }
239
240 /// getGlobalBaseReg - Return an SDNode that returns the value of
241 /// the global base register. Output instructions required to
242 /// initialize the global base register, if necessary.
243 ///
244 SDNode *getGlobalBaseReg();
245
137 OptForSize(false) {}
138
139 virtual const char *getPassName() const {
140 return "X86 DAG->DAG Instruction Selection";
141 }
142
143 /// InstructionSelect - This callback is invoked by
144 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.

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234 }
235
236 /// getGlobalBaseReg - Return an SDNode that returns the value of
237 /// the global base register. Output instructions required to
238 /// initialize the global base register, if necessary.
239 ///
240 SDNode *getGlobalBaseReg();
241
242 /// getTargetMachine - Return a reference to the TargetMachine, casted
243 /// to the target-specific type.
244 const X86TargetMachine &getTargetMachine() {
245 return static_cast<const X86TargetMachine &>(TM);
246 }
247
248 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
249 /// to the target-specific type.
250 const X86InstrInfo *getInstrInfo() {
251 return getTargetMachine().getInstrInfo();
252 }
253
246#ifndef NDEBUG
247 unsigned Indent;
248#endif
249 };
250}
251
252
253bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,

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669 if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
670 !MatchSegmentBaseAddress (Address, AM))
671 return false;
672
673 return true;
674}
675
676bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
254#ifndef NDEBUG
255 unsigned Indent;
256#endif
257 };
258}
259
260
261bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,

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677 if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
678 !MatchSegmentBaseAddress (Address, AM))
679 return false;
680
681 return true;
682}
683
684bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
685 bool SymbolicAddressesAreRIPRel =
686 getTargetMachine().symbolicAddressesAreRIPRel();
677 bool is64Bit = Subtarget->is64Bit();
678 DOUT << "Wrapper: 64bit " << is64Bit;
679 DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
680
681 // Under X86-64 non-small code model, GV (and friends) are 64-bits.
682 if (is64Bit && (TM.getCodeModel() != CodeModel::Small))
683 return true;
684
685 // Base and index reg must be 0 in order to use rip as base.
686 bool canUsePICRel = !AM.Base.Reg.getNode() && !AM.IndexReg.getNode();
687 bool is64Bit = Subtarget->is64Bit();
688 DOUT << "Wrapper: 64bit " << is64Bit;
689 DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
690
691 // Under X86-64 non-small code model, GV (and friends) are 64-bits.
692 if (is64Bit && (TM.getCodeModel() != CodeModel::Small))
693 return true;
694
695 // Base and index reg must be 0 in order to use rip as base.
696 bool canUsePICRel = !AM.Base.Reg.getNode() && !AM.IndexReg.getNode();
687 if (is64Bit && !canUsePICRel && TM.symbolicAddressesAreRIPRel())
697 if (is64Bit && !canUsePICRel && SymbolicAddressesAreRIPRel)
688 return true;
689
690 if (AM.hasSymbolicDisplacement())
691 return true;
692 // If value is available in a register both base and index components have
693 // been picked, we can't fit the result available in the register in the
694 // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
695
696 SDValue N0 = N.getOperand(0);
697 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
698 uint64_t Offset = G->getOffset();
699 if (!is64Bit || isInt32(AM.Disp + Offset)) {
700 GlobalValue *GV = G->getGlobal();
698 return true;
699
700 if (AM.hasSymbolicDisplacement())
701 return true;
702 // If value is available in a register both base and index components have
703 // been picked, we can't fit the result available in the register in the
704 // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
705
706 SDValue N0 = N.getOperand(0);
707 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
708 uint64_t Offset = G->getOffset();
709 if (!is64Bit || isInt32(AM.Disp + Offset)) {
710 GlobalValue *GV = G->getGlobal();
701 bool isRIPRel = TM.symbolicAddressesAreRIPRel();
711 bool isRIPRel = SymbolicAddressesAreRIPRel;
702 if (N0.getOpcode() == llvm::ISD::TargetGlobalTLSAddress) {
703 TLSModel::Model model =
704 getTLSModel (GV, TM.getRelocationModel());
705 if (is64Bit && model == TLSModel::InitialExec)
706 isRIPRel = true;
707 }
708 AM.GV = GV;
709 AM.Disp += Offset;
710 AM.isRIPRel = isRIPRel;
711 return false;
712 }
713 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
714 uint64_t Offset = CP->getOffset();
715 if (!is64Bit || isInt32(AM.Disp + Offset)) {
716 AM.CP = CP->getConstVal();
717 AM.Align = CP->getAlignment();
718 AM.Disp += Offset;
712 if (N0.getOpcode() == llvm::ISD::TargetGlobalTLSAddress) {
713 TLSModel::Model model =
714 getTLSModel (GV, TM.getRelocationModel());
715 if (is64Bit && model == TLSModel::InitialExec)
716 isRIPRel = true;
717 }
718 AM.GV = GV;
719 AM.Disp += Offset;
720 AM.isRIPRel = isRIPRel;
721 return false;
722 }
723 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
724 uint64_t Offset = CP->getOffset();
725 if (!is64Bit || isInt32(AM.Disp + Offset)) {
726 AM.CP = CP->getConstVal();
727 AM.Align = CP->getAlignment();
728 AM.Disp += Offset;
719 AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
729 AM.isRIPRel = SymbolicAddressesAreRIPRel;
720 return false;
721 }
722 } else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) {
723 AM.ES = S->getSymbol();
730 return false;
731 }
732 } else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) {
733 AM.ES = S->getSymbol();
724 AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
734 AM.isRIPRel = SymbolicAddressesAreRIPRel;
725 return false;
726 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
727 AM.JT = J->getIndex();
735 return false;
736 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
737 AM.JT = J->getIndex();
728 AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
738 AM.isRIPRel = SymbolicAddressesAreRIPRel;
729 return false;
730 }
731
732 return true;
733}
734
735/// MatchAddress - Add the specified node to the specified addressing mode,
736/// returning true if it cannot be done. This just pattern matches for the

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1295}
1296
1297/// getGlobalBaseReg - Return an SDNode that returns the value of
1298/// the global base register. Output instructions required to
1299/// initialize the global base register, if necessary.
1300///
1301SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1302 MachineFunction *MF = CurBB->getParent();
739 return false;
740 }
741
742 return true;
743}
744
745/// MatchAddress - Add the specified node to the specified addressing mode,
746/// returning true if it cannot be done. This just pattern matches for the

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1305}
1306
1307/// getGlobalBaseReg - Return an SDNode that returns the value of
1308/// the global base register. Output instructions required to
1309/// initialize the global base register, if necessary.
1310///
1311SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1312 MachineFunction *MF = CurBB->getParent();
1303 unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
1313 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1304 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1305}
1306
1307static SDNode *FindCallStartFromCall(SDNode *Node) {
1308 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
1309 assert(Node->getOperand(0).getValueType() == MVT::Other &&
1310 "Node doesn't have a token chain argument!");
1311 return FindCallStartFromCall(Node->getOperand(0).getNode());

--- 405 unchanged lines hidden --- 		1314 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1315}
1316
1317static SDNode *FindCallStartFromCall(SDNode *Node) {
1318 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
1319 assert(Node->getOperand(0).getValueType() == MVT::Other &&
1320 "Node doesn't have a token chain argument!");
1321 return FindCallStartFromCall(Node->getOperand(0).getNode());

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