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SILowerControlFlow.cpp (263508) SILowerControlFlow.cpp (266715)
1//===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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104} // End anonymous namespace
105
106char SILowerControlFlowPass::ID = 0;
107
108FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
109 return new SILowerControlFlowPass(tm);
110}
111
1//===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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104} // End anonymous namespace
105
106char SILowerControlFlowPass::ID = 0;
107
108FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
109 return new SILowerControlFlowPass(tm);
110}
111
112static bool isDS(unsigned Opcode) {
113 switch(Opcode) {
114 default: return false;
115 case AMDGPU::DS_ADD_U32_RTN:
116 case AMDGPU::DS_SUB_U32_RTN:
117 case AMDGPU::DS_WRITE_B32:
118 case AMDGPU::DS_WRITE_B8:
119 case AMDGPU::DS_WRITE_B16:
120 case AMDGPU::DS_READ_B32:
121 case AMDGPU::DS_READ_I8:
122 case AMDGPU::DS_READ_U8:
123 case AMDGPU::DS_READ_I16:
124 case AMDGPU::DS_READ_U16:
125 return true;
126 }
127}
128
112bool SILowerControlFlowPass::shouldSkip(MachineBasicBlock *From,
113 MachineBasicBlock *To) {
114
115 unsigned NumInstr = 0;
116
117 for (MachineBasicBlock *MBB = From; MBB != To && !MBB->succ_empty();
118 MBB = *MBB->succ_begin()) {
119

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140 .addReg(AMDGPU::EXEC);
141}
142
143void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
144
145 MachineBasicBlock &MBB = *MI.getParent();
146 DebugLoc DL = MI.getDebugLoc();
147
129bool SILowerControlFlowPass::shouldSkip(MachineBasicBlock *From,
130 MachineBasicBlock *To) {
131
132 unsigned NumInstr = 0;
133
134 for (MachineBasicBlock *MBB = From; MBB != To && !MBB->succ_empty();
135 MBB = *MBB->succ_begin()) {
136

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157 .addReg(AMDGPU::EXEC);
158}
159
160void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
161
162 MachineBasicBlock &MBB = *MI.getParent();
163 DebugLoc DL = MI.getDebugLoc();
164
148 if (!shouldSkip(&MBB, &MBB.getParent()->back()))
165 if (MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType !=
166 ShaderType::PIXEL ||
167 !shouldSkip(&MBB, &MBB.getParent()->back()))
149 return;
150
151 MachineBasicBlock::iterator Insert = &MI;
152 ++Insert;
153
154 // If the exec mask is non-zero, skip the next two instructions
155 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
156 .addImm(3)

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291 assert(0);
292}
293
294void SILowerControlFlowPass::Kill(MachineInstr &MI) {
295
296 MachineBasicBlock &MBB = *MI.getParent();
297 DebugLoc DL = MI.getDebugLoc();
298
168 return;
169
170 MachineBasicBlock::iterator Insert = &MI;
171 ++Insert;
172
173 // If the exec mask is non-zero, skip the next two instructions
174 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
175 .addImm(3)

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310 assert(0);
311}
312
313void SILowerControlFlowPass::Kill(MachineInstr &MI) {
314
315 MachineBasicBlock &MBB = *MI.getParent();
316 DebugLoc DL = MI.getDebugLoc();
317
299 // Kill is only allowed in pixel shaders
318 // Kill is only allowed in pixel / geometry shaders
300 assert(MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
319 assert(MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
301 ShaderType::PIXEL);
320 ShaderType::PIXEL ||
321 MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
322 ShaderType::GEOMETRY);
302
303 // Clear this pixel from the exec mask if the operand is negative
304 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
305 .addImm(0)
306 .addOperand(MI.getOperand(0));
307
308 MI.eraseFromParent();
309}

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426 BI != BE; ++BI) {
427
428 MachineBasicBlock &MBB = *BI;
429 for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
430 I != MBB.end(); I = Next) {
431
432 Next = llvm::next(I);
433 MachineInstr &MI = *I;
323
324 // Clear this pixel from the exec mask if the operand is negative
325 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
326 .addImm(0)
327 .addOperand(MI.getOperand(0));
328
329 MI.eraseFromParent();
330}

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447 BI != BE; ++BI) {
448
449 MachineBasicBlock &MBB = *BI;
450 for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
451 I != MBB.end(); I = Next) {
452
453 Next = llvm::next(I);
454 MachineInstr &MI = *I;
455 if (isDS(MI.getOpcode())) {
456 NeedM0 = true;
457 NeedWQM = true;
458 }
459
434 switch (MI.getOpcode()) {
435 default: break;
436 case AMDGPU::SI_IF:
437 ++Depth;
438 If(MI);
439 break;
440
441 case AMDGPU::SI_ELSE:

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486 case AMDGPU::SI_INDIRECT_DST_V1:
487 case AMDGPU::SI_INDIRECT_DST_V2:
488 case AMDGPU::SI_INDIRECT_DST_V4:
489 case AMDGPU::SI_INDIRECT_DST_V8:
490 case AMDGPU::SI_INDIRECT_DST_V16:
491 IndirectDst(MI);
492 break;
493
460 switch (MI.getOpcode()) {
461 default: break;
462 case AMDGPU::SI_IF:
463 ++Depth;
464 If(MI);
465 break;
466
467 case AMDGPU::SI_ELSE:

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512 case AMDGPU::SI_INDIRECT_DST_V1:
513 case AMDGPU::SI_INDIRECT_DST_V2:
514 case AMDGPU::SI_INDIRECT_DST_V4:
515 case AMDGPU::SI_INDIRECT_DST_V8:
516 case AMDGPU::SI_INDIRECT_DST_V16:
517 IndirectDst(MI);
518 break;
519
494 case AMDGPU::DS_READ_B32:
495 NeedWQM = true;
496 // Fall through
497 case AMDGPU::DS_WRITE_B32:
498 case AMDGPU::DS_ADD_U32_RTN:
499 NeedM0 = true;
500 break;
501
502 case AMDGPU::V_INTERP_P1_F32:
503 case AMDGPU::V_INTERP_P2_F32:
504 case AMDGPU::V_INTERP_MOV_F32:
505 NeedWQM = true;
506 break;
507
508 }
509 }
510 }
511
512 if (NeedM0) {
513 MachineBasicBlock &MBB = MF.front();
514 // Initialize M0 to a value that won't cause LDS access to be discarded
515 // due to offset clamping
516 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_MOV_B32),
517 AMDGPU::M0).addImm(0xffffffff);
518 }
519
520 case AMDGPU::V_INTERP_P1_F32:
521 case AMDGPU::V_INTERP_P2_F32:
522 case AMDGPU::V_INTERP_MOV_F32:
523 NeedWQM = true;
524 break;
525
526 }
527 }
528 }
529
530 if (NeedM0) {
531 MachineBasicBlock &MBB = MF.front();
532 // Initialize M0 to a value that won't cause LDS access to be discarded
533 // due to offset clamping
534 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_MOV_B32),
535 AMDGPU::M0).addImm(0xffffffff);
536 }
537
520 if (NeedWQM && MFI->ShaderType != ShaderType::COMPUTE) {
538 if (NeedWQM && MFI->ShaderType == ShaderType::PIXEL) {
521 MachineBasicBlock &MBB = MF.front();
522 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),
523 AMDGPU::EXEC).addReg(AMDGPU::EXEC);
524 }
525
526 return true;
527}
539 MachineBasicBlock &MBB = MF.front();
540 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),
541 AMDGPU::EXEC).addReg(AMDGPU::EXEC);
542 }
543
544 return true;
545}