1//===-- SIIntrinsics.td - SI Intrinsic defs ----------------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Intrinsic Definitions
11//
12//===----------------------------------------------------------------------===//
13
14
15let TargetPrefix = "SI", isTarget = 1 in {
16
17 def int_SI_tid : Intrinsic <[llvm_i32_ty], [], [IntrNoMem]>;
18 def int_SI_packf16 : Intrinsic <[llvm_i32_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
19 def int_SI_export : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], []>;
20 def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
21 def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_anyint_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ;
22
23 // Fully-flexible TBUFFER_STORE_FORMAT_* except for the ADDR64 bit, which is not exposed
24 def int_SI_tbuffer_store : Intrinsic <
25 [],
26 [llvm_anyint_ty, // rsrc(SGPR)
27 llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
28 llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW
29 llvm_i32_ty, // vaddr(VGPR)
30 llvm_i32_ty, // soffset(SGPR)
31 llvm_i32_ty, // inst_offset(imm)
32 llvm_i32_ty, // dfmt(imm)
33 llvm_i32_ty, // nfmt(imm)
34 llvm_i32_ty, // offen(imm)
35 llvm_i32_ty, // idxen(imm)
36 llvm_i32_ty, // glc(imm)
37 llvm_i32_ty, // slc(imm)
38 llvm_i32_ty], // tfe(imm)
39 []>;
40
| 1//===-- SIIntrinsics.td - SI Intrinsic defs ----------------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Intrinsic Definitions
11//
12//===----------------------------------------------------------------------===//
13
14
15let TargetPrefix = "SI", isTarget = 1 in {
16
17 def int_SI_tid : Intrinsic <[llvm_i32_ty], [], [IntrNoMem]>;
18 def int_SI_packf16 : Intrinsic <[llvm_i32_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
19 def int_SI_export : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], []>;
20 def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
21 def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_anyint_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ;
22
23 // Fully-flexible TBUFFER_STORE_FORMAT_* except for the ADDR64 bit, which is not exposed
24 def int_SI_tbuffer_store : Intrinsic <
25 [],
26 [llvm_anyint_ty, // rsrc(SGPR)
27 llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
28 llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW
29 llvm_i32_ty, // vaddr(VGPR)
30 llvm_i32_ty, // soffset(SGPR)
31 llvm_i32_ty, // inst_offset(imm)
32 llvm_i32_ty, // dfmt(imm)
33 llvm_i32_ty, // nfmt(imm)
34 llvm_i32_ty, // offen(imm)
35 llvm_i32_ty, // idxen(imm)
36 llvm_i32_ty, // glc(imm)
37 llvm_i32_ty, // slc(imm)
38 llvm_i32_ty], // tfe(imm)
39 []>;
40
|
| 41 // Fully-flexible BUFFER_LOAD_DWORD_* except for the ADDR64 bit, which is not exposed
42 def int_SI_buffer_load_dword : Intrinsic <
43 [llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
44 [llvm_anyint_ty, // rsrc(SGPR)
45 llvm_anyint_ty, // vaddr(VGPR)
46 llvm_i32_ty, // soffset(SGPR)
47 llvm_i32_ty, // inst_offset(imm)
48 llvm_i32_ty, // offen(imm)
49 llvm_i32_ty, // idxen(imm)
50 llvm_i32_ty, // glc(imm)
51 llvm_i32_ty, // slc(imm)
52 llvm_i32_ty], // tfe(imm)
53 [IntrReadArgMem]>;
54
55 def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
56
|
41 class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
42
43 def int_SI_sample : Sample;
44 def int_SI_sampleb : Sample;
45 def int_SI_sampled : Sample;
46 def int_SI_samplel : Sample;
47
48 def int_SI_imageload : Intrinsic <[llvm_v4i32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
49
50 def int_SI_resinfo : Intrinsic <[llvm_v4i32_ty], [llvm_i32_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
51
52 /* Interpolation Intrinsics */
53
54 def int_SI_fs_constant : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
55 def int_SI_fs_interp : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_v2i32_ty], [IntrNoMem]>;
56
57 /* Control flow Intrinsics */
58
59 def int_SI_if : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_empty_ty], []>;
60 def int_SI_else : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_empty_ty], []>;
61 def int_SI_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], []>;
62 def int_SI_if_break : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_i64_ty], []>;
63 def int_SI_else_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], []>;
64 def int_SI_loop : Intrinsic<[], [llvm_i64_ty, llvm_empty_ty], []>;
65 def int_SI_end_cf : Intrinsic<[], [llvm_i64_ty], []>;
66}
| 57 class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
58
59 def int_SI_sample : Sample;
60 def int_SI_sampleb : Sample;
61 def int_SI_sampled : Sample;
62 def int_SI_samplel : Sample;
63
64 def int_SI_imageload : Intrinsic <[llvm_v4i32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
65
66 def int_SI_resinfo : Intrinsic <[llvm_v4i32_ty], [llvm_i32_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
67
68 /* Interpolation Intrinsics */
69
70 def int_SI_fs_constant : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
71 def int_SI_fs_interp : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_v2i32_ty], [IntrNoMem]>;
72
73 /* Control flow Intrinsics */
74
75 def int_SI_if : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_empty_ty], []>;
76 def int_SI_else : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_empty_ty], []>;
77 def int_SI_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], []>;
78 def int_SI_if_break : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_i64_ty], []>;
79 def int_SI_else_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], []>;
80 def int_SI_loop : Intrinsic<[], [llvm_i64_ty, llvm_empty_ty], []>;
81 def int_SI_end_cf : Intrinsic<[], [llvm_i64_ty], []>;
82}
|