1//===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
--- 8 unchanged lines hidden (view full) ---
17int P20 = 1;
18}
19def INTERP : InterpSlots;
20
21def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
23}
24
25def isSI : Predicate<"Subtarget.getGeneration() "
26 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
27
28def WAIT_FLAG : InstFlag<"printWaitFlag">;
29
30let Predicates = [isSI] in {
31
32let neverHasSideEffects = 1 in {
--- 788 unchanged lines hidden (view full) ---
821 let hasCtrlDep = 1;
822 let mayLoad = 1;
823 let mayStore = 1;
824}
825
826def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
827 []
828>;
829} // End hasSideEffects
830//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
831//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
832//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
833//def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>;
834//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
835//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
836//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
837//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
838//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
839//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
840
841def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
842 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
843 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
844 []
845>{
846 let DisableEncoding = "$vcc";
847}
--- 126 unchanged lines hidden (view full) ---
974defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
975//defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
976defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
977defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
978
979let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
980// No patterns so that the scalar instructions are always selected.
981// The scalar versions will be replaced with vector when needed later.
982defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", []>;
983defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", []>;
984defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], "V_SUB_I32">;
985
986let Uses = [VCC] in { // Carry-in comes from VCC
987defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>;
988defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>;
989defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], "V_SUBB_U32">;
990} // End Uses = [VCC]
991} // End isCommutable = 1, Defs = [VCC]
992
993defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
994////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
995////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
996////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
997defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
--- 400 unchanged lines hidden (view full) ---
1398def : Pat <
1399 (int_AMDGPU_kilp),
1400 (SI_KILL (V_MOV_B32_e32 0xbf800000))
1401>;
1402
1403/* int_SI_vs_load_input */
1404def : Pat<
1405 (SIload_input i128:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr),
1406 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset)
1407>;
1408
1409/* int_SI_export */
1410def : Pat <
1411 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1412 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1413 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1414 $src0, $src1, $src2, $src3)
--- 238 unchanged lines hidden (view full) ---
1653/********** =================== **********/
1654
1655def : Pat <
1656 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
1657 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1658 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
1659>;
1660
1661def : Pat <
1662 (fabs f32:$src),
1663 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1664 1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
1665>;
1666
1667def : Pat <
1668 (fneg f32:$src),
1669 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1670 0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */)
1671>;
1672
1673/********** ================== **********/
1674/********** Immediate Patterns **********/
1675/********** ================== **********/
1676
1677def : Pat <
1678 (SGPRImm<(i32 imm)>:$imm),
--- 110 unchanged lines hidden (view full) ---
1789 sub3)
1790>;
1791
1792def : Pat <
1793 (i32 (sext i1:$src0)),
1794 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
1795>;
1796
1797// 1. Offset as 8bit DWORD immediate
1798def : Pat <
1799 (SIload_constant i128:$sbase, IMM8bitDWORD:$offset),
1800 (S_BUFFER_LOAD_DWORD_IMM $sbase, IMM8bitDWORD:$offset)
1801>;
1802
1803// 2. Offset loaded in an 32bit SGPR
1804def : Pat <
1805 (SIload_constant i128:$sbase, imm:$offset),
1806 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1807>;
1808
1809// 3. Offset in an 32Bit VGPR
1810def : Pat <
1811 (SIload_constant i128:$sbase, i32:$voff),
1812 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff)
1813>;
1814
1815// The multiplication scales from [0,1] to the unsigned integer range
1816def : Pat <
1817 (AMDGPUurecip i32:$src0),
1818 (V_CVT_U32_F32_e32
1819 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
1820 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
--- 144 unchanged lines hidden (view full) ---
1965
1966defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>;
1967defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>;
1968defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>;
1969defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>;
1970defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>;
1971defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>;
1972
1973//===----------------------------------------------------------------------===//
1974// MTBUF Patterns
1975//===----------------------------------------------------------------------===//
1976
1977// TBUFFER_STORE_FORMAT_*, addr64=0
1978class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
1979 (SItbuffer_store i128:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
1980 i32:$soffset, imm:$inst_offset, imm:$dfmt,
--- 71 unchanged lines hidden (view full) ---
2052 (i32 (EXTRACT_SUBREG $x, sub1)), sub1)
2053>;
2054
2055def : Pat <
2056 (i32 (trunc i64:$a)),
2057 (EXTRACT_SUBREG $a, sub0)
2058>;
2059
2060// V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector
2061// case, the sgpr-copies pass will fix this to use the vector version.
2062def : Pat <
2063 (i32 (addc i32:$src0, i32:$src1)),
2064 (S_ADD_I32 $src0, $src1)
2065>;
2066
2067def : Pat <
--- 14 unchanged lines hidden ---
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
--- 8 unchanged lines hidden (view full) ---
17int P20 = 1;
18}
19def INTERP : InterpSlots;
20
21def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
23}
24
25def isSI : Predicate<"Subtarget.getGeneration() "
26 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
27
28def WAIT_FLAG : InstFlag<"printWaitFlag">;
29
30let Predicates = [isSI] in {
31
32let neverHasSideEffects = 1 in {
--- 788 unchanged lines hidden (view full) ---
821 let hasCtrlDep = 1;
822 let mayLoad = 1;
823 let mayStore = 1;
824}
825
826def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
827 []
828>;
829} // End hasSideEffects
830//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
831//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
832//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
833//def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>;
834//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
835//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
836//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
837//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
838//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
839//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
840
841def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
842 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
843 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
844 []
845>{
846 let DisableEncoding = "$vcc";
847}
--- 126 unchanged lines hidden (view full) ---
974defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
975//defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
976defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
977defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
978
979let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
980// No patterns so that the scalar instructions are always selected.
981// The scalar versions will be replaced with vector when needed later.
982defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", []>;
983defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", []>;
984defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], "V_SUB_I32">;
985
986let Uses = [VCC] in { // Carry-in comes from VCC
987defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>;
988defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>;
989defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], "V_SUBB_U32">;
990} // End Uses = [VCC]
991} // End isCommutable = 1, Defs = [VCC]
992
993defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
994////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
995////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
996////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
997defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
--- 400 unchanged lines hidden (view full) ---
1398def : Pat <
1399 (int_AMDGPU_kilp),
1400 (SI_KILL (V_MOV_B32_e32 0xbf800000))
1401>;
1402
1403/* int_SI_vs_load_input */
1404def : Pat<
1405 (SIload_input i128:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr),
1406 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset)
1407>;
1408
1409/* int_SI_export */
1410def : Pat <
1411 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1412 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1413 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1414 $src0, $src1, $src2, $src3)
--- 238 unchanged lines hidden (view full) ---
1653/********** =================== **********/
1654
1655def : Pat <
1656 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
1657 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1658 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
1659>;
1660
1661def : Pat <
1662 (fabs f32:$src),
1663 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1664 1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
1665>;
1666
1667def : Pat <
1668 (fneg f32:$src),
1669 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1670 0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */)
1671>;
1672
1673/********** ================== **********/
1674/********** Immediate Patterns **********/
1675/********** ================== **********/
1676
1677def : Pat <
1678 (SGPRImm<(i32 imm)>:$imm),
--- 110 unchanged lines hidden (view full) ---
1789 sub3)
1790>;
1791
1792def : Pat <
1793 (i32 (sext i1:$src0)),
1794 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
1795>;
1796
1797// 1. Offset as 8bit DWORD immediate
1798def : Pat <
1799 (SIload_constant i128:$sbase, IMM8bitDWORD:$offset),
1800 (S_BUFFER_LOAD_DWORD_IMM $sbase, IMM8bitDWORD:$offset)
1801>;
1802
1803// 2. Offset loaded in an 32bit SGPR
1804def : Pat <
1805 (SIload_constant i128:$sbase, imm:$offset),
1806 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1807>;
1808
1809// 3. Offset in an 32Bit VGPR
1810def : Pat <
1811 (SIload_constant i128:$sbase, i32:$voff),
1812 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff)
1813>;
1814
1815// The multiplication scales from [0,1] to the unsigned integer range
1816def : Pat <
1817 (AMDGPUurecip i32:$src0),
1818 (V_CVT_U32_F32_e32
1819 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
1820 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
--- 144 unchanged lines hidden (view full) ---
1965
1966defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>;
1967defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>;
1968defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>;
1969defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>;
1970defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>;
1971defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>;
1972
1973//===----------------------------------------------------------------------===//
1974// MTBUF Patterns
1975//===----------------------------------------------------------------------===//
1976
1977// TBUFFER_STORE_FORMAT_*, addr64=0
1978class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
1979 (SItbuffer_store i128:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
1980 i32:$soffset, imm:$inst_offset, imm:$dfmt,
--- 71 unchanged lines hidden (view full) ---
2052 (i32 (EXTRACT_SUBREG $x, sub1)), sub1)
2053>;
2054
2055def : Pat <
2056 (i32 (trunc i64:$a)),
2057 (EXTRACT_SUBREG $a, sub0)
2058>;
2059
2060// V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector
2061// case, the sgpr-copies pass will fix this to use the vector version.
2062def : Pat <
2063 (i32 (addc i32:$src0, i32:$src1)),
2064 (S_ADD_I32 $src0, $src1)
2065>;
2066
2067def : Pat <
--- 14 unchanged lines hidden ---