1//===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 276 unchanged lines hidden (view full) --- 285 string revOp = opName> 286 : VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern, revOp>; 287 288multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern, 289 string revOp = opName> 290 : VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern, revOp>; 291 292multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern, |
293 RegisterClass src0_rc, string revOp = opName> { |
294 295 def _e32 : VOP2 < |
296 op, (outs VReg_32:$dst), (ins src0_rc:$src0, VReg_32:$src1), |
297 opName#"_e32 $dst, $src0, $src1", pattern 298 >, VOP <opName>, VOP2_REV<revOp#"_e32", !eq(revOp, opName)>; 299 300 def _e64 : VOP3b < 301 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, 302 (outs VReg_32:$dst), 303 (ins VSrc_32:$src0, VSrc_32:$src1, 304 i32imm:$abs, i32imm:$clamp, --- 115 unchanged lines hidden (view full) --- 420 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", 421 []> { 422 let mayStore = 1; 423 let mayLoad = 0; 424} 425 426multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> { 427 |
428 let lds = 0, mayLoad = 1 in { |
429 |
430 let addr64 = 0 in { |
431 |
432 let offen = 0, idxen = 0 in { 433 def _OFFSET : MUBUF <op, (outs regClass:$vdata), 434 (ins SReg_128:$srsrc, VReg_32:$vaddr, 435 i16imm:$offset, SSrc_32:$soffset, i1imm:$glc, 436 i1imm:$slc, i1imm:$tfe), 437 asm#" $vdata, $srsrc + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>; 438 } |
439 |
440 let offen = 1, idxen = 0, offset = 0 in { 441 def _OFFEN : MUBUF <op, (outs regClass:$vdata), 442 (ins SReg_128:$srsrc, VReg_32:$vaddr, 443 SSrc_32:$soffset, i1imm:$glc, i1imm:$slc, 444 i1imm:$tfe), 445 asm#" $vdata, $srsrc + $vaddr + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>; 446 } 447 448 let offen = 0, idxen = 1 in { 449 def _IDXEN : MUBUF <op, (outs regClass:$vdata), 450 (ins SReg_128:$srsrc, VReg_32:$vaddr, 451 i16imm:$offset, SSrc_32:$soffset, i1imm:$glc, 452 i1imm:$slc, i1imm:$tfe), 453 asm#" $vdata, $srsrc[$vaddr] + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>; 454 } 455 456 let offen = 1, idxen = 1 in { 457 def _BOTHEN : MUBUF <op, (outs regClass:$vdata), 458 (ins SReg_128:$srsrc, VReg_64:$vaddr, 459 SSrc_32:$soffset, i1imm:$glc, 460 i1imm:$slc, i1imm:$tfe), 461 asm#" $vdata, $srsrc[$vaddr[0]] + $vaddr[1] + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>; 462 } 463 } 464 465 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in { 466 def _ADDR64 : MUBUF <op, (outs regClass:$vdata), 467 (ins SReg_128:$srsrc, VReg_64:$vaddr, i16imm:$offset), 468 asm#" $vdata, $srsrc + $vaddr + $offset", []>; 469 } |
470 } |
471} 472 473class MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> : 474 MUBUF <op, (outs), (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, 475 i16imm:$offset), 476 name#" $vdata, $srsrc + $vaddr + $offset", 477 []> { 478 --- 145 unchanged lines hidden --- |