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1//===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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1511 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
1512 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
1513 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
1514 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
1515 [(set i32:$dst, (int_AMDIL_bit_extract_u32 i32:$src0, i32:$src1,
1516 i32:$src2))],
1517 VecALU
1518 >;
1519 def : BFEPattern <BFE_UINT_eg>;
1519// XXX: This pattern is broken, disabling for now. See comment in
1520// AMDGPUInstructions.td for more info.
1521// def : BFEPattern <BFE_UINT_eg>;
1522
1523 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", [], VecALU>;
1524 defm : BFIPatterns <BFI_INT_eg>;
1525
1526 def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24",
1527 [(set i32:$dst, (add (mul U24:$src0, U24:$src1), i32:$src2))], VecALU
1528 >;
1529 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;

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1633 pattern
1634 > {
1635
1636 let src1 = 0;
1637 let src1_rel = 0;
1638 let src2 = 0;
1639 let src2_rel = 0;
1640
1639 let Defs = [OQAP];
1641 let usesCustomInserter = 1;
1642 let LDS_1A = 1;
1643 let DisableEncoding = "$dst";
1644}
1645
1646class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
1647 string dst =""> :
1648 R600_LDS <

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1668}
1669
1670class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> :
1671 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> {
1672
1673 let BaseOp = name;
1674 let usesCustomInserter = 1;
1675 let DisableEncoding = "$dst";
1675 let Defs = [OQAP];
1676}
1677
1678class R600_LDS_1A2D <bits<6> lds_op, string name, list<dag> pattern> :
1679 R600_LDS <
1680 lds_op,
1681 (outs),
1682 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
1683 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,

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