Cross Reference: /freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

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PPCISelDAGToDAG.cpp (263508)	PPCISelDAGToDAG.cpp (266715)
1//===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines a pattern matching instruction selector for PowerPC, 11// converting from a legalized dag to a PPC dag. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "ppc-codegen" 16#include "PPC.h" 17#include "MCTargetDesc/PPCPredicates.h" 18#include "PPCTargetMachine.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/MachineRegisterInfo.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/SelectionDAGISel.h" 24#include "llvm/IR/Constants.h" 25#include "llvm/IR/Function.h" 26#include "llvm/IR/GlobalAlias.h" 27#include "llvm/IR/GlobalValue.h" 28#include "llvm/IR/GlobalVariable.h" 29#include "llvm/IR/Intrinsics.h" 30#include "llvm/Support/Debug.h" 31#include "llvm/Support/ErrorHandling.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/Target/TargetOptions.h" 35using namespace llvm; 36 37namespace llvm { 38 void initializePPCDAGToDAGISelPass(PassRegistry&); 39} 40 41namespace { 42 //===--------------------------------------------------------------------===// 43 /// PPCDAGToDAGISel - PPC specific code to select PPC machine 44 /// instructions for SelectionDAG operations. 45 /// 46 class PPCDAGToDAGISel : public SelectionDAGISel { 47 const PPCTargetMachine &TM; 48 const PPCTargetLowering &PPCLowering; 49 const PPCSubtarget &PPCSubTarget; 50 unsigned GlobalBaseReg; 51 public: 52 explicit PPCDAGToDAGISel(PPCTargetMachine &tm) 53 : SelectionDAGISel(tm), TM(tm), 54 PPCLowering(TM.getTargetLowering()), 55 PPCSubTarget(TM.getSubtargetImpl()) { 56 initializePPCDAGToDAGISelPass(PassRegistry::getPassRegistry()); 57 } 58 59 virtual bool runOnMachineFunction(MachineFunction &MF) { 60 // Make sure we re-emit a set of the global base reg if necessary 61 GlobalBaseReg = 0; 62 SelectionDAGISel::runOnMachineFunction(MF); 63 64 if (!PPCSubTarget.isSVR4ABI()) 65 InsertVRSaveCode(MF); 66 67 return true; 68 } 69 70 virtual void PostprocessISelDAG(); 71 72 /// getI32Imm - Return a target constant with the specified value, of type 73 /// i32. 74 inline SDValue getI32Imm(unsigned Imm) { 75 return CurDAG->getTargetConstant(Imm, MVT::i32); 76 } 77 78 /// getI64Imm - Return a target constant with the specified value, of type 79 /// i64. 80 inline SDValue getI64Imm(uint64_t Imm) { 81 return CurDAG->getTargetConstant(Imm, MVT::i64); 82 } 83 84 /// getSmallIPtrImm - Return a target constant of pointer type. 85 inline SDValue getSmallIPtrImm(unsigned Imm) { 86 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); 87 } 88 89 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s 90 /// with any number of 0s on either side. The 1s are allowed to wrap from 91 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 92 /// 0x0F0F0000 is not, since all 1s are not contiguous. 93 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME); 94 95 96 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a 97 /// rotate and mask opcode and mask operation. 98 static bool isRotateAndMask(SDNode N, unsigned Mask, bool isShiftMask, 99 unsigned &SH, unsigned &MB, unsigned &ME); 100 101 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC 102 /// base register. Return the virtual register that holds this value. 103 SDNode getGlobalBaseReg(); 104* 105 // Select - Convert the specified operand from a target-independent to a 106 // target-specific node if it hasn't already been changed. 107 SDNode Select(SDNode N); 108 109 SDNode SelectBitfieldInsert(SDNode N); 110 111 /// SelectCC - Select a comparison of the specified values with the 112 /// specified condition code, returning the CR# of the expression. 113 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl); 114 115 /// SelectAddrImm - Returns true if the address N can be represented by 116 /// a base register plus a signed 16-bit displacement [r+imm]. 117 bool SelectAddrImm(SDValue N, SDValue &Disp, 118 SDValue &Base) { 119 return PPCLowering.SelectAddressRegImm(N, Disp, Base, CurDAG, false); 120* } 121 122 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc 123 /// immediate field. Note that the operand at this point is already the 124 /// result of a prior SelectAddressRegImm call. 125 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const { 126 if (N.getOpcode() == ISD::TargetConstant \|\| 127 N.getOpcode() == ISD::TargetGlobalAddress) { 128 Out = N; 129 return true; 130 } 131 132 return false; 133 } 134 135 /// SelectAddrIdx - Given the specified addressed, check to see if it can be 136 /// represented as an indexed [r+r] operation. Returns false if it can 137 /// be represented by [r+imm], which are preferred. 138 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) { 139 return PPCLowering.SelectAddressRegReg(N, Base, Index, CurDAG); 140* } 141 142 /// SelectAddrIdxOnly - Given the specified addressed, force it to be 143 /// represented as an indexed [r+r] operation. 144 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) { 145 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, CurDAG); 146* } 147 148 /// SelectAddrImmX4 - Returns true if the address N can be represented by 149 /// a base register plus a signed 16-bit displacement that is a multiple of 4. 150 /// Suitable for use by STD and friends. 151 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) { 152 return PPCLowering.SelectAddressRegImm(N, Disp, Base, CurDAG, true); 153* } 154 155 // Select an address into a single register. 156 bool SelectAddr(SDValue N, SDValue &Base) { 157 Base = N; 158 return true; 159 } 160 161 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 162 /// inline asm expressions. It is always correct to compute the value into 163 /// a register. The case of adding a (possibly relocatable) constant to a 164 /// register can be improved, but it is wrong to substitute Reg+Reg for 165 /// Reg in an asm, because the load or store opcode would have to change. 166 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 167 char ConstraintCode, 168 std::vector<SDValue> &OutOps) { 169 OutOps.push_back(Op); 170 return false; 171 } 172 173 void InsertVRSaveCode(MachineFunction &MF); 174 175 virtual const char getPassName() const { 176* return "PowerPC DAG->DAG Pattern Instruction Selection"; 177 } 178 179// Include the pieces autogenerated from the target description. 180#include "PPCGenDAGISel.inc" 181 182private: 183 SDNode SelectSETCC(SDNode N); 184 }; 185} 186 187/// InsertVRSaveCode - Once the entire function has been instruction selected, 188/// all virtual registers are created and all machine instructions are built, 189/// check to see if we need to save/restore VRSAVE. If so, do it. 190void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) { 191 // Check to see if this function uses vector registers, which means we have to 192 // save and restore the VRSAVE register and update it with the regs we use. 193 // 194 // In this case, there will be virtual registers of vector type created 195 // by the scheduler. Detect them now. 196 bool HasVectorVReg = false; 197 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) { 198 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 199 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { 200 HasVectorVReg = true; 201 break; 202 } 203 } 204 if (!HasVectorVReg) return; // nothing to do. 205 206 // If we have a vector register, we want to emit code into the entry and exit 207 // blocks to save and restore the VRSAVE register. We do this here (instead 208 // of marking all vector instructions as clobbering VRSAVE) for two reasons: 209 // 210 // 1. This (trivially) reduces the load on the register allocator, by not 211 // having to represent the live range of the VRSAVE register. 212 // 2. This (more significantly) allows us to create a temporary virtual 213 // register to hold the saved VRSAVE value, allowing this temporary to be 214 // register allocated, instead of forcing it to be spilled to the stack. 215 216 // Create two vregs - one to hold the VRSAVE register that is live-in to the 217 // function and one for the value after having bits or'd into it. 218 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 219 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 220 221 const TargetInstrInfo &TII = TM.getInstrInfo(); 222* MachineBasicBlock &EntryBB = Fn.begin(); 223* DebugLoc dl; 224 // Emit the following code into the entry block: 225 // InVRSAVE = MFVRSAVE 226 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE 227 // MTVRSAVE UpdatedVRSAVE 228 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point 229 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); 230 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), 231 UpdatedVRSAVE).addReg(InVRSAVE); 232 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); 233 234 // Find all return blocks, outputting a restore in each epilog. 235 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 236 if (!BB->empty() && BB->back().isReturn()) { 237 IP = BB->end(); --IP; 238 239 // Skip over all terminator instructions, which are part of the return 240 // sequence. 241 MachineBasicBlock::iterator I2 = IP; 242 while (I2 != BB->begin() && (--I2)->isTerminator()) 243 IP = I2; 244 245 // Emit: MTVRSAVE InVRSave 246 BuildMI(BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); 247* } 248 } 249} 250 251 252/// getGlobalBaseReg - Output the instructions required to put the 253/// base address to use for accessing globals into a register. 254/// 255SDNode PPCDAGToDAGISel::getGlobalBaseReg() { 256* if (!GlobalBaseReg) { 257 const TargetInstrInfo &TII = TM.getInstrInfo(); 258* // Insert the set of GlobalBaseReg into the first MBB of the function 259 MachineBasicBlock &FirstMBB = MF->front(); 260 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 261 DebugLoc dl; 262 263 if (PPCLowering.getPointerTy() == MVT::i32) {	1//===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines a pattern matching instruction selector for PowerPC, 11// converting from a legalized dag to a PPC dag. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "ppc-codegen" 16#include "PPC.h" 17#include "MCTargetDesc/PPCPredicates.h" 18#include "PPCTargetMachine.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/MachineRegisterInfo.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/SelectionDAGISel.h" 24#include "llvm/IR/Constants.h" 25#include "llvm/IR/Function.h" 26#include "llvm/IR/GlobalAlias.h" 27#include "llvm/IR/GlobalValue.h" 28#include "llvm/IR/GlobalVariable.h" 29#include "llvm/IR/Intrinsics.h" 30#include "llvm/Support/Debug.h" 31#include "llvm/Support/ErrorHandling.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/Target/TargetOptions.h" 35using namespace llvm; 36 37namespace llvm { 38 void initializePPCDAGToDAGISelPass(PassRegistry&); 39} 40 41namespace { 42 //===--------------------------------------------------------------------===// 43 /// PPCDAGToDAGISel - PPC specific code to select PPC machine 44 /// instructions for SelectionDAG operations. 45 /// 46 class PPCDAGToDAGISel : public SelectionDAGISel { 47 const PPCTargetMachine &TM; 48 const PPCTargetLowering &PPCLowering; 49 const PPCSubtarget &PPCSubTarget; 50 unsigned GlobalBaseReg; 51 public: 52 explicit PPCDAGToDAGISel(PPCTargetMachine &tm) 53 : SelectionDAGISel(tm), TM(tm), 54 PPCLowering(TM.getTargetLowering()), 55 PPCSubTarget(TM.getSubtargetImpl()) { 56 initializePPCDAGToDAGISelPass(PassRegistry::getPassRegistry()); 57 } 58 59 virtual bool runOnMachineFunction(MachineFunction &MF) { 60 // Make sure we re-emit a set of the global base reg if necessary 61 GlobalBaseReg = 0; 62 SelectionDAGISel::runOnMachineFunction(MF); 63 64 if (!PPCSubTarget.isSVR4ABI()) 65 InsertVRSaveCode(MF); 66 67 return true; 68 } 69 70 virtual void PostprocessISelDAG(); 71 72 /// getI32Imm - Return a target constant with the specified value, of type 73 /// i32. 74 inline SDValue getI32Imm(unsigned Imm) { 75 return CurDAG->getTargetConstant(Imm, MVT::i32); 76 } 77 78 /// getI64Imm - Return a target constant with the specified value, of type 79 /// i64. 80 inline SDValue getI64Imm(uint64_t Imm) { 81 return CurDAG->getTargetConstant(Imm, MVT::i64); 82 } 83 84 /// getSmallIPtrImm - Return a target constant of pointer type. 85 inline SDValue getSmallIPtrImm(unsigned Imm) { 86 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); 87 } 88 89 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s 90 /// with any number of 0s on either side. The 1s are allowed to wrap from 91 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 92 /// 0x0F0F0000 is not, since all 1s are not contiguous. 93 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME); 94 95 96 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a 97 /// rotate and mask opcode and mask operation. 98 static bool isRotateAndMask(SDNode N, unsigned Mask, bool isShiftMask, 99 unsigned &SH, unsigned &MB, unsigned &ME); 100 101 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC 102 /// base register. Return the virtual register that holds this value. 103 SDNode getGlobalBaseReg(); 104* 105 // Select - Convert the specified operand from a target-independent to a 106 // target-specific node if it hasn't already been changed. 107 SDNode Select(SDNode N); 108 109 SDNode SelectBitfieldInsert(SDNode N); 110 111 /// SelectCC - Select a comparison of the specified values with the 112 /// specified condition code, returning the CR# of the expression. 113 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl); 114 115 /// SelectAddrImm - Returns true if the address N can be represented by 116 /// a base register plus a signed 16-bit displacement [r+imm]. 117 bool SelectAddrImm(SDValue N, SDValue &Disp, 118 SDValue &Base) { 119 return PPCLowering.SelectAddressRegImm(N, Disp, Base, CurDAG, false); 120* } 121 122 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc 123 /// immediate field. Note that the operand at this point is already the 124 /// result of a prior SelectAddressRegImm call. 125 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const { 126 if (N.getOpcode() == ISD::TargetConstant \|\| 127 N.getOpcode() == ISD::TargetGlobalAddress) { 128 Out = N; 129 return true; 130 } 131 132 return false; 133 } 134 135 /// SelectAddrIdx - Given the specified addressed, check to see if it can be 136 /// represented as an indexed [r+r] operation. Returns false if it can 137 /// be represented by [r+imm], which are preferred. 138 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) { 139 return PPCLowering.SelectAddressRegReg(N, Base, Index, CurDAG); 140* } 141 142 /// SelectAddrIdxOnly - Given the specified addressed, force it to be 143 /// represented as an indexed [r+r] operation. 144 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) { 145 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, CurDAG); 146* } 147 148 /// SelectAddrImmX4 - Returns true if the address N can be represented by 149 /// a base register plus a signed 16-bit displacement that is a multiple of 4. 150 /// Suitable for use by STD and friends. 151 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) { 152 return PPCLowering.SelectAddressRegImm(N, Disp, Base, CurDAG, true); 153* } 154 155 // Select an address into a single register. 156 bool SelectAddr(SDValue N, SDValue &Base) { 157 Base = N; 158 return true; 159 } 160 161 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 162 /// inline asm expressions. It is always correct to compute the value into 163 /// a register. The case of adding a (possibly relocatable) constant to a 164 /// register can be improved, but it is wrong to substitute Reg+Reg for 165 /// Reg in an asm, because the load or store opcode would have to change. 166 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 167 char ConstraintCode, 168 std::vector<SDValue> &OutOps) { 169 OutOps.push_back(Op); 170 return false; 171 } 172 173 void InsertVRSaveCode(MachineFunction &MF); 174 175 virtual const char getPassName() const { 176* return "PowerPC DAG->DAG Pattern Instruction Selection"; 177 } 178 179// Include the pieces autogenerated from the target description. 180#include "PPCGenDAGISel.inc" 181 182private: 183 SDNode SelectSETCC(SDNode N); 184 }; 185} 186 187/// InsertVRSaveCode - Once the entire function has been instruction selected, 188/// all virtual registers are created and all machine instructions are built, 189/// check to see if we need to save/restore VRSAVE. If so, do it. 190void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) { 191 // Check to see if this function uses vector registers, which means we have to 192 // save and restore the VRSAVE register and update it with the regs we use. 193 // 194 // In this case, there will be virtual registers of vector type created 195 // by the scheduler. Detect them now. 196 bool HasVectorVReg = false; 197 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) { 198 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 199 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { 200 HasVectorVReg = true; 201 break; 202 } 203 } 204 if (!HasVectorVReg) return; // nothing to do. 205 206 // If we have a vector register, we want to emit code into the entry and exit 207 // blocks to save and restore the VRSAVE register. We do this here (instead 208 // of marking all vector instructions as clobbering VRSAVE) for two reasons: 209 // 210 // 1. This (trivially) reduces the load on the register allocator, by not 211 // having to represent the live range of the VRSAVE register. 212 // 2. This (more significantly) allows us to create a temporary virtual 213 // register to hold the saved VRSAVE value, allowing this temporary to be 214 // register allocated, instead of forcing it to be spilled to the stack. 215 216 // Create two vregs - one to hold the VRSAVE register that is live-in to the 217 // function and one for the value after having bits or'd into it. 218 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 219 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 220 221 const TargetInstrInfo &TII = TM.getInstrInfo(); 222* MachineBasicBlock &EntryBB = Fn.begin(); 223* DebugLoc dl; 224 // Emit the following code into the entry block: 225 // InVRSAVE = MFVRSAVE 226 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE 227 // MTVRSAVE UpdatedVRSAVE 228 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point 229 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); 230 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), 231 UpdatedVRSAVE).addReg(InVRSAVE); 232 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); 233 234 // Find all return blocks, outputting a restore in each epilog. 235 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 236 if (!BB->empty() && BB->back().isReturn()) { 237 IP = BB->end(); --IP; 238 239 // Skip over all terminator instructions, which are part of the return 240 // sequence. 241 MachineBasicBlock::iterator I2 = IP; 242 while (I2 != BB->begin() && (--I2)->isTerminator()) 243 IP = I2; 244 245 // Emit: MTVRSAVE InVRSave 246 BuildMI(BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); 247* } 248 } 249} 250 251 252/// getGlobalBaseReg - Output the instructions required to put the 253/// base address to use for accessing globals into a register. 254/// 255SDNode PPCDAGToDAGISel::getGlobalBaseReg() { 256* if (!GlobalBaseReg) { 257 const TargetInstrInfo &TII = TM.getInstrInfo(); 258* // Insert the set of GlobalBaseReg into the first MBB of the function 259 MachineBasicBlock &FirstMBB = MF->front(); 260 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 261 DebugLoc dl; 262 263 if (PPCLowering.getPointerTy() == MVT::i32) {
264 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);	264 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
265 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); 266 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); 267 } else {	265 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); 266 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); 267 } else {
268 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RCRegClass);	268 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
269 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8)); 270 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg); 271 } 272 } 273 return CurDAG->getRegister(GlobalBaseReg, 274 PPCLowering.getPointerTy()).getNode(); 275} 276 277/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 278/// or 64-bit immediate, and if the value can be accurately represented as a 279/// sign extension from a 16-bit value. If so, this returns true and the 280/// immediate. 281static bool isIntS16Immediate(SDNode N, short &Imm) { 282* if (N->getOpcode() != ISD::Constant) 283 return false; 284 285 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 286 if (N->getValueType(0) == MVT::i32) 287 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 288 else 289 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 290} 291 292static bool isIntS16Immediate(SDValue Op, short &Imm) { 293 return isIntS16Immediate(Op.getNode(), Imm); 294} 295 296 297/// isInt32Immediate - This method tests to see if the node is a 32-bit constant 298/// operand. If so Imm will receive the 32-bit value. 299static bool isInt32Immediate(SDNode N, unsigned &Imm) { 300* if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 301 Imm = cast<ConstantSDNode>(N)->getZExtValue(); 302 return true; 303 } 304 return false; 305} 306 307/// isInt64Immediate - This method tests to see if the node is a 64-bit constant 308/// operand. If so Imm will receive the 64-bit value. 309static bool isInt64Immediate(SDNode N, uint64_t &Imm) { 310* if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { 311 Imm = cast<ConstantSDNode>(N)->getZExtValue(); 312 return true; 313 } 314 return false; 315} 316 317// isInt32Immediate - This method tests to see if a constant operand. 318// If so Imm will receive the 32 bit value. 319static bool isInt32Immediate(SDValue N, unsigned &Imm) { 320 return isInt32Immediate(N.getNode(), Imm); 321} 322 323 324// isOpcWithIntImmediate - This method tests to see if the node is a specific 325// opcode and that it has a immediate integer right operand. 326// If so Imm will receive the 32 bit value. 327static bool isOpcWithIntImmediate(SDNode N, unsigned Opc, unsigned& Imm) { 328* return N->getOpcode() == Opc 329 && isInt32Immediate(N->getOperand(1).getNode(), Imm); 330} 331 332bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { 333 if (!Val) 334 return false; 335 336 if (isShiftedMask_32(Val)) { 337 // look for the first non-zero bit 338 MB = countLeadingZeros(Val); 339 // look for the first zero bit after the run of ones 340 ME = countLeadingZeros((Val - 1) ^ Val); 341 return true; 342 } else { 343 Val = ~Val; // invert mask 344 if (isShiftedMask_32(Val)) { 345 // effectively look for the first zero bit 346 ME = countLeadingZeros(Val) - 1; 347 // effectively look for the first one bit after the run of zeros 348 MB = countLeadingZeros((Val - 1) ^ Val) + 1; 349 return true; 350 } 351 } 352 // no run present 353 return false; 354} 355 356bool PPCDAGToDAGISel::isRotateAndMask(SDNode N, unsigned Mask, 357* bool isShiftMask, unsigned &SH, 358 unsigned &MB, unsigned &ME) { 359 // Don't even go down this path for i64, since different logic will be 360 // necessary for rldicl/rldicr/rldimi. 361 if (N->getValueType(0) != MVT::i32) 362 return false; 363 364 unsigned Shift = 32; 365 unsigned Indeterminant = ~0; // bit mask marking indeterminant results 366 unsigned Opcode = N->getOpcode(); 367 if (N->getNumOperands() != 2 \|\| 368 !isInt32Immediate(N->getOperand(1).getNode(), Shift) \|\| (Shift > 31)) 369 return false; 370 371 if (Opcode == ISD::SHL) { 372 // apply shift left to mask if it comes first 373 if (isShiftMask) Mask = Mask << Shift; 374 // determine which bits are made indeterminant by shift 375 Indeterminant = ~(0xFFFFFFFFu << Shift); 376 } else if (Opcode == ISD::SRL) { 377 // apply shift right to mask if it comes first 378 if (isShiftMask) Mask = Mask >> Shift; 379 // determine which bits are made indeterminant by shift 380 Indeterminant = ~(0xFFFFFFFFu >> Shift); 381 // adjust for the left rotate 382 Shift = 32 - Shift; 383 } else if (Opcode == ISD::ROTL) { 384 Indeterminant = 0; 385 } else { 386 return false; 387 } 388 389 // if the mask doesn't intersect any Indeterminant bits 390 if (Mask && !(Mask & Indeterminant)) { 391 SH = Shift & 31; 392 // make sure the mask is still a mask (wrap arounds may not be) 393 return isRunOfOnes(Mask, MB, ME); 394 } 395 return false; 396} 397 398/// SelectBitfieldInsert - turn an or of two masked values into 399/// the rotate left word immediate then mask insert (rlwimi) instruction. 400SDNode PPCDAGToDAGISel::SelectBitfieldInsert(SDNode N) { 401 SDValue Op0 = N->getOperand(0); 402 SDValue Op1 = N->getOperand(1); 403 SDLoc dl(N); 404 405 APInt LKZ, LKO, RKZ, RKO; 406 CurDAG->ComputeMaskedBits(Op0, LKZ, LKO); 407 CurDAG->ComputeMaskedBits(Op1, RKZ, RKO); 408 409 unsigned TargetMask = LKZ.getZExtValue(); 410 unsigned InsertMask = RKZ.getZExtValue(); 411 412 if ((TargetMask \| InsertMask) == 0xFFFFFFFF) { 413 unsigned Op0Opc = Op0.getOpcode(); 414 unsigned Op1Opc = Op1.getOpcode(); 415 unsigned Value, SH = 0; 416 TargetMask = ~TargetMask; 417 InsertMask = ~InsertMask; 418 419 // If the LHS has a foldable shift and the RHS does not, then swap it to the 420 // RHS so that we can fold the shift into the insert. 421 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) { 422 if (Op0.getOperand(0).getOpcode() == ISD::SHL \|\| 423 Op0.getOperand(0).getOpcode() == ISD::SRL) { 424 if (Op1.getOperand(0).getOpcode() != ISD::SHL && 425 Op1.getOperand(0).getOpcode() != ISD::SRL) { 426 std::swap(Op0, Op1); 427 std::swap(Op0Opc, Op1Opc); 428 std::swap(TargetMask, InsertMask); 429 } 430 } 431 } else if (Op0Opc == ISD::SHL \|\| Op0Opc == ISD::SRL) { 432 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && 433 Op1.getOperand(0).getOpcode() != ISD::SRL) { 434 std::swap(Op0, Op1); 435 std::swap(Op0Opc, Op1Opc); 436 std::swap(TargetMask, InsertMask); 437 } 438 } 439 440 unsigned MB, ME; 441 if (isRunOfOnes(InsertMask, MB, ME)) { 442 SDValue Tmp1, Tmp2; 443 444 if ((Op1Opc == ISD::SHL \|\| Op1Opc == ISD::SRL) && 445 isInt32Immediate(Op1.getOperand(1), Value)) { 446 Op1 = Op1.getOperand(0); 447 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; 448 } 449 if (Op1Opc == ISD::AND) { 450 unsigned SHOpc = Op1.getOperand(0).getOpcode(); 451 if ((SHOpc == ISD::SHL \|\| SHOpc == ISD::SRL) && 452 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) { 453 // Note that Value must be in range here (less than 32) because 454 // otherwise there would not be any bits set in InsertMask. 455 Op1 = Op1.getOperand(0).getOperand(0); 456 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; 457 } 458 } 459 460 SH &= 31; 461 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB), 462 getI32Imm(ME) }; 463 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); 464 } 465 } 466 return 0; 467} 468 469/// SelectCC - Select a comparison of the specified values with the specified 470/// condition code, returning the CR# of the expression. 471SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, 472 ISD::CondCode CC, SDLoc dl) { 473 // Always select the LHS. 474 unsigned Opc; 475 476 if (LHS.getValueType() == MVT::i32) { 477 unsigned Imm; 478 if (CC == ISD::SETEQ \|\| CC == ISD::SETNE) { 479 if (isInt32Immediate(RHS, Imm)) { 480 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 481 if (isUInt<16>(Imm)) 482 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, 483 getI32Imm(Imm & 0xFFFF)), 0); 484 // If this is a 16-bit signed immediate, fold it. 485 if (isInt<16>((int)Imm)) 486 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, 487 getI32Imm(Imm & 0xFFFF)), 0); 488 489 // For non-equality comparisons, the default code would materialize the 490 // constant, then compare against it, like this: 491 // lis r2, 4660 492 // ori r2, r2, 22136 493 // cmpw cr0, r3, r2 494 // Since we are just comparing for equality, we can emit this instead: 495 // xoris r0,r3,0x1234 496 // cmplwi cr0,r0,0x5678 497 // beq cr0,L6 498 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS, 499 getI32Imm(Imm >> 16)), 0); 500 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor, 501 getI32Imm(Imm & 0xFFFF)), 0); 502 } 503 Opc = PPC::CMPLW; 504 } else if (ISD::isUnsignedIntSetCC(CC)) { 505 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm)) 506 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, 507 getI32Imm(Imm & 0xFFFF)), 0); 508 Opc = PPC::CMPLW; 509 } else { 510 short SImm; 511 if (isIntS16Immediate(RHS, SImm)) 512 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, 513 getI32Imm((int)SImm & 0xFFFF)), 514 0); 515 Opc = PPC::CMPW; 516 } 517 } else if (LHS.getValueType() == MVT::i64) { 518 uint64_t Imm; 519 if (CC == ISD::SETEQ \|\| CC == ISD::SETNE) { 520 if (isInt64Immediate(RHS.getNode(), Imm)) { 521 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 522 if (isUInt<16>(Imm)) 523 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, 524 getI32Imm(Imm & 0xFFFF)), 0); 525 // If this is a 16-bit signed immediate, fold it. 526 if (isInt<16>(Imm)) 527 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, 528 getI32Imm(Imm & 0xFFFF)), 0); 529 530 // For non-equality comparisons, the default code would materialize the 531 // constant, then compare against it, like this: 532 // lis r2, 4660 533 // ori r2, r2, 22136 534 // cmpd cr0, r3, r2 535 // Since we are just comparing for equality, we can emit this instead: 536 // xoris r0,r3,0x1234 537 // cmpldi cr0,r0,0x5678 538 // beq cr0,L6 539 if (isUInt<32>(Imm)) { 540 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS, 541 getI64Imm(Imm >> 16)), 0); 542 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor, 543 getI64Imm(Imm & 0xFFFF)), 0); 544 } 545 } 546 Opc = PPC::CMPLD; 547 } else if (ISD::isUnsignedIntSetCC(CC)) { 548 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm)) 549 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, 550 getI64Imm(Imm & 0xFFFF)), 0); 551 Opc = PPC::CMPLD; 552 } else { 553 short SImm; 554 if (isIntS16Immediate(RHS, SImm)) 555 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, 556 getI64Imm(SImm & 0xFFFF)), 557 0); 558 Opc = PPC::CMPD; 559 } 560 } else if (LHS.getValueType() == MVT::f32) { 561 Opc = PPC::FCMPUS; 562 } else { 563 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!"); 564 Opc = PPC::FCMPUD; 565 } 566 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0); 567} 568 569static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { 570 switch (CC) { 571 case ISD::SETUEQ: 572 case ISD::SETONE: 573 case ISD::SETOLE: 574 case ISD::SETOGE: 575 llvm_unreachable("Should be lowered by legalize!"); 576 default: llvm_unreachable("Unknown condition!"); 577 case ISD::SETOEQ: 578 case ISD::SETEQ: return PPC::PRED_EQ; 579 case ISD::SETUNE: 580 case ISD::SETNE: return PPC::PRED_NE; 581 case ISD::SETOLT: 582 case ISD::SETLT: return PPC::PRED_LT; 583 case ISD::SETULE: 584 case ISD::SETLE: return PPC::PRED_LE; 585 case ISD::SETOGT: 586 case ISD::SETGT: return PPC::PRED_GT; 587 case ISD::SETUGE: 588 case ISD::SETGE: return PPC::PRED_GE; 589 case ISD::SETO: return PPC::PRED_NU; 590 case ISD::SETUO: return PPC::PRED_UN; 591 // These two are invalid for floating point. Assume we have int. 592 case ISD::SETULT: return PPC::PRED_LT; 593 case ISD::SETUGT: return PPC::PRED_GT; 594 } 595} 596 597/// getCRIdxForSetCC - Return the index of the condition register field 598/// associated with the SetCC condition, and whether or not the field is 599/// treated as inverted. That is, lt = 0; ge = 0 inverted. 600static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { 601 Invert = false; 602 switch (CC) { 603 default: llvm_unreachable("Unknown condition!"); 604 case ISD::SETOLT: 605 case ISD::SETLT: return 0; // Bit #0 = SETOLT 606 case ISD::SETOGT: 607 case ISD::SETGT: return 1; // Bit #1 = SETOGT 608 case ISD::SETOEQ: 609 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ 610 case ISD::SETUO: return 3; // Bit #3 = SETUO 611 case ISD::SETUGE: 612 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE 613 case ISD::SETULE: 614 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE 615 case ISD::SETUNE: 616 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE 617 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO 618 case ISD::SETUEQ: 619 case ISD::SETOGE: 620 case ISD::SETOLE: 621 case ISD::SETONE: 622 llvm_unreachable("Invalid branch code: should be expanded by legalize"); 623 // These are invalid for floating point. Assume integer. 624 case ISD::SETULT: return 0; 625 case ISD::SETUGT: return 1; 626 } 627} 628 629// getVCmpInst: return the vector compare instruction for the specified 630// vector type and condition code. Since this is for altivec specific code, 631// only support the altivec types (v16i8, v8i16, v4i32, and v4f32). 632static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC) { 633 switch (CC) { 634 case ISD::SETEQ: 635 case ISD::SETUEQ: 636 case ISD::SETNE: 637 case ISD::SETUNE: 638 if (VecVT == MVT::v16i8) 639 return PPC::VCMPEQUB; 640 else if (VecVT == MVT::v8i16) 641 return PPC::VCMPEQUH; 642 else if (VecVT == MVT::v4i32) 643 return PPC::VCMPEQUW; 644 // v4f32 != v4f32 could be translate to unordered not equal 645 else if (VecVT == MVT::v4f32) 646 return PPC::VCMPEQFP; 647 break; 648 case ISD::SETLT: 649 case ISD::SETGT: 650 case ISD::SETLE: 651 case ISD::SETGE: 652 if (VecVT == MVT::v16i8) 653 return PPC::VCMPGTSB; 654 else if (VecVT == MVT::v8i16) 655 return PPC::VCMPGTSH; 656 else if (VecVT == MVT::v4i32) 657 return PPC::VCMPGTSW; 658 else if (VecVT == MVT::v4f32) 659 return PPC::VCMPGTFP; 660 break; 661 case ISD::SETULT: 662 case ISD::SETUGT: 663 case ISD::SETUGE: 664 case ISD::SETULE: 665 if (VecVT == MVT::v16i8) 666 return PPC::VCMPGTUB; 667 else if (VecVT == MVT::v8i16) 668 return PPC::VCMPGTUH; 669 else if (VecVT == MVT::v4i32) 670 return PPC::VCMPGTUW; 671 break; 672 case ISD::SETOEQ: 673 if (VecVT == MVT::v4f32) 674 return PPC::VCMPEQFP; 675 break; 676 case ISD::SETOLT: 677 case ISD::SETOGT: 678 case ISD::SETOLE: 679 if (VecVT == MVT::v4f32) 680 return PPC::VCMPGTFP; 681 break; 682 case ISD::SETOGE: 683 if (VecVT == MVT::v4f32) 684 return PPC::VCMPGEFP; 685 break; 686 default: 687 break; 688 } 689 llvm_unreachable("Invalid integer vector compare condition"); 690} 691 692// getVCmpEQInst: return the equal compare instruction for the specified vector 693// type. Since this is for altivec specific code, only support the altivec 694// types (v16i8, v8i16, v4i32, and v4f32). 695static unsigned int getVCmpEQInst(MVT::SimpleValueType VecVT) { 696 switch (VecVT) { 697 case MVT::v16i8: 698 return PPC::VCMPEQUB; 699 case MVT::v8i16: 700 return PPC::VCMPEQUH; 701 case MVT::v4i32: 702 return PPC::VCMPEQUW; 703 case MVT::v4f32: 704 return PPC::VCMPEQFP; 705 default: 706 llvm_unreachable("Invalid integer vector compare condition"); 707 } 708} 709 710 711SDNode PPCDAGToDAGISel::SelectSETCC(SDNode N) { 712 SDLoc dl(N); 713 unsigned Imm; 714 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 715 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy(); 716 bool isPPC64 = (PtrVT == MVT::i64); 717 718 if (isInt32Immediate(N->getOperand(1), Imm)) { 719 // We can codegen setcc op, imm very efficiently compared to a brcond. 720 // Check for those cases here. 721 // setcc op, 0 722 if (Imm == 0) { 723 SDValue Op = N->getOperand(0); 724 switch (CC) { 725 default: break; 726 case ISD::SETEQ: { 727 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); 728 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; 729 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 730 } 731 case ISD::SETNE: { 732 if (isPPC64) break; 733 SDValue AD = 734 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 735 Op, getI32Imm(~0U)), 0); 736 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, 737 AD.getValue(1)); 738 } 739 case ISD::SETLT: { 740 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 741 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 742 } 743 case ISD::SETGT: { 744 SDValue T = 745 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0); 746 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0); 747 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 748 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 749 } 750 } 751 } else if (Imm == ~0U) { // setcc op, -1 752 SDValue Op = N->getOperand(0); 753 switch (CC) { 754 default: break; 755 case ISD::SETEQ: 756 if (isPPC64) break; 757 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 758 Op, getI32Imm(1)), 0); 759 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 760 SDValue(CurDAG->getMachineNode(PPC::LI, dl, 761 MVT::i32, 762 getI32Imm(0)), 0), 763 Op.getValue(1)); 764 case ISD::SETNE: { 765 if (isPPC64) break; 766 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); 767 SDNode AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 768* Op, getI32Imm(~0U)); 769 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), 770 Op, SDValue(AD, 1)); 771 } 772 case ISD::SETLT: { 773 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op, 774 getI32Imm(1)), 0); 775 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD, 776 Op), 0); 777 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 778 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 779 } 780 case ISD::SETGT: { 781 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 782 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 783 0); 784 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, 785 getI32Imm(1)); 786 } 787 } 788 } 789 } 790 791 SDValue LHS = N->getOperand(0); 792 SDValue RHS = N->getOperand(1); 793 794 // Altivec Vector compare instructions do not set any CR register by default and 795 // vector compare operations return the same type as the operands. 796 if (LHS.getValueType().isVector()) { 797 EVT VecVT = LHS.getValueType(); 798 MVT::SimpleValueType VT = VecVT.getSimpleVT().SimpleTy; 799 unsigned int VCmpInst = getVCmpInst(VT, CC); 800 801 switch (CC) { 802 case ISD::SETEQ: 803 case ISD::SETOEQ: 804 case ISD::SETUEQ: 805 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); 806 case ISD::SETNE: 807 case ISD::SETONE: 808 case ISD::SETUNE: { 809 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0); 810 return CurDAG->SelectNodeTo(N, PPC::VNOR, VecVT, VCmp, VCmp); 811 } 812 case ISD::SETLT: 813 case ISD::SETOLT: 814 case ISD::SETULT: 815 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, RHS, LHS); 816 case ISD::SETGT: 817 case ISD::SETOGT: 818 case ISD::SETUGT: 819 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); 820 case ISD::SETGE: 821 case ISD::SETOGE: 822 case ISD::SETUGE: { 823 // Small optimization: Altivec provides a 'Vector Compare Greater Than 824 // or Equal To' instruction (vcmpgefp), so in this case there is no 825 // need for extra logic for the equal compare. 826 if (VecVT.getSimpleVT().isFloatingPoint()) { 827 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); 828 } else { 829 SDValue VCmpGT(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0); 830 unsigned int VCmpEQInst = getVCmpEQInst(VT); 831 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0); 832 return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpGT, VCmpEQ); 833 } 834 } 835 case ISD::SETLE: 836 case ISD::SETOLE: 837 case ISD::SETULE: { 838 SDValue VCmpLE(CurDAG->getMachineNode(VCmpInst, dl, VecVT, RHS, LHS), 0); 839 unsigned int VCmpEQInst = getVCmpEQInst(VT); 840 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0); 841 return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpLE, VCmpEQ); 842 } 843 default: 844 llvm_unreachable("Invalid vector compare type: should be expanded by legalize"); 845 } 846 } 847 848 bool Inv; 849 unsigned Idx = getCRIdxForSetCC(CC, Inv); 850 SDValue CCReg = SelectCC(LHS, RHS, CC, dl); 851 SDValue IntCR; 852 853 // Force the ccreg into CR7. 854 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); 855 856 SDValue InFlag(0, 0); // Null incoming flag value. 857 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg, 858 InFlag).getValue(1); 859 860 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, 861 CCReg), 0); 862 863 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), 864 getI32Imm(31), getI32Imm(31) }; 865 if (!Inv) 866 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 867 868 // Get the specified bit. 869 SDValue Tmp = 870 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0); 871 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); 872} 873 874 875// Select - Convert the specified operand from a target-independent to a 876// target-specific node if it hasn't already been changed. 877SDNode PPCDAGToDAGISel::Select(SDNode N) { 878 SDLoc dl(N); 879 if (N->isMachineOpcode()) { 880 N->setNodeId(-1); 881 return NULL; // Already selected. 882 } 883 884 switch (N->getOpcode()) { 885 default: break; 886 887 case ISD::Constant: { 888 if (N->getValueType(0) == MVT::i64) { 889 // Get 64 bit value. 890 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue(); 891 // Assume no remaining bits. 892 unsigned Remainder = 0; 893 // Assume no shift required. 894 unsigned Shift = 0; 895 896 // If it can't be represented as a 32 bit value. 897 if (!isInt<32>(Imm)) { 898 Shift = countTrailingZeros<uint64_t>(Imm); 899 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift; 900 901 // If the shifted value fits 32 bits. 902 if (isInt<32>(ImmSh)) { 903 // Go with the shifted value. 904 Imm = ImmSh; 905 } else { 906 // Still stuck with a 64 bit value. 907 Remainder = Imm; 908 Shift = 32; 909 Imm >>= 32; 910 } 911 } 912 913 // Intermediate operand. 914 SDNode Result; 915* 916 // Handle first 32 bits. 917 unsigned Lo = Imm & 0xFFFF; 918 unsigned Hi = (Imm >> 16) & 0xFFFF; 919 920 // Simple value. 921 if (isInt<16>(Imm)) { 922 // Just the Lo bits. 923 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo)); 924 } else if (Lo) { 925 // Handle the Hi bits. 926 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8; 927 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi)); 928 // And Lo bits. 929 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, 930 SDValue(Result, 0), getI32Imm(Lo)); 931 } else { 932 // Just the Hi bits. 933 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi)); 934 } 935 936 // If no shift, we're done. 937 if (!Shift) return Result; 938 939 // Shift for next step if the upper 32-bits were not zero. 940 if (Imm) { 941 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, 942 SDValue(Result, 0), 943 getI32Imm(Shift), 944 getI32Imm(63 - Shift)); 945 } 946 947 // Add in the last bits as required. 948 if ((Hi = (Remainder >> 16) & 0xFFFF)) { 949 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64, 950 SDValue(Result, 0), getI32Imm(Hi)); 951 } 952 if ((Lo = Remainder & 0xFFFF)) { 953 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, 954 SDValue(Result, 0), getI32Imm(Lo)); 955 } 956 957 return Result; 958 } 959 break; 960 } 961 962 case ISD::SETCC: 963 return SelectSETCC(N); 964 case PPCISD::GlobalBaseReg: 965 return getGlobalBaseReg(); 966 967 case ISD::FrameIndex: { 968 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 969 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0)); 970 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8; 971 if (N->hasOneUse()) 972 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI, 973 getSmallIPtrImm(0)); 974 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI, 975 getSmallIPtrImm(0)); 976 } 977 978 case PPCISD::MFOCRF: { 979 SDValue InFlag = N->getOperand(1); 980 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, 981 N->getOperand(0), InFlag); 982 } 983 984 case ISD::SDIV: { 985 // FIXME: since this depends on the setting of the carry flag from the srawi 986 // we should really be making notes about that for the scheduler. 987 // FIXME: It sure would be nice if we could cheaply recognize the 988 // srl/add/sra pattern the dag combiner will generate for this as 989 // sra/addze rather than having to handle sdiv ourselves. oh well. 990 unsigned Imm; 991 if (isInt32Immediate(N->getOperand(1), Imm)) { 992 SDValue N0 = N->getOperand(0); 993 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { 994 SDNode Op = 995* CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue, 996 N0, getI32Imm(Log2_32(Imm))); 997 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 998 SDValue(Op, 0), SDValue(Op, 1)); 999 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { 1000 SDNode Op = 1001* CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue, 1002 N0, getI32Imm(Log2_32(-Imm))); 1003 SDValue PT = 1004 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32, 1005 SDValue(Op, 0), SDValue(Op, 1)), 1006 0); 1007 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); 1008 } 1009 } 1010 1011 // Other cases are autogenerated. 1012 break; 1013 } 1014 1015 case ISD::LOAD: { 1016 // Handle preincrement loads. 1017 LoadSDNode LD = cast<LoadSDNode>(N); 1018* EVT LoadedVT = LD->getMemoryVT(); 1019 1020 // Normal loads are handled by code generated from the .td file. 1021 if (LD->getAddressingMode() != ISD::PRE_INC) 1022 break; 1023 1024 SDValue Offset = LD->getOffset(); 1025 if (Offset.getOpcode() == ISD::TargetConstant \|\| 1026 Offset.getOpcode() == ISD::TargetGlobalAddress) { 1027 1028 unsigned Opcode; 1029 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; 1030 if (LD->getValueType(0) != MVT::i64) { 1031 // Handle PPC32 integer and normal FP loads. 1032 assert((!isSExt \|\| LoadedVT == MVT::i16) && "Invalid sext update load"); 1033 switch (LoadedVT.getSimpleVT().SimpleTy) { 1034 default: llvm_unreachable("Invalid PPC load type!"); 1035 case MVT::f64: Opcode = PPC::LFDU; break; 1036 case MVT::f32: Opcode = PPC::LFSU; break; 1037 case MVT::i32: Opcode = PPC::LWZU; break; 1038 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; 1039 case MVT::i1: 1040 case MVT::i8: Opcode = PPC::LBZU; break; 1041 } 1042 } else { 1043 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); 1044 assert((!isSExt \|\| LoadedVT == MVT::i16) && "Invalid sext update load"); 1045 switch (LoadedVT.getSimpleVT().SimpleTy) { 1046 default: llvm_unreachable("Invalid PPC load type!"); 1047 case MVT::i64: Opcode = PPC::LDU; break; 1048 case MVT::i32: Opcode = PPC::LWZU8; break; 1049 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; 1050 case MVT::i1: 1051 case MVT::i8: Opcode = PPC::LBZU8; break; 1052 } 1053 } 1054 1055 SDValue Chain = LD->getChain(); 1056 SDValue Base = LD->getBasePtr(); 1057 SDValue Ops[] = { Offset, Base, Chain }; 1058 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), 1059 PPCLowering.getPointerTy(), 1060 MVT::Other, Ops); 1061 } else { 1062 unsigned Opcode; 1063 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; 1064 if (LD->getValueType(0) != MVT::i64) { 1065 // Handle PPC32 integer and normal FP loads. 1066 assert((!isSExt \|\| LoadedVT == MVT::i16) && "Invalid sext update load"); 1067 switch (LoadedVT.getSimpleVT().SimpleTy) { 1068 default: llvm_unreachable("Invalid PPC load type!"); 1069 case MVT::f64: Opcode = PPC::LFDUX; break; 1070 case MVT::f32: Opcode = PPC::LFSUX; break; 1071 case MVT::i32: Opcode = PPC::LWZUX; break; 1072 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; 1073 case MVT::i1: 1074 case MVT::i8: Opcode = PPC::LBZUX; break; 1075 } 1076 } else { 1077 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); 1078 assert((!isSExt \|\| LoadedVT == MVT::i16 \|\| LoadedVT == MVT::i32) && 1079 "Invalid sext update load"); 1080 switch (LoadedVT.getSimpleVT().SimpleTy) { 1081 default: llvm_unreachable("Invalid PPC load type!"); 1082 case MVT::i64: Opcode = PPC::LDUX; break; 1083 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break; 1084 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break; 1085 case MVT::i1: 1086 case MVT::i8: Opcode = PPC::LBZUX8; break; 1087 } 1088 } 1089 1090 SDValue Chain = LD->getChain(); 1091 SDValue Base = LD->getBasePtr(); 1092 SDValue Ops[] = { Base, Offset, Chain }; 1093 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), 1094 PPCLowering.getPointerTy(), 1095 MVT::Other, Ops); 1096 } 1097 } 1098 1099 case ISD::AND: { 1100 unsigned Imm, Imm2, SH, MB, ME; 1101 uint64_t Imm64; 1102 1103 // If this is an and of a value rotated between 0 and 31 bits and then and'd 1104 // with a mask, emit rlwinm 1105 if (isInt32Immediate(N->getOperand(1), Imm) && 1106 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) { 1107 SDValue Val = N->getOperand(0).getOperand(0); 1108 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1109 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1110 } 1111 // If this is just a masked value where the input is not handled above, and 1112 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm 1113 if (isInt32Immediate(N->getOperand(1), Imm) && 1114 isRunOfOnes(Imm, MB, ME) && 1115 N->getOperand(0).getOpcode() != ISD::ROTL) { 1116 SDValue Val = N->getOperand(0); 1117 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) }; 1118 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1119 } 1120 // If this is a 64-bit zero-extension mask, emit rldicl. 1121 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) && 1122 isMask_64(Imm64)) { 1123 SDValue Val = N->getOperand(0); 1124 MB = 64 - CountTrailingOnes_64(Imm64); 1125 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB) }; 1126 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops, 3); 1127 } 1128 // AND X, 0 -> 0, not "rlwinm 32". 1129 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) { 1130 ReplaceUses(SDValue(N, 0), N->getOperand(1)); 1131 return NULL; 1132 } 1133 // ISD::OR doesn't get all the bitfield insertion fun. 1134 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert 1135 if (isInt32Immediate(N->getOperand(1), Imm) && 1136 N->getOperand(0).getOpcode() == ISD::OR && 1137 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) { 1138 unsigned MB, ME; 1139 Imm = ~(Imm^Imm2); 1140 if (isRunOfOnes(Imm, MB, ME)) { 1141 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1142 N->getOperand(0).getOperand(1), 1143 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) }; 1144 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); 1145 } 1146 } 1147 1148 // Other cases are autogenerated. 1149 break; 1150 } 1151 case ISD::OR: 1152 if (N->getValueType(0) == MVT::i32) 1153 if (SDNode I = SelectBitfieldInsert(N)) 1154* return I; 1155 1156 // Other cases are autogenerated. 1157 break; 1158 case ISD::SHL: { 1159 unsigned Imm, SH, MB, ME; 1160 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && 1161 isRotateAndMask(N, Imm, true, SH, MB, ME)) { 1162 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1163 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1164 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1165 } 1166 1167 // Other cases are autogenerated. 1168 break; 1169 } 1170 case ISD::SRL: { 1171 unsigned Imm, SH, MB, ME; 1172 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && 1173 isRotateAndMask(N, Imm, true, SH, MB, ME)) { 1174 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1175 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1176 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1177 } 1178 1179 // Other cases are autogenerated. 1180 break; 1181 } 1182 case ISD::SELECT_CC: { 1183 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 1184 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy(); 1185 bool isPPC64 = (PtrVT == MVT::i64); 1186 1187 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc 1188 if (!isPPC64) 1189 if (ConstantSDNode N1C = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1190* if (ConstantSDNode N2C = dyn_cast<ConstantSDNode>(N->getOperand(2))) 1191* if (ConstantSDNode N3C = dyn_cast<ConstantSDNode>(N->getOperand(3))) 1192* if (N1C->isNullValue() && N3C->isNullValue() && 1193 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && 1194 // FIXME: Implement this optzn for PPC64. 1195 N->getValueType(0) == MVT::i32) { 1196 SDNode Tmp = 1197* CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 1198 N->getOperand(0), getI32Imm(~0U)); 1199 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, 1200 SDValue(Tmp, 0), N->getOperand(0), 1201 SDValue(Tmp, 1)); 1202 } 1203 1204 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); 1205 unsigned BROpc = getPredicateForSetCC(CC); 1206 1207 unsigned SelectCCOp; 1208 if (N->getValueType(0) == MVT::i32) 1209 SelectCCOp = PPC::SELECT_CC_I4; 1210 else if (N->getValueType(0) == MVT::i64) 1211 SelectCCOp = PPC::SELECT_CC_I8; 1212 else if (N->getValueType(0) == MVT::f32) 1213 SelectCCOp = PPC::SELECT_CC_F4; 1214 else if (N->getValueType(0) == MVT::f64) 1215 SelectCCOp = PPC::SELECT_CC_F8; 1216 else 1217 SelectCCOp = PPC::SELECT_CC_VRRC; 1218 1219 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3), 1220 getI32Imm(BROpc) }; 1221 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4); 1222 } 1223 case PPCISD::BDNZ: 1224 case PPCISD::BDZ: { 1225 bool IsPPC64 = PPCSubTarget.isPPC64(); 1226 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) }; 1227 return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ? 1228 (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : 1229 (IsPPC64 ? PPC::BDZ8 : PPC::BDZ), 1230 MVT::Other, Ops, 2); 1231 } 1232 case PPCISD::COND_BRANCH: { 1233 // Op #0 is the Chain. 1234 // Op #1 is the PPC::PRED_* number. 1235 // Op #2 is the CR# 1236 // Op #3 is the Dest MBB 1237 // Op #4 is the Flag. 1238 // Prevent PPC::PRED_* from being selected into LI. 1239 SDValue Pred = 1240 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()); 1241 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3), 1242 N->getOperand(0), N->getOperand(4) }; 1243 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5); 1244 } 1245 case ISD::BR_CC: { 1246 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 1247 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); 1248 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, 1249 N->getOperand(4), N->getOperand(0) }; 1250 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4); 1251 } 1252 case ISD::BRIND: { 1253 // FIXME: Should custom lower this. 1254 SDValue Chain = N->getOperand(0); 1255 SDValue Target = N->getOperand(1); 1256 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; 1257 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8; 1258 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target, 1259 Chain), 0); 1260 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain); 1261 } 1262 case PPCISD::TOC_ENTRY: { 1263 assert (PPCSubTarget.isPPC64() && "Only supported for 64-bit ABI"); 1264 1265 // For medium and large code model, we generate two instructions as 1266 // described below. Otherwise we allow SelectCodeCommon to handle this, 1267 // selecting one of LDtoc, LDtocJTI, and LDtocCPT. 1268 CodeModel::Model CModel = TM.getCodeModel(); 1269 if (CModel != CodeModel::Medium && CModel != CodeModel::Large) 1270 break; 1271 1272 // The first source operand is a TargetGlobalAddress or a 1273 // TargetJumpTable. If it is an externally defined symbol, a symbol 1274 // with common linkage, a function address, or a jump table address, 1275 // or if we are generating code for large code model, we generate: 1276 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>)) 1277 // Otherwise we generate: 1278 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>) 1279 SDValue GA = N->getOperand(0); 1280 SDValue TOCbase = N->getOperand(1); 1281 SDNode Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64, 1282* TOCbase, GA); 1283 1284 if (isa<JumpTableSDNode>(GA) \|\| CModel == CodeModel::Large) 1285 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA, 1286 SDValue(Tmp, 0)); 1287 1288 if (GlobalAddressSDNode G = dyn_cast<GlobalAddressSDNode>(GA)) { 1289* const GlobalValue GValue = G->getGlobal(); 1290* const GlobalAlias GAlias = dyn_cast<GlobalAlias>(GValue); 1291* const GlobalValue RealGValue = GAlias ? 1292* GAlias->resolveAliasedGlobal(false) : GValue; 1293 const GlobalVariable GVar = dyn_cast<GlobalVariable>(RealGValue); 1294* assert((GVar \|\| isa<Function>(RealGValue)) && 1295 "Unexpected global value subclass!"); 1296 1297 // An external variable is one without an initializer. For these, 1298 // for variables with common linkage, and for Functions, generate 1299 // the LDtocL form. 1300 if (!GVar \|\| !GVar->hasInitializer() \|\| RealGValue->hasCommonLinkage() \|\| 1301 RealGValue->hasAvailableExternallyLinkage()) 1302 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA, 1303 SDValue(Tmp, 0)); 1304 } 1305 1306 return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64, 1307 SDValue(Tmp, 0), GA); 1308 } 1309 case PPCISD::VADD_SPLAT: { 1310 // This expands into one of three sequences, depending on whether 1311 // the first operand is odd or even, positive or negative. 1312 assert(isa<ConstantSDNode>(N->getOperand(0)) && 1313 isa<ConstantSDNode>(N->getOperand(1)) && 1314 "Invalid operand on VADD_SPLAT!"); 1315 1316 int Elt = N->getConstantOperandVal(0); 1317 int EltSize = N->getConstantOperandVal(1); 1318 unsigned Opc1, Opc2, Opc3; 1319 EVT VT; 1320 1321 if (EltSize == 1) { 1322 Opc1 = PPC::VSPLTISB; 1323 Opc2 = PPC::VADDUBM; 1324 Opc3 = PPC::VSUBUBM; 1325 VT = MVT::v16i8; 1326 } else if (EltSize == 2) { 1327 Opc1 = PPC::VSPLTISH; 1328 Opc2 = PPC::VADDUHM; 1329 Opc3 = PPC::VSUBUHM; 1330 VT = MVT::v8i16; 1331 } else { 1332 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!"); 1333 Opc1 = PPC::VSPLTISW; 1334 Opc2 = PPC::VADDUWM; 1335 Opc3 = PPC::VSUBUWM; 1336 VT = MVT::v4i32; 1337 } 1338 1339 if ((Elt & 1) == 0) { 1340 // Elt is even, in the range [-32,-18] + [16,30]. 1341 // 1342 // Convert: VADD_SPLAT elt, size 1343 // Into: tmp = VSPLTIS[BHW] elt 1344 // VADDU[BHW]M tmp, tmp 1345 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4 1346 SDValue EltVal = getI32Imm(Elt >> 1); 1347 SDNode Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1348* SDValue TmpVal = SDValue(Tmp, 0); 1349 return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal); 1350 1351 } else if (Elt > 0) { 1352 // Elt is odd and positive, in the range [17,31]. 1353 // 1354 // Convert: VADD_SPLAT elt, size 1355 // Into: tmp1 = VSPLTIS[BHW] elt-16 1356 // tmp2 = VSPLTIS[BHW] -16 1357 // VSUBU[BHW]M tmp1, tmp2 1358 SDValue EltVal = getI32Imm(Elt - 16); 1359 SDNode Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1360* EltVal = getI32Imm(-16); 1361 SDNode Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1362* return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0), 1363 SDValue(Tmp2, 0)); 1364 1365 } else { 1366 // Elt is odd and negative, in the range [-31,-17]. 1367 // 1368 // Convert: VADD_SPLAT elt, size 1369 // Into: tmp1 = VSPLTIS[BHW] elt+16 1370 // tmp2 = VSPLTIS[BHW] -16 1371 // VADDU[BHW]M tmp1, tmp2 1372 SDValue EltVal = getI32Imm(Elt + 16); 1373 SDNode Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1374* EltVal = getI32Imm(-16); 1375 SDNode Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1376* return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0), 1377 SDValue(Tmp2, 0)); 1378 } 1379 } 1380 } 1381 1382 return SelectCode(N); 1383} 1384 1385/// PostProcessISelDAG - Perform some late peephole optimizations 1386/// on the DAG representation. 1387void PPCDAGToDAGISel::PostprocessISelDAG() { 1388 1389 // Skip peepholes at -O0. 1390 if (TM.getOptLevel() == CodeGenOpt::None) 1391 return; 1392 1393 // These optimizations are currently supported only for 64-bit SVR4. 1394 if (PPCSubTarget.isDarwin() \|\| !PPCSubTarget.isPPC64()) 1395 return; 1396 1397 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode()); 1398 ++Position; 1399 1400 while (Position != CurDAG->allnodes_begin()) { 1401 SDNode N = --Position; 1402* // Skip dead nodes and any non-machine opcodes. 1403 if (N->use_empty() \|\| !N->isMachineOpcode()) 1404 continue; 1405 1406 unsigned FirstOp; 1407 unsigned StorageOpcode = N->getMachineOpcode(); 1408 1409 switch (StorageOpcode) { 1410 default: continue; 1411 1412 case PPC::LBZ: 1413 case PPC::LBZ8: 1414 case PPC::LD: 1415 case PPC::LFD: 1416 case PPC::LFS: 1417 case PPC::LHA: 1418 case PPC::LHA8: 1419 case PPC::LHZ: 1420 case PPC::LHZ8: 1421 case PPC::LWA: 1422 case PPC::LWZ: 1423 case PPC::LWZ8: 1424 FirstOp = 0; 1425 break; 1426 1427 case PPC::STB: 1428 case PPC::STB8: 1429 case PPC::STD: 1430 case PPC::STFD: 1431 case PPC::STFS: 1432 case PPC::STH: 1433 case PPC::STH8: 1434 case PPC::STW: 1435 case PPC::STW8: 1436 FirstOp = 1; 1437 break; 1438 } 1439 1440 // If this is a load or store with a zero offset, we may be able to 1441 // fold an add-immediate into the memory operation. 1442 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) \|\| 1443 N->getConstantOperandVal(FirstOp) != 0) 1444 continue; 1445 1446 SDValue Base = N->getOperand(FirstOp + 1); 1447 if (!Base.isMachineOpcode()) 1448 continue; 1449 1450 unsigned Flags = 0; 1451 bool ReplaceFlags = true; 1452 1453 // When the feeding operation is an add-immediate of some sort, 1454 // determine whether we need to add relocation information to the 1455 // target flags on the immediate operand when we fold it into the 1456 // load instruction. 1457 // 1458 // For something like ADDItocL, the relocation information is 1459 // inferred from the opcode; when we process it in the AsmPrinter, 1460 // we add the necessary relocation there. A load, though, can receive 1461 // relocation from various flavors of ADDIxxx, so we need to carry 1462 // the relocation information in the target flags. 1463 switch (Base.getMachineOpcode()) { 1464 default: continue; 1465 1466 case PPC::ADDI8: 1467 case PPC::ADDI: 1468 // In some cases (such as TLS) the relocation information 1469 // is already in place on the operand, so copying the operand 1470 // is sufficient. 1471 ReplaceFlags = false; 1472 // For these cases, the immediate may not be divisible by 4, in 1473 // which case the fold is illegal for DS-form instructions. (The 1474 // other cases provide aligned addresses and are always safe.) 1475 if ((StorageOpcode == PPC::LWA \|\| 1476 StorageOpcode == PPC::LD \|\| 1477 StorageOpcode == PPC::STD) && 1478 (!isa<ConstantSDNode>(Base.getOperand(1)) \|\| 1479 Base.getConstantOperandVal(1) % 4 != 0)) 1480 continue; 1481 break; 1482 case PPC::ADDIdtprelL: 1483 Flags = PPCII::MO_DTPREL_LO; 1484 break; 1485 case PPC::ADDItlsldL: 1486 Flags = PPCII::MO_TLSLD_LO; 1487 break; 1488 case PPC::ADDItocL: 1489 Flags = PPCII::MO_TOC_LO; 1490 break; 1491 } 1492 1493 // We found an opportunity. Reverse the operands from the add 1494 // immediate and substitute them into the load or store. If 1495 // needed, update the target flags for the immediate operand to 1496 // reflect the necessary relocation information. 1497 DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: "); 1498 DEBUG(Base->dump(CurDAG)); 1499 DEBUG(dbgs() << "\nN: "); 1500 DEBUG(N->dump(CurDAG)); 1501 DEBUG(dbgs() << "\n"); 1502 1503 SDValue ImmOpnd = Base.getOperand(1); 1504 1505 // If the relocation information isn't already present on the 1506 // immediate operand, add it now. 1507 if (ReplaceFlags) { 1508 if (GlobalAddressSDNode GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) { 1509* SDLoc dl(GA); 1510 const GlobalValue GV = GA->getGlobal(); 1511* // We can't perform this optimization for data whose alignment 1512 // is insufficient for the instruction encoding. 1513 if (GV->getAlignment() < 4 && 1514 (StorageOpcode == PPC::LD \|\| StorageOpcode == PPC::STD \|\| 1515 StorageOpcode == PPC::LWA)) { 1516 DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n"); 1517 continue; 1518 } 1519 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags); 1520 } else if (ConstantPoolSDNode CP = 1521* dyn_cast<ConstantPoolSDNode>(ImmOpnd)) { 1522 const Constant C = CP->getConstVal(); 1523* ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64, 1524 CP->getAlignment(), 1525 0, Flags); 1526 } 1527 } 1528 1529 if (FirstOp == 1) // Store 1530 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd, 1531 Base.getOperand(0), N->getOperand(3)); 1532 else // Load 1533 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0), 1534 N->getOperand(2)); 1535 1536 // The add-immediate may now be dead, in which case remove it. 1537 if (Base.getNode()->use_empty()) 1538 CurDAG->RemoveDeadNode(Base.getNode()); 1539 } 1540} 1541 1542 1543/// createPPCISelDag - This pass converts a legalized DAG into a 1544/// PowerPC-specific DAG, ready for instruction scheduling. 1545/// 1546FunctionPass llvm::createPPCISelDag(PPCTargetMachine &TM) { 1547* return new PPCDAGToDAGISel(TM); 1548} 1549 1550static void initializePassOnce(PassRegistry &Registry) { 1551 const char Name = "PowerPC DAG->DAG Pattern Instruction Selection"; 1552* PassInfo PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID, 0, 1553* false, false); 1554 Registry.registerPass(PI, true); 1555} 1556* 1557void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) { 1558 CALL_ONCE_INITIALIZATION(initializePassOnce); 1559} 1560	269 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8)); 270 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg); 271 } 272 } 273 return CurDAG->getRegister(GlobalBaseReg, 274 PPCLowering.getPointerTy()).getNode(); 275} 276 277/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 278/// or 64-bit immediate, and if the value can be accurately represented as a 279/// sign extension from a 16-bit value. If so, this returns true and the 280/// immediate. 281static bool isIntS16Immediate(SDNode N, short &Imm) { 282* if (N->getOpcode() != ISD::Constant) 283 return false; 284 285 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 286 if (N->getValueType(0) == MVT::i32) 287 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 288 else 289 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 290} 291 292static bool isIntS16Immediate(SDValue Op, short &Imm) { 293 return isIntS16Immediate(Op.getNode(), Imm); 294} 295 296 297/// isInt32Immediate - This method tests to see if the node is a 32-bit constant 298/// operand. If so Imm will receive the 32-bit value. 299static bool isInt32Immediate(SDNode N, unsigned &Imm) { 300* if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 301 Imm = cast<ConstantSDNode>(N)->getZExtValue(); 302 return true; 303 } 304 return false; 305} 306 307/// isInt64Immediate - This method tests to see if the node is a 64-bit constant 308/// operand. If so Imm will receive the 64-bit value. 309static bool isInt64Immediate(SDNode N, uint64_t &Imm) { 310* if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { 311 Imm = cast<ConstantSDNode>(N)->getZExtValue(); 312 return true; 313 } 314 return false; 315} 316 317// isInt32Immediate - This method tests to see if a constant operand. 318// If so Imm will receive the 32 bit value. 319static bool isInt32Immediate(SDValue N, unsigned &Imm) { 320 return isInt32Immediate(N.getNode(), Imm); 321} 322 323 324// isOpcWithIntImmediate - This method tests to see if the node is a specific 325// opcode and that it has a immediate integer right operand. 326// If so Imm will receive the 32 bit value. 327static bool isOpcWithIntImmediate(SDNode N, unsigned Opc, unsigned& Imm) { 328* return N->getOpcode() == Opc 329 && isInt32Immediate(N->getOperand(1).getNode(), Imm); 330} 331 332bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { 333 if (!Val) 334 return false; 335 336 if (isShiftedMask_32(Val)) { 337 // look for the first non-zero bit 338 MB = countLeadingZeros(Val); 339 // look for the first zero bit after the run of ones 340 ME = countLeadingZeros((Val - 1) ^ Val); 341 return true; 342 } else { 343 Val = ~Val; // invert mask 344 if (isShiftedMask_32(Val)) { 345 // effectively look for the first zero bit 346 ME = countLeadingZeros(Val) - 1; 347 // effectively look for the first one bit after the run of zeros 348 MB = countLeadingZeros((Val - 1) ^ Val) + 1; 349 return true; 350 } 351 } 352 // no run present 353 return false; 354} 355 356bool PPCDAGToDAGISel::isRotateAndMask(SDNode N, unsigned Mask, 357* bool isShiftMask, unsigned &SH, 358 unsigned &MB, unsigned &ME) { 359 // Don't even go down this path for i64, since different logic will be 360 // necessary for rldicl/rldicr/rldimi. 361 if (N->getValueType(0) != MVT::i32) 362 return false; 363 364 unsigned Shift = 32; 365 unsigned Indeterminant = ~0; // bit mask marking indeterminant results 366 unsigned Opcode = N->getOpcode(); 367 if (N->getNumOperands() != 2 \|\| 368 !isInt32Immediate(N->getOperand(1).getNode(), Shift) \|\| (Shift > 31)) 369 return false; 370 371 if (Opcode == ISD::SHL) { 372 // apply shift left to mask if it comes first 373 if (isShiftMask) Mask = Mask << Shift; 374 // determine which bits are made indeterminant by shift 375 Indeterminant = ~(0xFFFFFFFFu << Shift); 376 } else if (Opcode == ISD::SRL) { 377 // apply shift right to mask if it comes first 378 if (isShiftMask) Mask = Mask >> Shift; 379 // determine which bits are made indeterminant by shift 380 Indeterminant = ~(0xFFFFFFFFu >> Shift); 381 // adjust for the left rotate 382 Shift = 32 - Shift; 383 } else if (Opcode == ISD::ROTL) { 384 Indeterminant = 0; 385 } else { 386 return false; 387 } 388 389 // if the mask doesn't intersect any Indeterminant bits 390 if (Mask && !(Mask & Indeterminant)) { 391 SH = Shift & 31; 392 // make sure the mask is still a mask (wrap arounds may not be) 393 return isRunOfOnes(Mask, MB, ME); 394 } 395 return false; 396} 397 398/// SelectBitfieldInsert - turn an or of two masked values into 399/// the rotate left word immediate then mask insert (rlwimi) instruction. 400SDNode PPCDAGToDAGISel::SelectBitfieldInsert(SDNode N) { 401 SDValue Op0 = N->getOperand(0); 402 SDValue Op1 = N->getOperand(1); 403 SDLoc dl(N); 404 405 APInt LKZ, LKO, RKZ, RKO; 406 CurDAG->ComputeMaskedBits(Op0, LKZ, LKO); 407 CurDAG->ComputeMaskedBits(Op1, RKZ, RKO); 408 409 unsigned TargetMask = LKZ.getZExtValue(); 410 unsigned InsertMask = RKZ.getZExtValue(); 411 412 if ((TargetMask \| InsertMask) == 0xFFFFFFFF) { 413 unsigned Op0Opc = Op0.getOpcode(); 414 unsigned Op1Opc = Op1.getOpcode(); 415 unsigned Value, SH = 0; 416 TargetMask = ~TargetMask; 417 InsertMask = ~InsertMask; 418 419 // If the LHS has a foldable shift and the RHS does not, then swap it to the 420 // RHS so that we can fold the shift into the insert. 421 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) { 422 if (Op0.getOperand(0).getOpcode() == ISD::SHL \|\| 423 Op0.getOperand(0).getOpcode() == ISD::SRL) { 424 if (Op1.getOperand(0).getOpcode() != ISD::SHL && 425 Op1.getOperand(0).getOpcode() != ISD::SRL) { 426 std::swap(Op0, Op1); 427 std::swap(Op0Opc, Op1Opc); 428 std::swap(TargetMask, InsertMask); 429 } 430 } 431 } else if (Op0Opc == ISD::SHL \|\| Op0Opc == ISD::SRL) { 432 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && 433 Op1.getOperand(0).getOpcode() != ISD::SRL) { 434 std::swap(Op0, Op1); 435 std::swap(Op0Opc, Op1Opc); 436 std::swap(TargetMask, InsertMask); 437 } 438 } 439 440 unsigned MB, ME; 441 if (isRunOfOnes(InsertMask, MB, ME)) { 442 SDValue Tmp1, Tmp2; 443 444 if ((Op1Opc == ISD::SHL \|\| Op1Opc == ISD::SRL) && 445 isInt32Immediate(Op1.getOperand(1), Value)) { 446 Op1 = Op1.getOperand(0); 447 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; 448 } 449 if (Op1Opc == ISD::AND) { 450 unsigned SHOpc = Op1.getOperand(0).getOpcode(); 451 if ((SHOpc == ISD::SHL \|\| SHOpc == ISD::SRL) && 452 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) { 453 // Note that Value must be in range here (less than 32) because 454 // otherwise there would not be any bits set in InsertMask. 455 Op1 = Op1.getOperand(0).getOperand(0); 456 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; 457 } 458 } 459 460 SH &= 31; 461 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB), 462 getI32Imm(ME) }; 463 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); 464 } 465 } 466 return 0; 467} 468 469/// SelectCC - Select a comparison of the specified values with the specified 470/// condition code, returning the CR# of the expression. 471SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, 472 ISD::CondCode CC, SDLoc dl) { 473 // Always select the LHS. 474 unsigned Opc; 475 476 if (LHS.getValueType() == MVT::i32) { 477 unsigned Imm; 478 if (CC == ISD::SETEQ \|\| CC == ISD::SETNE) { 479 if (isInt32Immediate(RHS, Imm)) { 480 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 481 if (isUInt<16>(Imm)) 482 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, 483 getI32Imm(Imm & 0xFFFF)), 0); 484 // If this is a 16-bit signed immediate, fold it. 485 if (isInt<16>((int)Imm)) 486 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, 487 getI32Imm(Imm & 0xFFFF)), 0); 488 489 // For non-equality comparisons, the default code would materialize the 490 // constant, then compare against it, like this: 491 // lis r2, 4660 492 // ori r2, r2, 22136 493 // cmpw cr0, r3, r2 494 // Since we are just comparing for equality, we can emit this instead: 495 // xoris r0,r3,0x1234 496 // cmplwi cr0,r0,0x5678 497 // beq cr0,L6 498 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS, 499 getI32Imm(Imm >> 16)), 0); 500 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor, 501 getI32Imm(Imm & 0xFFFF)), 0); 502 } 503 Opc = PPC::CMPLW; 504 } else if (ISD::isUnsignedIntSetCC(CC)) { 505 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm)) 506 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, 507 getI32Imm(Imm & 0xFFFF)), 0); 508 Opc = PPC::CMPLW; 509 } else { 510 short SImm; 511 if (isIntS16Immediate(RHS, SImm)) 512 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, 513 getI32Imm((int)SImm & 0xFFFF)), 514 0); 515 Opc = PPC::CMPW; 516 } 517 } else if (LHS.getValueType() == MVT::i64) { 518 uint64_t Imm; 519 if (CC == ISD::SETEQ \|\| CC == ISD::SETNE) { 520 if (isInt64Immediate(RHS.getNode(), Imm)) { 521 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 522 if (isUInt<16>(Imm)) 523 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, 524 getI32Imm(Imm & 0xFFFF)), 0); 525 // If this is a 16-bit signed immediate, fold it. 526 if (isInt<16>(Imm)) 527 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, 528 getI32Imm(Imm & 0xFFFF)), 0); 529 530 // For non-equality comparisons, the default code would materialize the 531 // constant, then compare against it, like this: 532 // lis r2, 4660 533 // ori r2, r2, 22136 534 // cmpd cr0, r3, r2 535 // Since we are just comparing for equality, we can emit this instead: 536 // xoris r0,r3,0x1234 537 // cmpldi cr0,r0,0x5678 538 // beq cr0,L6 539 if (isUInt<32>(Imm)) { 540 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS, 541 getI64Imm(Imm >> 16)), 0); 542 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor, 543 getI64Imm(Imm & 0xFFFF)), 0); 544 } 545 } 546 Opc = PPC::CMPLD; 547 } else if (ISD::isUnsignedIntSetCC(CC)) { 548 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm)) 549 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, 550 getI64Imm(Imm & 0xFFFF)), 0); 551 Opc = PPC::CMPLD; 552 } else { 553 short SImm; 554 if (isIntS16Immediate(RHS, SImm)) 555 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, 556 getI64Imm(SImm & 0xFFFF)), 557 0); 558 Opc = PPC::CMPD; 559 } 560 } else if (LHS.getValueType() == MVT::f32) { 561 Opc = PPC::FCMPUS; 562 } else { 563 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!"); 564 Opc = PPC::FCMPUD; 565 } 566 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0); 567} 568 569static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { 570 switch (CC) { 571 case ISD::SETUEQ: 572 case ISD::SETONE: 573 case ISD::SETOLE: 574 case ISD::SETOGE: 575 llvm_unreachable("Should be lowered by legalize!"); 576 default: llvm_unreachable("Unknown condition!"); 577 case ISD::SETOEQ: 578 case ISD::SETEQ: return PPC::PRED_EQ; 579 case ISD::SETUNE: 580 case ISD::SETNE: return PPC::PRED_NE; 581 case ISD::SETOLT: 582 case ISD::SETLT: return PPC::PRED_LT; 583 case ISD::SETULE: 584 case ISD::SETLE: return PPC::PRED_LE; 585 case ISD::SETOGT: 586 case ISD::SETGT: return PPC::PRED_GT; 587 case ISD::SETUGE: 588 case ISD::SETGE: return PPC::PRED_GE; 589 case ISD::SETO: return PPC::PRED_NU; 590 case ISD::SETUO: return PPC::PRED_UN; 591 // These two are invalid for floating point. Assume we have int. 592 case ISD::SETULT: return PPC::PRED_LT; 593 case ISD::SETUGT: return PPC::PRED_GT; 594 } 595} 596 597/// getCRIdxForSetCC - Return the index of the condition register field 598/// associated with the SetCC condition, and whether or not the field is 599/// treated as inverted. That is, lt = 0; ge = 0 inverted. 600static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { 601 Invert = false; 602 switch (CC) { 603 default: llvm_unreachable("Unknown condition!"); 604 case ISD::SETOLT: 605 case ISD::SETLT: return 0; // Bit #0 = SETOLT 606 case ISD::SETOGT: 607 case ISD::SETGT: return 1; // Bit #1 = SETOGT 608 case ISD::SETOEQ: 609 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ 610 case ISD::SETUO: return 3; // Bit #3 = SETUO 611 case ISD::SETUGE: 612 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE 613 case ISD::SETULE: 614 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE 615 case ISD::SETUNE: 616 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE 617 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO 618 case ISD::SETUEQ: 619 case ISD::SETOGE: 620 case ISD::SETOLE: 621 case ISD::SETONE: 622 llvm_unreachable("Invalid branch code: should be expanded by legalize"); 623 // These are invalid for floating point. Assume integer. 624 case ISD::SETULT: return 0; 625 case ISD::SETUGT: return 1; 626 } 627} 628 629// getVCmpInst: return the vector compare instruction for the specified 630// vector type and condition code. Since this is for altivec specific code, 631// only support the altivec types (v16i8, v8i16, v4i32, and v4f32). 632static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC) { 633 switch (CC) { 634 case ISD::SETEQ: 635 case ISD::SETUEQ: 636 case ISD::SETNE: 637 case ISD::SETUNE: 638 if (VecVT == MVT::v16i8) 639 return PPC::VCMPEQUB; 640 else if (VecVT == MVT::v8i16) 641 return PPC::VCMPEQUH; 642 else if (VecVT == MVT::v4i32) 643 return PPC::VCMPEQUW; 644 // v4f32 != v4f32 could be translate to unordered not equal 645 else if (VecVT == MVT::v4f32) 646 return PPC::VCMPEQFP; 647 break; 648 case ISD::SETLT: 649 case ISD::SETGT: 650 case ISD::SETLE: 651 case ISD::SETGE: 652 if (VecVT == MVT::v16i8) 653 return PPC::VCMPGTSB; 654 else if (VecVT == MVT::v8i16) 655 return PPC::VCMPGTSH; 656 else if (VecVT == MVT::v4i32) 657 return PPC::VCMPGTSW; 658 else if (VecVT == MVT::v4f32) 659 return PPC::VCMPGTFP; 660 break; 661 case ISD::SETULT: 662 case ISD::SETUGT: 663 case ISD::SETUGE: 664 case ISD::SETULE: 665 if (VecVT == MVT::v16i8) 666 return PPC::VCMPGTUB; 667 else if (VecVT == MVT::v8i16) 668 return PPC::VCMPGTUH; 669 else if (VecVT == MVT::v4i32) 670 return PPC::VCMPGTUW; 671 break; 672 case ISD::SETOEQ: 673 if (VecVT == MVT::v4f32) 674 return PPC::VCMPEQFP; 675 break; 676 case ISD::SETOLT: 677 case ISD::SETOGT: 678 case ISD::SETOLE: 679 if (VecVT == MVT::v4f32) 680 return PPC::VCMPGTFP; 681 break; 682 case ISD::SETOGE: 683 if (VecVT == MVT::v4f32) 684 return PPC::VCMPGEFP; 685 break; 686 default: 687 break; 688 } 689 llvm_unreachable("Invalid integer vector compare condition"); 690} 691 692// getVCmpEQInst: return the equal compare instruction for the specified vector 693// type. Since this is for altivec specific code, only support the altivec 694// types (v16i8, v8i16, v4i32, and v4f32). 695static unsigned int getVCmpEQInst(MVT::SimpleValueType VecVT) { 696 switch (VecVT) { 697 case MVT::v16i8: 698 return PPC::VCMPEQUB; 699 case MVT::v8i16: 700 return PPC::VCMPEQUH; 701 case MVT::v4i32: 702 return PPC::VCMPEQUW; 703 case MVT::v4f32: 704 return PPC::VCMPEQFP; 705 default: 706 llvm_unreachable("Invalid integer vector compare condition"); 707 } 708} 709 710 711SDNode PPCDAGToDAGISel::SelectSETCC(SDNode N) { 712 SDLoc dl(N); 713 unsigned Imm; 714 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 715 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy(); 716 bool isPPC64 = (PtrVT == MVT::i64); 717 718 if (isInt32Immediate(N->getOperand(1), Imm)) { 719 // We can codegen setcc op, imm very efficiently compared to a brcond. 720 // Check for those cases here. 721 // setcc op, 0 722 if (Imm == 0) { 723 SDValue Op = N->getOperand(0); 724 switch (CC) { 725 default: break; 726 case ISD::SETEQ: { 727 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); 728 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; 729 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 730 } 731 case ISD::SETNE: { 732 if (isPPC64) break; 733 SDValue AD = 734 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 735 Op, getI32Imm(~0U)), 0); 736 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, 737 AD.getValue(1)); 738 } 739 case ISD::SETLT: { 740 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 741 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 742 } 743 case ISD::SETGT: { 744 SDValue T = 745 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0); 746 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0); 747 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 748 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 749 } 750 } 751 } else if (Imm == ~0U) { // setcc op, -1 752 SDValue Op = N->getOperand(0); 753 switch (CC) { 754 default: break; 755 case ISD::SETEQ: 756 if (isPPC64) break; 757 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 758 Op, getI32Imm(1)), 0); 759 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 760 SDValue(CurDAG->getMachineNode(PPC::LI, dl, 761 MVT::i32, 762 getI32Imm(0)), 0), 763 Op.getValue(1)); 764 case ISD::SETNE: { 765 if (isPPC64) break; 766 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); 767 SDNode AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 768* Op, getI32Imm(~0U)); 769 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), 770 Op, SDValue(AD, 1)); 771 } 772 case ISD::SETLT: { 773 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op, 774 getI32Imm(1)), 0); 775 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD, 776 Op), 0); 777 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 778 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 779 } 780 case ISD::SETGT: { 781 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 782 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 783 0); 784 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, 785 getI32Imm(1)); 786 } 787 } 788 } 789 } 790 791 SDValue LHS = N->getOperand(0); 792 SDValue RHS = N->getOperand(1); 793 794 // Altivec Vector compare instructions do not set any CR register by default and 795 // vector compare operations return the same type as the operands. 796 if (LHS.getValueType().isVector()) { 797 EVT VecVT = LHS.getValueType(); 798 MVT::SimpleValueType VT = VecVT.getSimpleVT().SimpleTy; 799 unsigned int VCmpInst = getVCmpInst(VT, CC); 800 801 switch (CC) { 802 case ISD::SETEQ: 803 case ISD::SETOEQ: 804 case ISD::SETUEQ: 805 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); 806 case ISD::SETNE: 807 case ISD::SETONE: 808 case ISD::SETUNE: { 809 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0); 810 return CurDAG->SelectNodeTo(N, PPC::VNOR, VecVT, VCmp, VCmp); 811 } 812 case ISD::SETLT: 813 case ISD::SETOLT: 814 case ISD::SETULT: 815 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, RHS, LHS); 816 case ISD::SETGT: 817 case ISD::SETOGT: 818 case ISD::SETUGT: 819 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); 820 case ISD::SETGE: 821 case ISD::SETOGE: 822 case ISD::SETUGE: { 823 // Small optimization: Altivec provides a 'Vector Compare Greater Than 824 // or Equal To' instruction (vcmpgefp), so in this case there is no 825 // need for extra logic for the equal compare. 826 if (VecVT.getSimpleVT().isFloatingPoint()) { 827 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); 828 } else { 829 SDValue VCmpGT(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0); 830 unsigned int VCmpEQInst = getVCmpEQInst(VT); 831 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0); 832 return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpGT, VCmpEQ); 833 } 834 } 835 case ISD::SETLE: 836 case ISD::SETOLE: 837 case ISD::SETULE: { 838 SDValue VCmpLE(CurDAG->getMachineNode(VCmpInst, dl, VecVT, RHS, LHS), 0); 839 unsigned int VCmpEQInst = getVCmpEQInst(VT); 840 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0); 841 return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpLE, VCmpEQ); 842 } 843 default: 844 llvm_unreachable("Invalid vector compare type: should be expanded by legalize"); 845 } 846 } 847 848 bool Inv; 849 unsigned Idx = getCRIdxForSetCC(CC, Inv); 850 SDValue CCReg = SelectCC(LHS, RHS, CC, dl); 851 SDValue IntCR; 852 853 // Force the ccreg into CR7. 854 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); 855 856 SDValue InFlag(0, 0); // Null incoming flag value. 857 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg, 858 InFlag).getValue(1); 859 860 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, 861 CCReg), 0); 862 863 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), 864 getI32Imm(31), getI32Imm(31) }; 865 if (!Inv) 866 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 867 868 // Get the specified bit. 869 SDValue Tmp = 870 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0); 871 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); 872} 873 874 875// Select - Convert the specified operand from a target-independent to a 876// target-specific node if it hasn't already been changed. 877SDNode PPCDAGToDAGISel::Select(SDNode N) { 878 SDLoc dl(N); 879 if (N->isMachineOpcode()) { 880 N->setNodeId(-1); 881 return NULL; // Already selected. 882 } 883 884 switch (N->getOpcode()) { 885 default: break; 886 887 case ISD::Constant: { 888 if (N->getValueType(0) == MVT::i64) { 889 // Get 64 bit value. 890 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue(); 891 // Assume no remaining bits. 892 unsigned Remainder = 0; 893 // Assume no shift required. 894 unsigned Shift = 0; 895 896 // If it can't be represented as a 32 bit value. 897 if (!isInt<32>(Imm)) { 898 Shift = countTrailingZeros<uint64_t>(Imm); 899 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift; 900 901 // If the shifted value fits 32 bits. 902 if (isInt<32>(ImmSh)) { 903 // Go with the shifted value. 904 Imm = ImmSh; 905 } else { 906 // Still stuck with a 64 bit value. 907 Remainder = Imm; 908 Shift = 32; 909 Imm >>= 32; 910 } 911 } 912 913 // Intermediate operand. 914 SDNode Result; 915* 916 // Handle first 32 bits. 917 unsigned Lo = Imm & 0xFFFF; 918 unsigned Hi = (Imm >> 16) & 0xFFFF; 919 920 // Simple value. 921 if (isInt<16>(Imm)) { 922 // Just the Lo bits. 923 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo)); 924 } else if (Lo) { 925 // Handle the Hi bits. 926 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8; 927 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi)); 928 // And Lo bits. 929 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, 930 SDValue(Result, 0), getI32Imm(Lo)); 931 } else { 932 // Just the Hi bits. 933 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi)); 934 } 935 936 // If no shift, we're done. 937 if (!Shift) return Result; 938 939 // Shift for next step if the upper 32-bits were not zero. 940 if (Imm) { 941 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, 942 SDValue(Result, 0), 943 getI32Imm(Shift), 944 getI32Imm(63 - Shift)); 945 } 946 947 // Add in the last bits as required. 948 if ((Hi = (Remainder >> 16) & 0xFFFF)) { 949 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64, 950 SDValue(Result, 0), getI32Imm(Hi)); 951 } 952 if ((Lo = Remainder & 0xFFFF)) { 953 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, 954 SDValue(Result, 0), getI32Imm(Lo)); 955 } 956 957 return Result; 958 } 959 break; 960 } 961 962 case ISD::SETCC: 963 return SelectSETCC(N); 964 case PPCISD::GlobalBaseReg: 965 return getGlobalBaseReg(); 966 967 case ISD::FrameIndex: { 968 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 969 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0)); 970 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8; 971 if (N->hasOneUse()) 972 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI, 973 getSmallIPtrImm(0)); 974 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI, 975 getSmallIPtrImm(0)); 976 } 977 978 case PPCISD::MFOCRF: { 979 SDValue InFlag = N->getOperand(1); 980 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, 981 N->getOperand(0), InFlag); 982 } 983 984 case ISD::SDIV: { 985 // FIXME: since this depends on the setting of the carry flag from the srawi 986 // we should really be making notes about that for the scheduler. 987 // FIXME: It sure would be nice if we could cheaply recognize the 988 // srl/add/sra pattern the dag combiner will generate for this as 989 // sra/addze rather than having to handle sdiv ourselves. oh well. 990 unsigned Imm; 991 if (isInt32Immediate(N->getOperand(1), Imm)) { 992 SDValue N0 = N->getOperand(0); 993 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { 994 SDNode Op = 995* CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue, 996 N0, getI32Imm(Log2_32(Imm))); 997 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 998 SDValue(Op, 0), SDValue(Op, 1)); 999 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { 1000 SDNode Op = 1001* CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue, 1002 N0, getI32Imm(Log2_32(-Imm))); 1003 SDValue PT = 1004 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32, 1005 SDValue(Op, 0), SDValue(Op, 1)), 1006 0); 1007 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); 1008 } 1009 } 1010 1011 // Other cases are autogenerated. 1012 break; 1013 } 1014 1015 case ISD::LOAD: { 1016 // Handle preincrement loads. 1017 LoadSDNode LD = cast<LoadSDNode>(N); 1018* EVT LoadedVT = LD->getMemoryVT(); 1019 1020 // Normal loads are handled by code generated from the .td file. 1021 if (LD->getAddressingMode() != ISD::PRE_INC) 1022 break; 1023 1024 SDValue Offset = LD->getOffset(); 1025 if (Offset.getOpcode() == ISD::TargetConstant \|\| 1026 Offset.getOpcode() == ISD::TargetGlobalAddress) { 1027 1028 unsigned Opcode; 1029 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; 1030 if (LD->getValueType(0) != MVT::i64) { 1031 // Handle PPC32 integer and normal FP loads. 1032 assert((!isSExt \|\| LoadedVT == MVT::i16) && "Invalid sext update load"); 1033 switch (LoadedVT.getSimpleVT().SimpleTy) { 1034 default: llvm_unreachable("Invalid PPC load type!"); 1035 case MVT::f64: Opcode = PPC::LFDU; break; 1036 case MVT::f32: Opcode = PPC::LFSU; break; 1037 case MVT::i32: Opcode = PPC::LWZU; break; 1038 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; 1039 case MVT::i1: 1040 case MVT::i8: Opcode = PPC::LBZU; break; 1041 } 1042 } else { 1043 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); 1044 assert((!isSExt \|\| LoadedVT == MVT::i16) && "Invalid sext update load"); 1045 switch (LoadedVT.getSimpleVT().SimpleTy) { 1046 default: llvm_unreachable("Invalid PPC load type!"); 1047 case MVT::i64: Opcode = PPC::LDU; break; 1048 case MVT::i32: Opcode = PPC::LWZU8; break; 1049 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; 1050 case MVT::i1: 1051 case MVT::i8: Opcode = PPC::LBZU8; break; 1052 } 1053 } 1054 1055 SDValue Chain = LD->getChain(); 1056 SDValue Base = LD->getBasePtr(); 1057 SDValue Ops[] = { Offset, Base, Chain }; 1058 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), 1059 PPCLowering.getPointerTy(), 1060 MVT::Other, Ops); 1061 } else { 1062 unsigned Opcode; 1063 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; 1064 if (LD->getValueType(0) != MVT::i64) { 1065 // Handle PPC32 integer and normal FP loads. 1066 assert((!isSExt \|\| LoadedVT == MVT::i16) && "Invalid sext update load"); 1067 switch (LoadedVT.getSimpleVT().SimpleTy) { 1068 default: llvm_unreachable("Invalid PPC load type!"); 1069 case MVT::f64: Opcode = PPC::LFDUX; break; 1070 case MVT::f32: Opcode = PPC::LFSUX; break; 1071 case MVT::i32: Opcode = PPC::LWZUX; break; 1072 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; 1073 case MVT::i1: 1074 case MVT::i8: Opcode = PPC::LBZUX; break; 1075 } 1076 } else { 1077 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); 1078 assert((!isSExt \|\| LoadedVT == MVT::i16 \|\| LoadedVT == MVT::i32) && 1079 "Invalid sext update load"); 1080 switch (LoadedVT.getSimpleVT().SimpleTy) { 1081 default: llvm_unreachable("Invalid PPC load type!"); 1082 case MVT::i64: Opcode = PPC::LDUX; break; 1083 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break; 1084 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break; 1085 case MVT::i1: 1086 case MVT::i8: Opcode = PPC::LBZUX8; break; 1087 } 1088 } 1089 1090 SDValue Chain = LD->getChain(); 1091 SDValue Base = LD->getBasePtr(); 1092 SDValue Ops[] = { Base, Offset, Chain }; 1093 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), 1094 PPCLowering.getPointerTy(), 1095 MVT::Other, Ops); 1096 } 1097 } 1098 1099 case ISD::AND: { 1100 unsigned Imm, Imm2, SH, MB, ME; 1101 uint64_t Imm64; 1102 1103 // If this is an and of a value rotated between 0 and 31 bits and then and'd 1104 // with a mask, emit rlwinm 1105 if (isInt32Immediate(N->getOperand(1), Imm) && 1106 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) { 1107 SDValue Val = N->getOperand(0).getOperand(0); 1108 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1109 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1110 } 1111 // If this is just a masked value where the input is not handled above, and 1112 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm 1113 if (isInt32Immediate(N->getOperand(1), Imm) && 1114 isRunOfOnes(Imm, MB, ME) && 1115 N->getOperand(0).getOpcode() != ISD::ROTL) { 1116 SDValue Val = N->getOperand(0); 1117 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) }; 1118 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1119 } 1120 // If this is a 64-bit zero-extension mask, emit rldicl. 1121 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) && 1122 isMask_64(Imm64)) { 1123 SDValue Val = N->getOperand(0); 1124 MB = 64 - CountTrailingOnes_64(Imm64); 1125 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB) }; 1126 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops, 3); 1127 } 1128 // AND X, 0 -> 0, not "rlwinm 32". 1129 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) { 1130 ReplaceUses(SDValue(N, 0), N->getOperand(1)); 1131 return NULL; 1132 } 1133 // ISD::OR doesn't get all the bitfield insertion fun. 1134 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert 1135 if (isInt32Immediate(N->getOperand(1), Imm) && 1136 N->getOperand(0).getOpcode() == ISD::OR && 1137 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) { 1138 unsigned MB, ME; 1139 Imm = ~(Imm^Imm2); 1140 if (isRunOfOnes(Imm, MB, ME)) { 1141 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1142 N->getOperand(0).getOperand(1), 1143 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) }; 1144 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); 1145 } 1146 } 1147 1148 // Other cases are autogenerated. 1149 break; 1150 } 1151 case ISD::OR: 1152 if (N->getValueType(0) == MVT::i32) 1153 if (SDNode I = SelectBitfieldInsert(N)) 1154* return I; 1155 1156 // Other cases are autogenerated. 1157 break; 1158 case ISD::SHL: { 1159 unsigned Imm, SH, MB, ME; 1160 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && 1161 isRotateAndMask(N, Imm, true, SH, MB, ME)) { 1162 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1163 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1164 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1165 } 1166 1167 // Other cases are autogenerated. 1168 break; 1169 } 1170 case ISD::SRL: { 1171 unsigned Imm, SH, MB, ME; 1172 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && 1173 isRotateAndMask(N, Imm, true, SH, MB, ME)) { 1174 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1175 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1176 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1177 } 1178 1179 // Other cases are autogenerated. 1180 break; 1181 } 1182 case ISD::SELECT_CC: { 1183 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 1184 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy(); 1185 bool isPPC64 = (PtrVT == MVT::i64); 1186 1187 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc 1188 if (!isPPC64) 1189 if (ConstantSDNode N1C = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1190* if (ConstantSDNode N2C = dyn_cast<ConstantSDNode>(N->getOperand(2))) 1191* if (ConstantSDNode N3C = dyn_cast<ConstantSDNode>(N->getOperand(3))) 1192* if (N1C->isNullValue() && N3C->isNullValue() && 1193 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && 1194 // FIXME: Implement this optzn for PPC64. 1195 N->getValueType(0) == MVT::i32) { 1196 SDNode Tmp = 1197* CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 1198 N->getOperand(0), getI32Imm(~0U)); 1199 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, 1200 SDValue(Tmp, 0), N->getOperand(0), 1201 SDValue(Tmp, 1)); 1202 } 1203 1204 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); 1205 unsigned BROpc = getPredicateForSetCC(CC); 1206 1207 unsigned SelectCCOp; 1208 if (N->getValueType(0) == MVT::i32) 1209 SelectCCOp = PPC::SELECT_CC_I4; 1210 else if (N->getValueType(0) == MVT::i64) 1211 SelectCCOp = PPC::SELECT_CC_I8; 1212 else if (N->getValueType(0) == MVT::f32) 1213 SelectCCOp = PPC::SELECT_CC_F4; 1214 else if (N->getValueType(0) == MVT::f64) 1215 SelectCCOp = PPC::SELECT_CC_F8; 1216 else 1217 SelectCCOp = PPC::SELECT_CC_VRRC; 1218 1219 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3), 1220 getI32Imm(BROpc) }; 1221 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4); 1222 } 1223 case PPCISD::BDNZ: 1224 case PPCISD::BDZ: { 1225 bool IsPPC64 = PPCSubTarget.isPPC64(); 1226 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) }; 1227 return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ? 1228 (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : 1229 (IsPPC64 ? PPC::BDZ8 : PPC::BDZ), 1230 MVT::Other, Ops, 2); 1231 } 1232 case PPCISD::COND_BRANCH: { 1233 // Op #0 is the Chain. 1234 // Op #1 is the PPC::PRED_* number. 1235 // Op #2 is the CR# 1236 // Op #3 is the Dest MBB 1237 // Op #4 is the Flag. 1238 // Prevent PPC::PRED_* from being selected into LI. 1239 SDValue Pred = 1240 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()); 1241 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3), 1242 N->getOperand(0), N->getOperand(4) }; 1243 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5); 1244 } 1245 case ISD::BR_CC: { 1246 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 1247 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); 1248 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, 1249 N->getOperand(4), N->getOperand(0) }; 1250 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4); 1251 } 1252 case ISD::BRIND: { 1253 // FIXME: Should custom lower this. 1254 SDValue Chain = N->getOperand(0); 1255 SDValue Target = N->getOperand(1); 1256 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; 1257 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8; 1258 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target, 1259 Chain), 0); 1260 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain); 1261 } 1262 case PPCISD::TOC_ENTRY: { 1263 assert (PPCSubTarget.isPPC64() && "Only supported for 64-bit ABI"); 1264 1265 // For medium and large code model, we generate two instructions as 1266 // described below. Otherwise we allow SelectCodeCommon to handle this, 1267 // selecting one of LDtoc, LDtocJTI, and LDtocCPT. 1268 CodeModel::Model CModel = TM.getCodeModel(); 1269 if (CModel != CodeModel::Medium && CModel != CodeModel::Large) 1270 break; 1271 1272 // The first source operand is a TargetGlobalAddress or a 1273 // TargetJumpTable. If it is an externally defined symbol, a symbol 1274 // with common linkage, a function address, or a jump table address, 1275 // or if we are generating code for large code model, we generate: 1276 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>)) 1277 // Otherwise we generate: 1278 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>) 1279 SDValue GA = N->getOperand(0); 1280 SDValue TOCbase = N->getOperand(1); 1281 SDNode Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64, 1282* TOCbase, GA); 1283 1284 if (isa<JumpTableSDNode>(GA) \|\| CModel == CodeModel::Large) 1285 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA, 1286 SDValue(Tmp, 0)); 1287 1288 if (GlobalAddressSDNode G = dyn_cast<GlobalAddressSDNode>(GA)) { 1289* const GlobalValue GValue = G->getGlobal(); 1290* const GlobalAlias GAlias = dyn_cast<GlobalAlias>(GValue); 1291* const GlobalValue RealGValue = GAlias ? 1292* GAlias->resolveAliasedGlobal(false) : GValue; 1293 const GlobalVariable GVar = dyn_cast<GlobalVariable>(RealGValue); 1294* assert((GVar \|\| isa<Function>(RealGValue)) && 1295 "Unexpected global value subclass!"); 1296 1297 // An external variable is one without an initializer. For these, 1298 // for variables with common linkage, and for Functions, generate 1299 // the LDtocL form. 1300 if (!GVar \|\| !GVar->hasInitializer() \|\| RealGValue->hasCommonLinkage() \|\| 1301 RealGValue->hasAvailableExternallyLinkage()) 1302 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA, 1303 SDValue(Tmp, 0)); 1304 } 1305 1306 return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64, 1307 SDValue(Tmp, 0), GA); 1308 } 1309 case PPCISD::VADD_SPLAT: { 1310 // This expands into one of three sequences, depending on whether 1311 // the first operand is odd or even, positive or negative. 1312 assert(isa<ConstantSDNode>(N->getOperand(0)) && 1313 isa<ConstantSDNode>(N->getOperand(1)) && 1314 "Invalid operand on VADD_SPLAT!"); 1315 1316 int Elt = N->getConstantOperandVal(0); 1317 int EltSize = N->getConstantOperandVal(1); 1318 unsigned Opc1, Opc2, Opc3; 1319 EVT VT; 1320 1321 if (EltSize == 1) { 1322 Opc1 = PPC::VSPLTISB; 1323 Opc2 = PPC::VADDUBM; 1324 Opc3 = PPC::VSUBUBM; 1325 VT = MVT::v16i8; 1326 } else if (EltSize == 2) { 1327 Opc1 = PPC::VSPLTISH; 1328 Opc2 = PPC::VADDUHM; 1329 Opc3 = PPC::VSUBUHM; 1330 VT = MVT::v8i16; 1331 } else { 1332 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!"); 1333 Opc1 = PPC::VSPLTISW; 1334 Opc2 = PPC::VADDUWM; 1335 Opc3 = PPC::VSUBUWM; 1336 VT = MVT::v4i32; 1337 } 1338 1339 if ((Elt & 1) == 0) { 1340 // Elt is even, in the range [-32,-18] + [16,30]. 1341 // 1342 // Convert: VADD_SPLAT elt, size 1343 // Into: tmp = VSPLTIS[BHW] elt 1344 // VADDU[BHW]M tmp, tmp 1345 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4 1346 SDValue EltVal = getI32Imm(Elt >> 1); 1347 SDNode Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1348* SDValue TmpVal = SDValue(Tmp, 0); 1349 return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal); 1350 1351 } else if (Elt > 0) { 1352 // Elt is odd and positive, in the range [17,31]. 1353 // 1354 // Convert: VADD_SPLAT elt, size 1355 // Into: tmp1 = VSPLTIS[BHW] elt-16 1356 // tmp2 = VSPLTIS[BHW] -16 1357 // VSUBU[BHW]M tmp1, tmp2 1358 SDValue EltVal = getI32Imm(Elt - 16); 1359 SDNode Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1360* EltVal = getI32Imm(-16); 1361 SDNode Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1362* return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0), 1363 SDValue(Tmp2, 0)); 1364 1365 } else { 1366 // Elt is odd and negative, in the range [-31,-17]. 1367 // 1368 // Convert: VADD_SPLAT elt, size 1369 // Into: tmp1 = VSPLTIS[BHW] elt+16 1370 // tmp2 = VSPLTIS[BHW] -16 1371 // VADDU[BHW]M tmp1, tmp2 1372 SDValue EltVal = getI32Imm(Elt + 16); 1373 SDNode Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1374* EltVal = getI32Imm(-16); 1375 SDNode Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1376* return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0), 1377 SDValue(Tmp2, 0)); 1378 } 1379 } 1380 } 1381 1382 return SelectCode(N); 1383} 1384 1385/// PostProcessISelDAG - Perform some late peephole optimizations 1386/// on the DAG representation. 1387void PPCDAGToDAGISel::PostprocessISelDAG() { 1388 1389 // Skip peepholes at -O0. 1390 if (TM.getOptLevel() == CodeGenOpt::None) 1391 return; 1392 1393 // These optimizations are currently supported only for 64-bit SVR4. 1394 if (PPCSubTarget.isDarwin() \|\| !PPCSubTarget.isPPC64()) 1395 return; 1396 1397 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode()); 1398 ++Position; 1399 1400 while (Position != CurDAG->allnodes_begin()) { 1401 SDNode N = --Position; 1402* // Skip dead nodes and any non-machine opcodes. 1403 if (N->use_empty() \|\| !N->isMachineOpcode()) 1404 continue; 1405 1406 unsigned FirstOp; 1407 unsigned StorageOpcode = N->getMachineOpcode(); 1408 1409 switch (StorageOpcode) { 1410 default: continue; 1411 1412 case PPC::LBZ: 1413 case PPC::LBZ8: 1414 case PPC::LD: 1415 case PPC::LFD: 1416 case PPC::LFS: 1417 case PPC::LHA: 1418 case PPC::LHA8: 1419 case PPC::LHZ: 1420 case PPC::LHZ8: 1421 case PPC::LWA: 1422 case PPC::LWZ: 1423 case PPC::LWZ8: 1424 FirstOp = 0; 1425 break; 1426 1427 case PPC::STB: 1428 case PPC::STB8: 1429 case PPC::STD: 1430 case PPC::STFD: 1431 case PPC::STFS: 1432 case PPC::STH: 1433 case PPC::STH8: 1434 case PPC::STW: 1435 case PPC::STW8: 1436 FirstOp = 1; 1437 break; 1438 } 1439 1440 // If this is a load or store with a zero offset, we may be able to 1441 // fold an add-immediate into the memory operation. 1442 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) \|\| 1443 N->getConstantOperandVal(FirstOp) != 0) 1444 continue; 1445 1446 SDValue Base = N->getOperand(FirstOp + 1); 1447 if (!Base.isMachineOpcode()) 1448 continue; 1449 1450 unsigned Flags = 0; 1451 bool ReplaceFlags = true; 1452 1453 // When the feeding operation is an add-immediate of some sort, 1454 // determine whether we need to add relocation information to the 1455 // target flags on the immediate operand when we fold it into the 1456 // load instruction. 1457 // 1458 // For something like ADDItocL, the relocation information is 1459 // inferred from the opcode; when we process it in the AsmPrinter, 1460 // we add the necessary relocation there. A load, though, can receive 1461 // relocation from various flavors of ADDIxxx, so we need to carry 1462 // the relocation information in the target flags. 1463 switch (Base.getMachineOpcode()) { 1464 default: continue; 1465 1466 case PPC::ADDI8: 1467 case PPC::ADDI: 1468 // In some cases (such as TLS) the relocation information 1469 // is already in place on the operand, so copying the operand 1470 // is sufficient. 1471 ReplaceFlags = false; 1472 // For these cases, the immediate may not be divisible by 4, in 1473 // which case the fold is illegal for DS-form instructions. (The 1474 // other cases provide aligned addresses and are always safe.) 1475 if ((StorageOpcode == PPC::LWA \|\| 1476 StorageOpcode == PPC::LD \|\| 1477 StorageOpcode == PPC::STD) && 1478 (!isa<ConstantSDNode>(Base.getOperand(1)) \|\| 1479 Base.getConstantOperandVal(1) % 4 != 0)) 1480 continue; 1481 break; 1482 case PPC::ADDIdtprelL: 1483 Flags = PPCII::MO_DTPREL_LO; 1484 break; 1485 case PPC::ADDItlsldL: 1486 Flags = PPCII::MO_TLSLD_LO; 1487 break; 1488 case PPC::ADDItocL: 1489 Flags = PPCII::MO_TOC_LO; 1490 break; 1491 } 1492 1493 // We found an opportunity. Reverse the operands from the add 1494 // immediate and substitute them into the load or store. If 1495 // needed, update the target flags for the immediate operand to 1496 // reflect the necessary relocation information. 1497 DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: "); 1498 DEBUG(Base->dump(CurDAG)); 1499 DEBUG(dbgs() << "\nN: "); 1500 DEBUG(N->dump(CurDAG)); 1501 DEBUG(dbgs() << "\n"); 1502 1503 SDValue ImmOpnd = Base.getOperand(1); 1504 1505 // If the relocation information isn't already present on the 1506 // immediate operand, add it now. 1507 if (ReplaceFlags) { 1508 if (GlobalAddressSDNode GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) { 1509* SDLoc dl(GA); 1510 const GlobalValue GV = GA->getGlobal(); 1511* // We can't perform this optimization for data whose alignment 1512 // is insufficient for the instruction encoding. 1513 if (GV->getAlignment() < 4 && 1514 (StorageOpcode == PPC::LD \|\| StorageOpcode == PPC::STD \|\| 1515 StorageOpcode == PPC::LWA)) { 1516 DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n"); 1517 continue; 1518 } 1519 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags); 1520 } else if (ConstantPoolSDNode CP = 1521* dyn_cast<ConstantPoolSDNode>(ImmOpnd)) { 1522 const Constant C = CP->getConstVal(); 1523* ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64, 1524 CP->getAlignment(), 1525 0, Flags); 1526 } 1527 } 1528 1529 if (FirstOp == 1) // Store 1530 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd, 1531 Base.getOperand(0), N->getOperand(3)); 1532 else // Load 1533 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0), 1534 N->getOperand(2)); 1535 1536 // The add-immediate may now be dead, in which case remove it. 1537 if (Base.getNode()->use_empty()) 1538 CurDAG->RemoveDeadNode(Base.getNode()); 1539 } 1540} 1541 1542 1543/// createPPCISelDag - This pass converts a legalized DAG into a 1544/// PowerPC-specific DAG, ready for instruction scheduling. 1545/// 1546FunctionPass llvm::createPPCISelDag(PPCTargetMachine &TM) { 1547* return new PPCDAGToDAGISel(TM); 1548} 1549 1550static void initializePassOnce(PassRegistry &Registry) { 1551 const char Name = "PowerPC DAG->DAG Pattern Instruction Selection"; 1552* PassInfo PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID, 0, 1553* false, false); 1554 Registry.registerPass(PI, true); 1555} 1556* 1557void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) { 1558 CALL_ONCE_INITIALIZATION(initializePassOnce); 1559} 1560