1//===- MipsRegisterInfo.td - Mips Register defs -----------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Declarations that describe the MIPS register file
12//===----------------------------------------------------------------------===//
13
14// We have banks of 32 registers each.
15class MipsReg<string n> : Register<n> {
16 field bits<5> Num;
17 let Namespace = "Mips";
18}
19
20class MipsRegWithSubRegs<string n, list<Register> subregs>
21 : RegisterWithSubRegs<n, subregs> {
22 field bits<5> Num;
23 let Namespace = "Mips";
24}
25
26// Mips CPU Registers
27class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
28 let Num = num;
29}
30
31// Mips 32-bit FPU Registers
32class FPR<bits<5> num, string n> : MipsReg<n> {
33 let Num = num;
34}
35
36// Mips 64-bit (aliased) FPU Registers
37class AFPR<bits<5> num, string n, list<Register> subregs>
38 : MipsRegWithSubRegs<n, subregs> {
39 let Num = num;
40}
41
42//===----------------------------------------------------------------------===//
43// Registers
44//===----------------------------------------------------------------------===//
45
46let Namespace = "Mips" in {
47
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136 def HI : Register<"hi">, DwarfRegNum<[64]>;
137 def LO : Register<"lo">, DwarfRegNum<[65]>;
138
139 // Status flags register
140 def FCR31 : Register<"31">;
141}
142
143//===----------------------------------------------------------------------===//
144// Subregister Set Definitions
145//===----------------------------------------------------------------------===//
146
147def mips_subreg_fpeven : PatLeaf<(i32 1)>;
148def mips_subreg_fpodd : PatLeaf<(i32 2)>;
149
150def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
151 D8, D9, D10, D11, D12, D13, D14, D15],
152 [F0, F2, F4, F6, F8, F10, F12, F14,
153 F16, F18, F20, F22, F24, F26, F28, F30]>;
154
155def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7,
156 D8, D9, D10, D11, D12, D13, D14, D15],
157 [F1, F3, F5, F7, F9, F11, F13, F15,
158 F17, F19, F21, F23, F25, F27, F29, F31]>;
159
160//===----------------------------------------------------------------------===//
161// Register Classes
162//===----------------------------------------------------------------------===//
163
164def CPURegs : RegisterClass<"Mips", [i32], 32,
165 // Return Values and Arguments
166 [V0, V1, A0, A1, A2, A3,
167 // Not preserved across procedure calls
168 T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
--- 81 unchanged lines hidden (view full) ---
250 [D0, D1, D6, D7,
251 // Not preserved across procedure calls
252 D2, D3, D4, D5, D8, D9,
253 // Callee save
254 D10, D11, D12, D13, D14,
255 // Reserved
256 D15]>
257{
258 let SubRegClassList = [FGR32, FGR32];
259 let MethodProtos = [{
260 iterator allocation_order_end(const MachineFunction &MF) const;
261 }];
262 let MethodBodies = [{
263 AFGR64Class::iterator
264 AFGR64Class::allocation_order_end(const MachineFunction &MF) const {
265 // The last register on the list above is reserved
266 return end()-1;
267 }
268 }];
269}
270
271// Condition Register for floating point operations
272def CCR : RegisterClass<"Mips", [i32], 32, [FCR31]>;
273
274// Hi/Lo Registers
275def HILO : RegisterClass<"Mips", [i32], 32, [HI, LO]>;
276
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Declarations that describe the MIPS register file
12//===----------------------------------------------------------------------===//
13
14// We have banks of 32 registers each.
15class MipsReg<string n> : Register<n> {
16 field bits<5> Num;
17 let Namespace = "Mips";
18}
19
20class MipsRegWithSubRegs<string n, list<Register> subregs>
21 : RegisterWithSubRegs<n, subregs> {
22 field bits<5> Num;
23 let Namespace = "Mips";
24}
25
26// Mips CPU Registers
27class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
28 let Num = num;
29}
30
31// Mips 32-bit FPU Registers
32class FPR<bits<5> num, string n> : MipsReg<n> {
33 let Num = num;
34}
35
36// Mips 64-bit (aliased) FPU Registers
37class AFPR<bits<5> num, string n, list<Register> subregs>
38 : MipsRegWithSubRegs<n, subregs> {
39 let Num = num;
40}
41
42//===----------------------------------------------------------------------===//
43// Registers
44//===----------------------------------------------------------------------===//
45
46let Namespace = "Mips" in {
47
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136 def HI : Register<"hi">, DwarfRegNum<[64]>;
137 def LO : Register<"lo">, DwarfRegNum<[65]>;
138
139 // Status flags register
140 def FCR31 : Register<"31">;
141}
142
143//===----------------------------------------------------------------------===//
144// Subregister Set Definitions
145//===----------------------------------------------------------------------===//
146
147def mips_subreg_fpeven : PatLeaf<(i32 1)>;
148def mips_subreg_fpodd : PatLeaf<(i32 2)>;
149
150def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
151 D8, D9, D10, D11, D12, D13, D14, D15],
152 [F0, F2, F4, F6, F8, F10, F12, F14,
153 F16, F18, F20, F22, F24, F26, F28, F30]>;
154
155def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7,
156 D8, D9, D10, D11, D12, D13, D14, D15],
157 [F1, F3, F5, F7, F9, F11, F13, F15,
158 F17, F19, F21, F23, F25, F27, F29, F31]>;
159
160//===----------------------------------------------------------------------===//
161// Register Classes
162//===----------------------------------------------------------------------===//
163
164def CPURegs : RegisterClass<"Mips", [i32], 32,
165 // Return Values and Arguments
166 [V0, V1, A0, A1, A2, A3,
167 // Not preserved across procedure calls
168 T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
--- 81 unchanged lines hidden (view full) ---
250 [D0, D1, D6, D7,
251 // Not preserved across procedure calls
252 D2, D3, D4, D5, D8, D9,
253 // Callee save
254 D10, D11, D12, D13, D14,
255 // Reserved
256 D15]>
257{
258 let SubRegClassList = [FGR32, FGR32];
259 let MethodProtos = [{
260 iterator allocation_order_end(const MachineFunction &MF) const;
261 }];
262 let MethodBodies = [{
263 AFGR64Class::iterator
264 AFGR64Class::allocation_order_end(const MachineFunction &MF) const {
265 // The last register on the list above is reserved
266 return end()-1;
267 }
268 }];
269}
270
271// Condition Register for floating point operations
272def CCR : RegisterClass<"Mips", [i32], 32, [FCR31]>;
273
274// Hi/Lo Registers
275def HILO : RegisterClass<"Mips", [i32], 32, [HI, LO]>;
276