1//===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the ARM v6 processors.
11//
12//===----------------------------------------------------------------------===//
13
14// Model based on ARM1176
15//
16// Scheduling information derived from "ARM1176JZF-S Technical Reference Manual".
17//
18def ARMV6Itineraries : ProcessorItineraries<[
19 //
20 // No operand cycles
21 InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
22 //
23 // Binary Instructions that produce a result
24 InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
25 InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>], [2, 2, 2]>,
26 InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>], [2, 2, 1]>,
27 InstrItinData<IIC_iALUsr , [InstrStage<2, [FU_Pipe0]>], [3, 3, 2, 1]>,
28 //
29 // Unary Instructions that produce a result
30 InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
31 InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>], [2, 1]>,
32 InstrItinData<IIC_iUNAsr , [InstrStage<2, [FU_Pipe0]>], [3, 2, 1]>,
33 //
34 // Compare instructions
35 InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>], [2]>,
36 InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
37 InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>], [2, 1]>,
38 InstrItinData<IIC_iCMPsr , [InstrStage<2, [FU_Pipe0]>], [3, 2, 1]>,
39 //
40 // Move instructions, unconditional
41 InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>], [2]>,
42 InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
43 InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>], [2, 1]>,
44 InstrItinData<IIC_iMOVsr , [InstrStage<2, [FU_Pipe0]>], [3, 2, 1]>,
45 //
46 // Move instructions, conditional
47 InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>], [3]>,
48 InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>], [3, 2]>,
49 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>], [3, 1]>,
50 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>], [4, 2, 1]>,
51
52 // Integer multiply pipeline
53 //
54 InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>], [4, 1, 1]>,
55 InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>], [4, 1, 1, 2]>,
56 InstrItinData<IIC_iMUL32 , [InstrStage<2, [FU_Pipe0]>], [5, 1, 1]>,
57 InstrItinData<IIC_iMAC32 , [InstrStage<2, [FU_Pipe0]>], [5, 1, 1, 2]>,
58 InstrItinData<IIC_iMUL64 , [InstrStage<3, [FU_Pipe0]>], [6, 1, 1]>,
59 InstrItinData<IIC_iMAC64 , [InstrStage<3, [FU_Pipe0]>], [6, 1, 1, 2]>,
60
61 // Integer load pipeline
62 //
63 // Immediate offset
64 InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>], [4, 1]>,
65 //
66 // Register offset
67 InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>], [4, 1, 1]>,
68 //
69 // Scaled register offset, issues over 2 cycles
70 InstrItinData<IIC_iLoadsi , [InstrStage<2, [FU_Pipe0]>], [5, 2, 1]>,
71 //
72 // Immediate offset with update
73 InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>], [4, 2, 1]>,
74 //
75 // Register offset with update
76 InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>], [4, 2, 1, 1]>,
77 //
78 // Scaled register offset with update, issues over 2 cycles
79 InstrItinData<IIC_iLoadsiu , [InstrStage<2, [FU_Pipe0]>], [5, 2, 2, 1]>,
80
81 //
82 // Load multiple
83 InstrItinData<IIC_iLoadm , [InstrStage<3, [FU_Pipe0]>]>,
84
85 // Integer store pipeline
86 //
87 // Immediate offset
88 InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>], [2, 1]>,
89 //
90 // Register offset
91 InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>], [2, 1, 1]>,
92
93 //
94 // Scaled register offset, issues over 2 cycles
95 InstrItinData<IIC_iStoresi , [InstrStage<2, [FU_Pipe0]>], [2, 2, 1]>,
96 //
97 // Immediate offset with update
98 InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>], [2, 2, 1]>,
99 //
100 // Register offset with update
101 InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>], [2, 2, 1, 1]>,
102 //
103 // Scaled register offset with update, issues over 2 cycles
104 InstrItinData<IIC_iStoresiu, [InstrStage<2, [FU_Pipe0]>], [2, 2, 2, 1]>,
105 //
106 // Store multiple
107 InstrItinData<IIC_iStorem , [InstrStage<3, [FU_Pipe0]>]>,
108
109 // Branch
110 //
111 // no delay slots, so the latency of a branch is unimportant
112 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
113
114 // VFP
115 // Issue through integer pipeline, and execute in NEON unit. We assume
116 // RunFast mode so that NFP pipeline is used for single-precision when
117 // possible.
118 //
119 // FP Special Register to Integer Register File Move
120 InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0]>], [3]>,
121 //
122 // Single-precision FP Unary
123 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0]>], [5, 2]>,
124 //
125 // Double-precision FP Unary
126 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0]>], [5, 2]>,
127 //
128 // Single-precision FP Compare
129 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
130 //
131 // Double-precision FP Compare
132 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
133 //
134 // Single to Double FP Convert
135 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0]>], [5, 2]>,
136 //
137 // Double to Single FP Convert
138 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0]>], [5, 2]>,
139 //
140 // Single-Precision FP to Integer Convert
141 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0]>], [9, 2]>,
142 //
143 // Double-Precision FP to Integer Convert
144 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0]>], [9, 2]>,
145 //
146 // Integer to Single-Precision FP Convert
147 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0]>], [9, 2]>,
148 //
149 // Integer to Double-Precision FP Convert
150 InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0]>], [9, 2]>,
151 //
152 // Single-precision FP ALU
153 InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0]>], [9, 2, 2]>,
154 //
155 // Double-precision FP ALU
156 InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0]>], [9, 2, 2]>,
157 //
158 // Single-precision FP Multiply
159 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0]>], [9, 2, 2]>,
160 //
161 // Double-precision FP Multiply
162 InstrItinData<IIC_fpMUL64 , [InstrStage<2, [FU_Pipe0]>], [9, 2, 2]>,
163 //
164 // Single-precision FP MAC
165 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0]>], [9, 2, 2, 2]>,
166 //
167 // Double-precision FP MAC
168 InstrItinData<IIC_fpMAC64 , [InstrStage<2, [FU_Pipe0]>], [9, 2, 2, 2]>,
169 //
170 // Single-precision FP DIV
171 InstrItinData<IIC_fpDIV32 , [InstrStage<15, [FU_Pipe0]>], [20, 2, 2]>,
172 //
173 // Double-precision FP DIV
174 InstrItinData<IIC_fpDIV64 , [InstrStage<29, [FU_Pipe0]>], [34, 2, 2]>,
175 //
176 // Single-precision FP SQRT
177 InstrItinData<IIC_fpSQRT32 , [InstrStage<15, [FU_Pipe0]>], [20, 2, 2]>,
178 //
179 // Double-precision FP SQRT
180 InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [FU_Pipe0]>], [34, 2, 2]>,
181 //
182 // Single-precision FP Load
183 InstrItinData<IIC_fpLoad32 , [InstrStage<1, [FU_Pipe0]>], [5, 2, 2]>,
184 //
185 // Double-precision FP Load
186 InstrItinData<IIC_fpLoad64 , [InstrStage<1, [FU_Pipe0]>], [5, 2, 2]>,
187 //
188 // FP Load Multiple
189 InstrItinData<IIC_fpLoadm , [InstrStage<3, [FU_Pipe0]>]>,
190 //
191 // Single-precision FP Store
192 InstrItinData<IIC_fpStore32 , [InstrStage<1, [FU_Pipe0]>], [2, 2, 2]>,
193 //
194 // Double-precision FP Store
195 // use FU_Issue to enforce the 1 load/store per cycle limit
196 InstrItinData<IIC_fpStore64 , [InstrStage<1, [FU_Pipe0]>], [2, 2, 2]>,
197 //
198 // FP Store Multiple
199 InstrItinData<IIC_fpStorem , [InstrStage<3, [FU_Pipe0]>]>
200]>;
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the ARM v6 processors.
11//
12//===----------------------------------------------------------------------===//
13
14// Model based on ARM1176
15//
16// Scheduling information derived from "ARM1176JZF-S Technical Reference Manual".
17//
18def ARMV6Itineraries : ProcessorItineraries<[
19 //
20 // No operand cycles
21 InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
22 //
23 // Binary Instructions that produce a result
24 InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
25 InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>], [2, 2, 2]>,
26 InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>], [2, 2, 1]>,
27 InstrItinData<IIC_iALUsr , [InstrStage<2, [FU_Pipe0]>], [3, 3, 2, 1]>,
28 //
29 // Unary Instructions that produce a result
30 InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
31 InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>], [2, 1]>,
32 InstrItinData<IIC_iUNAsr , [InstrStage<2, [FU_Pipe0]>], [3, 2, 1]>,
33 //
34 // Compare instructions
35 InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>], [2]>,
36 InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
37 InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>], [2, 1]>,
38 InstrItinData<IIC_iCMPsr , [InstrStage<2, [FU_Pipe0]>], [3, 2, 1]>,
39 //
40 // Move instructions, unconditional
41 InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>], [2]>,
42 InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
43 InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>], [2, 1]>,
44 InstrItinData<IIC_iMOVsr , [InstrStage<2, [FU_Pipe0]>], [3, 2, 1]>,
45 //
46 // Move instructions, conditional
47 InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>], [3]>,
48 InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>], [3, 2]>,
49 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>], [3, 1]>,
50 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>], [4, 2, 1]>,
51
52 // Integer multiply pipeline
53 //
54 InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>], [4, 1, 1]>,
55 InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>], [4, 1, 1, 2]>,
56 InstrItinData<IIC_iMUL32 , [InstrStage<2, [FU_Pipe0]>], [5, 1, 1]>,
57 InstrItinData<IIC_iMAC32 , [InstrStage<2, [FU_Pipe0]>], [5, 1, 1, 2]>,
58 InstrItinData<IIC_iMUL64 , [InstrStage<3, [FU_Pipe0]>], [6, 1, 1]>,
59 InstrItinData<IIC_iMAC64 , [InstrStage<3, [FU_Pipe0]>], [6, 1, 1, 2]>,
60
61 // Integer load pipeline
62 //
63 // Immediate offset
64 InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>], [4, 1]>,
65 //
66 // Register offset
67 InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>], [4, 1, 1]>,
68 //
69 // Scaled register offset, issues over 2 cycles
70 InstrItinData<IIC_iLoadsi , [InstrStage<2, [FU_Pipe0]>], [5, 2, 1]>,
71 //
72 // Immediate offset with update
73 InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>], [4, 2, 1]>,
74 //
75 // Register offset with update
76 InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>], [4, 2, 1, 1]>,
77 //
78 // Scaled register offset with update, issues over 2 cycles
79 InstrItinData<IIC_iLoadsiu , [InstrStage<2, [FU_Pipe0]>], [5, 2, 2, 1]>,
80
81 //
82 // Load multiple
83 InstrItinData<IIC_iLoadm , [InstrStage<3, [FU_Pipe0]>]>,
84
85 // Integer store pipeline
86 //
87 // Immediate offset
88 InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>], [2, 1]>,
89 //
90 // Register offset
91 InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>], [2, 1, 1]>,
92
93 //
94 // Scaled register offset, issues over 2 cycles
95 InstrItinData<IIC_iStoresi , [InstrStage<2, [FU_Pipe0]>], [2, 2, 1]>,
96 //
97 // Immediate offset with update
98 InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>], [2, 2, 1]>,
99 //
100 // Register offset with update
101 InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>], [2, 2, 1, 1]>,
102 //
103 // Scaled register offset with update, issues over 2 cycles
104 InstrItinData<IIC_iStoresiu, [InstrStage<2, [FU_Pipe0]>], [2, 2, 2, 1]>,
105 //
106 // Store multiple
107 InstrItinData<IIC_iStorem , [InstrStage<3, [FU_Pipe0]>]>,
108
109 // Branch
110 //
111 // no delay slots, so the latency of a branch is unimportant
112 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
113
114 // VFP
115 // Issue through integer pipeline, and execute in NEON unit. We assume
116 // RunFast mode so that NFP pipeline is used for single-precision when
117 // possible.
118 //
119 // FP Special Register to Integer Register File Move
120 InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0]>], [3]>,
121 //
122 // Single-precision FP Unary
123 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0]>], [5, 2]>,
124 //
125 // Double-precision FP Unary
126 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0]>], [5, 2]>,
127 //
128 // Single-precision FP Compare
129 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
130 //
131 // Double-precision FP Compare
132 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
133 //
134 // Single to Double FP Convert
135 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0]>], [5, 2]>,
136 //
137 // Double to Single FP Convert
138 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0]>], [5, 2]>,
139 //
140 // Single-Precision FP to Integer Convert
141 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0]>], [9, 2]>,
142 //
143 // Double-Precision FP to Integer Convert
144 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0]>], [9, 2]>,
145 //
146 // Integer to Single-Precision FP Convert
147 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0]>], [9, 2]>,
148 //
149 // Integer to Double-Precision FP Convert
150 InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0]>], [9, 2]>,
151 //
152 // Single-precision FP ALU
153 InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0]>], [9, 2, 2]>,
154 //
155 // Double-precision FP ALU
156 InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0]>], [9, 2, 2]>,
157 //
158 // Single-precision FP Multiply
159 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0]>], [9, 2, 2]>,
160 //
161 // Double-precision FP Multiply
162 InstrItinData<IIC_fpMUL64 , [InstrStage<2, [FU_Pipe0]>], [9, 2, 2]>,
163 //
164 // Single-precision FP MAC
165 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0]>], [9, 2, 2, 2]>,
166 //
167 // Double-precision FP MAC
168 InstrItinData<IIC_fpMAC64 , [InstrStage<2, [FU_Pipe0]>], [9, 2, 2, 2]>,
169 //
170 // Single-precision FP DIV
171 InstrItinData<IIC_fpDIV32 , [InstrStage<15, [FU_Pipe0]>], [20, 2, 2]>,
172 //
173 // Double-precision FP DIV
174 InstrItinData<IIC_fpDIV64 , [InstrStage<29, [FU_Pipe0]>], [34, 2, 2]>,
175 //
176 // Single-precision FP SQRT
177 InstrItinData<IIC_fpSQRT32 , [InstrStage<15, [FU_Pipe0]>], [20, 2, 2]>,
178 //
179 // Double-precision FP SQRT
180 InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [FU_Pipe0]>], [34, 2, 2]>,
181 //
182 // Single-precision FP Load
183 InstrItinData<IIC_fpLoad32 , [InstrStage<1, [FU_Pipe0]>], [5, 2, 2]>,
184 //
185 // Double-precision FP Load
186 InstrItinData<IIC_fpLoad64 , [InstrStage<1, [FU_Pipe0]>], [5, 2, 2]>,
187 //
188 // FP Load Multiple
189 InstrItinData<IIC_fpLoadm , [InstrStage<3, [FU_Pipe0]>]>,
190 //
191 // Single-precision FP Store
192 InstrItinData<IIC_fpStore32 , [InstrStage<1, [FU_Pipe0]>], [2, 2, 2]>,
193 //
194 // Double-precision FP Store
195 // use FU_Issue to enforce the 1 load/store per cycle limit
196 InstrItinData<IIC_fpStore64 , [InstrStage<1, [FU_Pipe0]>], [2, 2, 2]>,
197 //
198 // FP Store Multiple
199 InstrItinData<IIC_fpStorem , [InstrStage<3, [FU_Pipe0]>]>
200]>;