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ARMInstrThumb2.td (200581) ARMInstrThumb2.td (201360)
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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160
161//===----------------------------------------------------------------------===//
162// Multiclass helpers...
163//
164
165/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
166/// unary operation that produces a value. These are predicable and can be
167/// changed to modify CPSR.
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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160
161//===----------------------------------------------------------------------===//
162// Multiclass helpers...
163//
164
165/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
166/// unary operation that produces a value. These are predicable and can be
167/// changed to modify CPSR.
168multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
168multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
169 bit Cheap = 0, bit ReMat = 0> {
169 // shifted imm
170 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
171 opc, "\t$dst, $src",
172 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
173 let isAsCheapAsAMove = Cheap;
174 let isReMaterializable = ReMat;
170 // shifted imm
171 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
172 opc, "\t$dst, $src",
173 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
174 let isAsCheapAsAMove = Cheap;
175 let isReMaterializable = ReMat;
176 let Inst{31-27} = 0b11110;
177 let Inst{25} = 0;
178 let Inst{24-21} = opcod;
179 let Inst{20} = ?; // The S bit.
180 let Inst{19-16} = 0b1111; // Rn
181 let Inst{15} = 0;
175 }
176 // register
177 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
178 opc, ".w\t$dst, $src",
182 }
183 // register
184 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
185 opc, ".w\t$dst, $src",
179 [(set GPR:$dst, (opnode GPR:$src))]>;
186 [(set GPR:$dst, (opnode GPR:$src))]> {
187 let Inst{31-27} = 0b11101;
188 let Inst{26-25} = 0b01;
189 let Inst{24-21} = opcod;
190 let Inst{20} = ?; // The S bit.
191 let Inst{19-16} = 0b1111; // Rn
192 let Inst{14-12} = 0b000; // imm3
193 let Inst{7-6} = 0b00; // imm2
194 let Inst{5-4} = 0b00; // type
195 }
180 // shifted register
181 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
182 opc, ".w\t$dst, $src",
196 // shifted register
197 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
198 opc, ".w\t$dst, $src",
183 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
199 [(set GPR:$dst, (opnode t2_so_reg:$src))]> {
200 let Inst{31-27} = 0b11101;
201 let Inst{26-25} = 0b01;
202 let Inst{24-21} = opcod;
203 let Inst{20} = ?; // The S bit.
204 let Inst{19-16} = 0b1111; // Rn
205 }
184}
185
186/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
187// binary operation that produces a value. These are predicable and can be
188/// changed to modify CPSR.
206}
207
208/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
209// binary operation that produces a value. These are predicable and can be
210/// changed to modify CPSR.
189multiclass T2I_bin_irs211multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
190 bit Commutable = 0, string wide =""> {
191 // shifted imm
192 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
193 opc, "\t$dst, $lhs, $rhs",
212 bit Commutable = 0, string wide =""> {
213 // shifted imm
214 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
215 opc, "\t$dst, $lhs, $rhs",
194 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
216 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
217 let Inst{31-27} = 0b11110;
218 let Inst{25} = 0;
219 let Inst{24-21} = opcod;
220 let Inst{20} = ?; // The S bit.
221 let Inst{15} = 0;
222 }
195 // register
196 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
197 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
198 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
199 let isCommutable = Commutable;
223 // register
224 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
225 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
226 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
227 let isCommutable = Commutable;
228 let Inst{31-27} = 0b11101;
229 let Inst{26-25} = 0b01;
230 let Inst{24-21} = opcod;
231 let Inst{20} = ?; // The S bit.
232 let Inst{14-12} = 0b000; // imm3
233 let Inst{7-6} = 0b00; // imm2
234 let Inst{5-4} = 0b00; // type
200 }
201 // shifted register
202 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
203 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
235 }
236 // shifted register
237 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
238 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
204 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
239 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
240 let Inst{31-27} = 0b11101;
241 let Inst{26-25} = 0b01;
242 let Inst{24-21} = opcod;
243 let Inst{20} = ?; // The S bit.
244 }
205}
206
207/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
208// the ".w" prefix to indicate that they are wide.
245}
246
247/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
248// the ".w" prefix to indicate that they are wide.
209multiclass T2I_bin_w_irs<string opc, PatFrag opnode, bit Commutable = 0> :
210 T2I_bin_irs<opc, opnode, Commutable, ".w">;
249multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
250 bit Commutable = 0> :
251 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
211
212/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
213/// reversed. It doesn't define the 'rr' form since it's handled by its
214/// T2I_bin_irs counterpart.
252
253/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
254/// reversed. It doesn't define the 'rr' form since it's handled by its
255/// T2I_bin_irs counterpart.
215multiclass T2I_rbin_is {
256multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
216 // shifted imm
217 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
218 opc, ".w\t$dst, $rhs, $lhs",
257 // shifted imm
258 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
259 opc, ".w\t$dst, $rhs, $lhs",
219 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
260 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
261 let Inst{31-27} = 0b11110;
262 let Inst{25} = 0;
263 let Inst{24-21} = opcod;
264 let Inst{20} = 0; // The S bit.
265 let Inst{15} = 0;
266 }
220 // shifted register
221 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
222 opc, "\t$dst, $rhs, $lhs",
267 // shifted register
268 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
269 opc, "\t$dst, $rhs, $lhs",
223 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
270 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
271 let Inst{31-27} = 0b11101;
272 let Inst{26-25} = 0b01;
273 let Inst{24-21} = opcod;
274 let Inst{20} = 0; // The S bit.
275 }
224}
225
226/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
227/// instruction modifies the CPSR register.
228let Defs = [CPSR] in {
276}
277
278/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
279/// instruction modifies the CPSR register.
280let Defs = [CPSR] in {
229multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
281multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
282 bit Commutable = 0> {
230 // shifted imm
231 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
232 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
283 // shifted imm
284 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
285 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
233 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
286 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
287 let Inst{31-27} = 0b11110;
288 let Inst{25} = 0;
289 let Inst{24-21} = opcod;
290 let Inst{20} = 1; // The S bit.
291 let Inst{15} = 0;
292 }
234 // register
235 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
236 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
237 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
238 let isCommutable = Commutable;
293 // register
294 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
295 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
296 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
297 let isCommutable = Commutable;
298 let Inst{31-27} = 0b11101;
299 let Inst{26-25} = 0b01;
300 let Inst{24-21} = opcod;
301 let Inst{20} = 1; // The S bit.
302 let Inst{14-12} = 0b000; // imm3
303 let Inst{7-6} = 0b00; // imm2
304 let Inst{5-4} = 0b00; // type
239 }
240 // shifted register
241 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
242 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
305 }
306 // shifted register
307 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
308 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
243 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
309 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
310 let Inst{31-27} = 0b11101;
311 let Inst{26-25} = 0b01;
312 let Inst{24-21} = opcod;
313 let Inst{20} = 1; // The S bit.
314 }
244}
245}
246
247/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
248/// patterns for a binary operation that produces a value.
315}
316}
317
318/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
319/// patterns for a binary operation that produces a value.
249multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
320multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
321 bit Commutable = 0> {
250 // shifted imm
251 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
252 opc, ".w\t$dst, $lhs, $rhs",
322 // shifted imm
323 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
324 opc, ".w\t$dst, $lhs, $rhs",
253 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
325 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
326 let Inst{31-27} = 0b11110;
327 let Inst{25} = 0;
328 let Inst{24} = 1;
329 let Inst{23-21} = op23_21;
330 let Inst{20} = 0; // The S bit.
331 let Inst{15} = 0;
332 }
254 // 12-bit imm
255 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
256 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
333 // 12-bit imm
334 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
335 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
257 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
336 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
337 let Inst{31-27} = 0b11110;
338 let Inst{25} = 1;
339 let Inst{24} = 0;
340 let Inst{23-21} = op23_21;
341 let Inst{20} = 0; // The S bit.
342 let Inst{15} = 0;
343 }
258 // register
259 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
260 opc, ".w\t$dst, $lhs, $rhs",
261 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
262 let isCommutable = Commutable;
344 // register
345 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
346 opc, ".w\t$dst, $lhs, $rhs",
347 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
348 let isCommutable = Commutable;
349 let Inst{31-27} = 0b11101;
350 let Inst{26-25} = 0b01;
351 let Inst{24} = 1;
352 let Inst{23-21} = op23_21;
353 let Inst{20} = 0; // The S bit.
354 let Inst{14-12} = 0b000; // imm3
355 let Inst{7-6} = 0b00; // imm2
356 let Inst{5-4} = 0b00; // type
263 }
264 // shifted register
265 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
266 opc, ".w\t$dst, $lhs, $rhs",
357 }
358 // shifted register
359 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
360 opc, ".w\t$dst, $lhs, $rhs",
267 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
361 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
362 let Inst{31-27} = 0b11101;
363 let Inst{24} = 1;
364 let Inst{26-25} = 0b01;
365 let Inst{23-21} = op23_21;
366 let Inst{20} = 0; // The S bit.
367 }
268}
269
270/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
271/// for a binary operation that produces a value and use and define the carry
272/// bit. It's not predicable.
273let Uses = [CPSR] in {
368}
369
370/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
371/// for a binary operation that produces a value and use and define the carry
372/// bit. It's not predicable.
373let Uses = [CPSR] in {
274multiclass T2I_adde_sube_irs {
374multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, bit Commutable = 0> {
275 // shifted imm
276 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
277 opc, "\t$dst, $lhs, $rhs",
278 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
375 // shifted imm
376 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
377 opc, "\t$dst, $lhs, $rhs",
378 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
279 Requires<[IsThumb2, CarryDefIsUnused]>;
379 Requires<[IsThumb2, CarryDefIsUnused]> {
380 let Inst{31-27} = 0b11110;
381 let Inst{25} = 0;
382 let Inst{24-21} = opcod;
383 let Inst{20} = 0; // The S bit.
384 let Inst{15} = 0;
385 }
280 // register
281 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
282 opc, ".w\t$dst, $lhs, $rhs",
283 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
284 Requires<[IsThumb2, CarryDefIsUnused]> {
285 let isCommutable = Commutable;
386 // register
387 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
388 opc, ".w\t$dst, $lhs, $rhs",
389 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
390 Requires<[IsThumb2, CarryDefIsUnused]> {
391 let isCommutable = Commutable;
392 let Inst{31-27} = 0b11101;
393 let Inst{26-25} = 0b01;
394 let Inst{24-21} = opcod;
395 let Inst{20} = 0; // The S bit.
396 let Inst{14-12} = 0b000; // imm3
397 let Inst{7-6} = 0b00; // imm2
398 let Inst{5-4} = 0b00; // type
286 }
287 // shifted register
288 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
289 opc, ".w\t$dst, $lhs, $rhs",
290 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
399 }
400 // shifted register
401 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
402 opc, ".w\t$dst, $lhs, $rhs",
403 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
291 Requires<[IsThumb2, CarryDefIsUnused]>;
404 Requires<[IsThumb2, CarryDefIsUnused]> {
405 let Inst{31-27} = 0b11101;
406 let Inst{26-25} = 0b01;
407 let Inst{24-21} = opcod;
408 let Inst{20} = 0; // The S bit.
409 }
292 // Carry setting variants
293 // shifted imm
294 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
295 !strconcat(opc, "s\t$dst, $lhs, $rhs"),
296 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
297 Requires<[IsThumb2, CarryDefIsUsed]> {
410 // Carry setting variants
411 // shifted imm
412 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
413 !strconcat(opc, "s\t$dst, $lhs, $rhs"),
414 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
415 Requires<[IsThumb2, CarryDefIsUsed]> {
298 let Defs = [CPSR];
299 }
416 let Defs = [CPSR];
417 let Inst{31-27} = 0b11110;
418 let Inst{25} = 0;
419 let Inst{24-21} = opcod;
420 let Inst{20} = 1; // The S bit.
421 let Inst{15} = 0;
422 }
300 // register
301 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
302 !strconcat(opc, "s.w\t$dst, $lhs, $rhs"),
303 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
304 Requires<[IsThumb2, CarryDefIsUsed]> {
423 // register
424 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
425 !strconcat(opc, "s.w\t$dst, $lhs, $rhs"),
426 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
427 Requires<[IsThumb2, CarryDefIsUsed]> {
305 let Defs = [CPSR];
306 let isCommutable = Commutable;
428 let Defs = [CPSR];
429 let isCommutable = Commutable;
430 let Inst{31-27} = 0b11101;
431 let Inst{26-25} = 0b01;
432 let Inst{24-21} = opcod;
433 let Inst{20} = 1; // The S bit.
434 let Inst{14-12} = 0b000; // imm3
435 let Inst{7-6} = 0b00; // imm2
436 let Inst{5-4} = 0b00; // type
307 }
308 // shifted register
309 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
310 !strconcat(opc, "s.w\t$dst, $lhs, $rhs"),
311 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
312 Requires<[IsThumb2, CarryDefIsUsed]> {
437 }
438 // shifted register
439 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
440 !strconcat(opc, "s.w\t$dst, $lhs, $rhs"),
441 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
442 Requires<[IsThumb2, CarryDefIsUsed]> {
313 let Defs = [CPSR];
443 let Defs = [CPSR];
444 let Inst{31-27} = 0b11101;
445 let Inst{26-25} = 0b01;
446 let Inst{24-21} = opcod;
447 let Inst{20} = 1; // The S bit.
314 }
315}
316}
317
318/// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
319let Defs = [CPSR] in {
448 }
449}
450}
451
452/// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
453let Defs = [CPSR] in {
320multiclass T2I_rbin_s_is {
454multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
321 // shifted imm
322 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
323 IIC_iALUi,
324 !strconcat(opc, "${s}.w\t$dst, $rhs, $lhs"),
455 // shifted imm
456 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
457 IIC_iALUi,
458 !strconcat(opc, "${s}.w\t$dst, $rhs, $lhs"),
325 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
459 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
460 let Inst{31-27} = 0b11110;
461 let Inst{25} = 0;
462 let Inst{24-21} = opcod;
463 let Inst{20} = 1; // The S bit.
464 let Inst{15} = 0;
465 }
326 // shifted register
327 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
328 IIC_iALUsi,
329 !strconcat(opc, "${s}\t$dst, $rhs, $lhs"),
466 // shifted register
467 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
468 IIC_iALUsi,
469 !strconcat(opc, "${s}\t$dst, $rhs, $lhs"),
330 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
470 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
471 let Inst{31-27} = 0b11101;
472 let Inst{26-25} = 0b01;
473 let Inst{24-21} = opcod;
474 let Inst{20} = 1; // The S bit.
475 }
331}
332}
333
334/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
335// rotate operation that produces a value.
476}
477}
478
479/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
480// rotate operation that produces a value.
336multiclass T2I_sh_ir {
481multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
337 // 5-bit imm
338 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
339 opc, ".w\t$dst, $lhs, $rhs",
482 // 5-bit imm
483 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
484 opc, ".w\t$dst, $lhs, $rhs",
340 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
485 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]> {
486 let Inst{31-27} = 0b11101;
487 let Inst{26-21} = 0b010010;
488 let Inst{19-16} = 0b1111; // Rn
489 let Inst{5-4} = opcod;
490 }
341 // register
342 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr,
343 opc, ".w\t$dst, $lhs, $rhs",
491 // register
492 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr,
493 opc, ".w\t$dst, $lhs, $rhs",
344 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
494 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
495 let Inst{31-27} = 0b11111;
496 let Inst{26-23} = 0b0100;
497 let Inst{22-21} = opcod;
498 let Inst{15-12} = 0b1111;
499 let Inst{7-4} = 0b0000;
500 }
345}
346
501}
502
347/// T2I_cmp_is - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
503/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
348/// patterns. Similar to T2I_bin_irs except the instruction does not produce
349/// a explicit result, only implicitly set CPSR.
350let Defs = [CPSR] in {
504/// patterns. Similar to T2I_bin_irs except the instruction does not produce
505/// a explicit result, only implicitly set CPSR.
506let Defs = [CPSR] in {
351multiclass T2I_cmp_is<string opc, PatFrag opnode> {
507multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
352 // shifted imm
353 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
354 opc, ".w\t$lhs, $rhs",
508 // shifted imm
509 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
510 opc, ".w\t$lhs, $rhs",
355 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
511 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
512 let Inst{31-27} = 0b11110;
513 let Inst{25} = 0;
514 let Inst{24-21} = opcod;
515 let Inst{20} = 1; // The S bit.
516 let Inst{15} = 0;
517 let Inst{11-8} = 0b1111; // Rd
518 }
356 // register
357 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
358 opc, ".w\t$lhs, $rhs",
519 // register
520 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
521 opc, ".w\t$lhs, $rhs",
359 [(opnode GPR:$lhs, GPR:$rhs)]>;
522 [(opnode GPR:$lhs, GPR:$rhs)]> {
523 let Inst{31-27} = 0b11101;
524 let Inst{26-25} = 0b01;
525 let Inst{24-21} = opcod;
526 let Inst{20} = 1; // The S bit.
527 let Inst{14-12} = 0b000; // imm3
528 let Inst{11-8} = 0b1111; // Rd
529 let Inst{7-6} = 0b00; // imm2
530 let Inst{5-4} = 0b00; // type
531 }
360 // shifted register
361 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
362 opc, ".w\t$lhs, $rhs",
532 // shifted register
533 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
534 opc, ".w\t$lhs, $rhs",
363 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
535 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
536 let Inst{31-27} = 0b11101;
537 let Inst{26-25} = 0b01;
538 let Inst{24-21} = opcod;
539 let Inst{20} = 1; // The S bit.
540 let Inst{11-8} = 0b1111; // Rd
541 }
364}
365}
366
367/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
542}
543}
544
545/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
368multiclass T2I_ld {
546multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> {
369 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
370 opc, ".w\t$dst, $addr",
547 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
548 opc, ".w\t$dst, $addr",
371 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
549 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
550 let Inst{31-27} = 0b11111;
551 let Inst{26-25} = 0b00;
552 let Inst{24} = signed;
553 let Inst{23} = 1;
554 let Inst{22-21} = opcod;
555 let Inst{20} = 1; // load
556 }
372 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
373 opc, "\t$dst, $addr",
557 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
558 opc, "\t$dst, $addr",
374 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
559 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
560 let Inst{31-27} = 0b11111;
561 let Inst{26-25} = 0b00;
562 let Inst{24} = signed;
563 let Inst{23} = 0;
564 let Inst{22-21} = opcod;
565 let Inst{20} = 1; // load
566 let Inst{11} = 1;
567 // Offset: index==TRUE, wback==FALSE
568 let Inst{10} = 1; // The P bit.
569 let Inst{8} = 0; // The W bit.
570 }
375 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
376 opc, ".w\t$dst, $addr",
571 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
572 opc, ".w\t$dst, $addr",
377 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
573 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
574 let Inst{31-27} = 0b11111;
575 let Inst{26-25} = 0b00;
576 let Inst{24} = signed;
577 let Inst{23} = 0;
578 let Inst{22-21} = opcod;
579 let Inst{20} = 1; // load
580 let Inst{11-6} = 0b000000;
581 }
378 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
379 opc, ".w\t$dst, $addr",
380 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
381 let isReMaterializable = 1;
582 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
583 opc, ".w\t$dst, $addr",
584 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
585 let isReMaterializable = 1;
586 let Inst{31-27} = 0b11111;
587 let Inst{26-25} = 0b00;
588 let Inst{24} = signed;
589 let Inst{23} = ?; // add = (U == '1')
590 let Inst{22-21} = opcod;
591 let Inst{20} = 1; // load
592 let Inst{19-16} = 0b1111; // Rn
382 }
383}
384
385/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
593 }
594}
595
596/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
386multiclass T2I_st {
597multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> {
387 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
388 opc, ".w\t$src, $addr",
598 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
599 opc, ".w\t$src, $addr",
389 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
600 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
601 let Inst{31-27} = 0b11111;
602 let Inst{26-23} = 0b0001;
603 let Inst{22-21} = opcod;
604 let Inst{20} = 0; // !load
605 }
390 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
391 opc, "\t$src, $addr",
606 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
607 opc, "\t$src, $addr",
392 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
608 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
609 let Inst{31-27} = 0b11111;
610 let Inst{26-23} = 0b0000;
611 let Inst{22-21} = opcod;
612 let Inst{20} = 0; // !load
613 let Inst{11} = 1;
614 // Offset: index==TRUE, wback==FALSE
615 let Inst{10} = 1; // The P bit.
616 let Inst{8} = 0; // The W bit.
617 }
393 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
394 opc, ".w\t$src, $addr",
618 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
619 opc, ".w\t$src, $addr",
395 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
620 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
621 let Inst{31-27} = 0b11111;
622 let Inst{26-23} = 0b0000;
623 let Inst{22-21} = opcod;
624 let Inst{20} = 0; // !load
625 let Inst{11-6} = 0b000000;
626 }
396}
397
398/// T2I_picld - Defines the PIC load pattern.
399class T2I_picld<string opc, PatFrag opnode> :
400 T2I<(outs GPR:$dst), (ins addrmodepc:$addr), IIC_iLoadi,
401 !strconcat("\n${addr:label}:\n\t", opc), "\t$dst, $addr",
402 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
403
404/// T2I_picst - Defines the PIC store pattern.
405class T2I_picst<string opc, PatFrag opnode> :
406 T2I<(outs), (ins GPR:$src, addrmodepc:$addr), IIC_iStorer,
407 !strconcat("\n${addr:label}:\n\t", opc), "\t$src, $addr",
408 [(opnode GPR:$src, addrmodepc:$addr)]>;
409
410
411/// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
412/// register and one whose operand is a register rotated by 8/16/24.
627}
628
629/// T2I_picld - Defines the PIC load pattern.
630class T2I_picld<string opc, PatFrag opnode> :
631 T2I<(outs GPR:$dst), (ins addrmodepc:$addr), IIC_iLoadi,
632 !strconcat("\n${addr:label}:\n\t", opc), "\t$dst, $addr",
633 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
634
635/// T2I_picst - Defines the PIC store pattern.
636class T2I_picst<string opc, PatFrag opnode> :
637 T2I<(outs), (ins GPR:$src, addrmodepc:$addr), IIC_iStorer,
638 !strconcat("\n${addr:label}:\n\t", opc), "\t$src, $addr",
639 [(opnode GPR:$src, addrmodepc:$addr)]>;
640
641
642/// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
643/// register and one whose operand is a register rotated by 8/16/24.
413multiclass T2I_unary_rrot {
644multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
414 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
415 opc, ".w\t$dst, $src",
645 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
646 opc, ".w\t$dst, $src",
416 [(set GPR:$dst, (opnode GPR:$src))]>;
647 [(set GPR:$dst, (opnode GPR:$src))]> {
648 let Inst{31-27} = 0b11111;
649 let Inst{26-23} = 0b0100;
650 let Inst{22-20} = opcod;
651 let Inst{19-16} = 0b1111; // Rn
652 let Inst{15-12} = 0b1111;
653 let Inst{7} = 1;
654 let Inst{5-4} = 0b00; // rotate
655 }
417 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
418 opc, ".w\t$dst, $src, ror $rot",
656 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
657 opc, ".w\t$dst, $src, ror $rot",
419 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>;
658 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]> {
659 let Inst{31-27} = 0b11111;
660 let Inst{26-23} = 0b0100;
661 let Inst{22-20} = opcod;
662 let Inst{19-16} = 0b1111; // Rn
663 let Inst{15-12} = 0b1111;
664 let Inst{7} = 1;
665 let Inst{5-4} = {?,?}; // rotate
666 }
420}
421
422/// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
423/// register and one whose operand is a register rotated by 8/16/24.
667}
668
669/// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
670/// register and one whose operand is a register rotated by 8/16/24.
424multiclass T2I_bin_rrot {
671multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
425 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
426 opc, "\t$dst, $LHS, $RHS",
672 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
673 opc, "\t$dst, $LHS, $RHS",
427 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>;
674 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]> {
675 let Inst{31-27} = 0b11111;
676 let Inst{26-23} = 0b0100;
677 let Inst{22-20} = opcod;
678 let Inst{15-12} = 0b1111;
679 let Inst{7} = 1;
680 let Inst{5-4} = 0b00; // rotate
681 }
428 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
429 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
430 [(set GPR:$dst, (opnode GPR:$LHS,
682 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
683 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
684 [(set GPR:$dst, (opnode GPR:$LHS,
431 (rotr GPR:$RHS, rot_imm:$rot)))]>;
685 (rotr GPR:$RHS, rot_imm:$rot)))]> {
686 let Inst{31-27} = 0b11111;
687 let Inst{26-23} = 0b0100;
688 let Inst{22-20} = opcod;
689 let Inst{15-12} = 0b1111;
690 let Inst{7} = 1;
691 let Inst{5-4} = {?,?}; // rotate
692 }
432}
433
434//===----------------------------------------------------------------------===//
435// Instructions
436//===----------------------------------------------------------------------===//
437
438//===----------------------------------------------------------------------===//
439// Miscellaneous Instructions.
440//
441
442// LEApcrel - Load a pc-relative address into a register without offending the
443// assembler.
444def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
693}
694
695//===----------------------------------------------------------------------===//
696// Instructions
697//===----------------------------------------------------------------------===//
698
699//===----------------------------------------------------------------------===//
700// Miscellaneous Instructions.
701//
702
703// LEApcrel - Load a pc-relative address into a register without offending the
704// assembler.
705def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
445 "adr$p.w\t$dst, #$label", []>;
446
706 "adr$p.w\t$dst, #$label", []> {
707 let Inst{31-27} = 0b11110;
708 let Inst{25-24} = 0b10;
709 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
710 let Inst{22} = 0;
711 let Inst{20} = 0;
712 let Inst{19-16} = 0b1111; // Rn
713 let Inst{15} = 0;
714}
447def t2LEApcrelJT : T2XI<(outs GPR:$dst),
448 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
715def t2LEApcrelJT : T2XI<(outs GPR:$dst),
716 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
449 "adr$p.w\t$dst, #${label}_${id}", []>;
717 "adr$p.w\t$dst, #${label}_${id}", []> {
718 let Inst{31-27} = 0b11110;
719 let Inst{25-24} = 0b10;
720 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
721 let Inst{22} = 0;
722 let Inst{20} = 0;
723 let Inst{19-16} = 0b1111; // Rn
724 let Inst{15} = 0;
725}
450
451// ADD r, sp, {so_imm|i12}
452def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
726
727// ADD r, sp, {so_imm|i12}
728def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
453 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []>;
729 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
730 let Inst{31-27} = 0b11110;
731 let Inst{25} = 0;
732 let Inst{24-21} = 0b1000;
733 let Inst{20} = ?; // The S bit.
734 let Inst{19-16} = 0b1101; // Rn = sp
735 let Inst{15} = 0;
736}
454def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
737def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
455 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []>;
738 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
739 let Inst{31-27} = 0b11110;
740 let Inst{25} = 1;
741 let Inst{24-21} = 0b0000;
742 let Inst{20} = 0; // The S bit.
743 let Inst{19-16} = 0b1101; // Rn = sp
744 let Inst{15} = 0;
745}
456
457// ADD r, sp, so_reg
458def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
746
747// ADD r, sp, so_reg
748def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
459 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []>;
749 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
750 let Inst{31-27} = 0b11101;
751 let Inst{26-25} = 0b01;
752 let Inst{24-21} = 0b1000;
753 let Inst{20} = ?; // The S bit.
754 let Inst{19-16} = 0b1101; // Rn = sp
755 let Inst{15} = 0;
756}
460
461// SUB r, sp, {so_imm|i12}
462def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
757
758// SUB r, sp, {so_imm|i12}
759def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
463 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []>;
760 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
761 let Inst{31-27} = 0b11110;
762 let Inst{25} = 0;
763 let Inst{24-21} = 0b1101;
764 let Inst{20} = ?; // The S bit.
765 let Inst{19-16} = 0b1101; // Rn = sp
766 let Inst{15} = 0;
767}
464def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
768def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
465 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []>;
769 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
770 let Inst{31-27} = 0b11110;
771 let Inst{25} = 1;
772 let Inst{24-21} = 0b0101;
773 let Inst{20} = 0; // The S bit.
774 let Inst{19-16} = 0b1101; // Rn = sp
775 let Inst{15} = 0;
776}
466
467// SUB r, sp, so_reg
468def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
469 IIC_iALUsi,
777
778// SUB r, sp, so_reg
779def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
780 IIC_iALUsi,
470 "sub", "\t$dst, $sp, $rhs", []>;
781 "sub", "\t$dst, $sp, $rhs", []> {
782 let Inst{31-27} = 0b11101;
783 let Inst{26-25} = 0b01;
784 let Inst{24-21} = 0b1101;
785 let Inst{20} = ?; // The S bit.
786 let Inst{19-16} = 0b1101; // Rn = sp
787 let Inst{15} = 0;
788}
471
789
472
473// Pseudo instruction that will expand into a t2SUBrSPi + a copy.
474let usesCustomInserter = 1 in { // Expanded after instruction selection.
475def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
476 NoItinerary, "@ sub.w\t$dst, $sp, $imm", []>;
477def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
478 NoItinerary, "@ subw\t$dst, $sp, $imm", []>;
479def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
480 NoItinerary, "@ sub\t$dst, $sp, $rhs", []>;
481} // usesCustomInserter
482
483
484//===----------------------------------------------------------------------===//
485// Load / store Instructions.
486//
487
488// Load
489let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
790// Pseudo instruction that will expand into a t2SUBrSPi + a copy.
791let usesCustomInserter = 1 in { // Expanded after instruction selection.
792def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
793 NoItinerary, "@ sub.w\t$dst, $sp, $imm", []>;
794def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
795 NoItinerary, "@ subw\t$dst, $sp, $imm", []>;
796def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
797 NoItinerary, "@ sub\t$dst, $sp, $rhs", []>;
798} // usesCustomInserter
799
800
801//===----------------------------------------------------------------------===//
802// Load / store Instructions.
803//
804
805// Load
806let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
490defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
807defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>;
491
492// Loads with zero extension
808
809// Loads with zero extension
493defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
494defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
810defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
811defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
495
496// Loads with sign extension
812
813// Loads with sign extension
497defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
498defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
814defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
815defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
499
500let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
501// Load doubleword
816
817let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
818// Load doubleword
502def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst1, GPR:$dst2),
819def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
503 (ins t2addrmode_imm8s4:$addr),
504 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
820 (ins t2addrmode_imm8s4:$addr),
821 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
505def t2LDRDpci : T2Ii8s4<(outs GPR:$dst1, GPR:$dst2),
822def t2LDRDpci : T2Ii8s4<?, ?, 1, (outs GPR:$dst1, GPR:$dst2),
506 (ins i32imm:$addr), IIC_iLoadi,
823 (ins i32imm:$addr), IIC_iLoadi,
507 "ldrd", "\t$dst1, $addr", []>;
824 "ldrd", "\t$dst1, $addr", []> {
825 let Inst{19-16} = 0b1111; // Rn
508}
826}
827}
509
510// zextload i1 -> zextload i8
511def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
512 (t2LDRBi12 t2addrmode_imm12:$addr)>;
513def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
514 (t2LDRBi8 t2addrmode_imm8:$addr)>;
515def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
516 (t2LDRBs t2addrmode_so_reg:$addr)>;

--- 27 unchanged lines hidden (view full) ---

544 (t2LDRHi8 t2addrmode_imm8:$addr)>;
545def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
546 (t2LDRHs t2addrmode_so_reg:$addr)>;
547def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
548 (t2LDRHpci tconstpool:$addr)>;
549
550// Indexed loads
551let mayLoad = 1 in {
828
829// zextload i1 -> zextload i8
830def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
831 (t2LDRBi12 t2addrmode_imm12:$addr)>;
832def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
833 (t2LDRBi8 t2addrmode_imm8:$addr)>;
834def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
835 (t2LDRBs t2addrmode_so_reg:$addr)>;

--- 27 unchanged lines hidden (view full) ---

863 (t2LDRHi8 t2addrmode_imm8:$addr)>;
864def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
865 (t2LDRHs t2addrmode_so_reg:$addr)>;
866def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
867 (t2LDRHpci tconstpool:$addr)>;
868
869// Indexed loads
870let mayLoad = 1 in {
552def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
871def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
553 (ins t2addrmode_imm8:$addr),
554 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
555 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
556 []>;
557
872 (ins t2addrmode_imm8:$addr),
873 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
874 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
875 []>;
876
558def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
877def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
559 (ins GPR:$base, t2am_imm8_offset:$offset),
560 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
561 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
562 []>;
563
878 (ins GPR:$base, t2am_imm8_offset:$offset),
879 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
880 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
881 []>;
882
564def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
883def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
565 (ins t2addrmode_imm8:$addr),
566 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
567 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
568 []>;
884 (ins t2addrmode_imm8:$addr),
885 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
886 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
887 []>;
569def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
888def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
570 (ins GPR:$base, t2am_imm8_offset:$offset),
571 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
572 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
573 []>;
574
889 (ins GPR:$base, t2am_imm8_offset:$offset),
890 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
891 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
892 []>;
893
575def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
894def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
576 (ins t2addrmode_imm8:$addr),
577 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
578 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
579 []>;
895 (ins t2addrmode_imm8:$addr),
896 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
897 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
898 []>;
580def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
899def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
581 (ins GPR:$base, t2am_imm8_offset:$offset),
582 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
583 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
584 []>;
585
900 (ins GPR:$base, t2am_imm8_offset:$offset),
901 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
902 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
903 []>;
904
586def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
905def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
587 (ins t2addrmode_imm8:$addr),
588 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
589 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
590 []>;
906 (ins t2addrmode_imm8:$addr),
907 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
908 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
909 []>;
591def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
910def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
592 (ins GPR:$base, t2am_imm8_offset:$offset),
593 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
594 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
595 []>;
596
911 (ins GPR:$base, t2am_imm8_offset:$offset),
912 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
913 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
914 []>;
915
597def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
916def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
598 (ins t2addrmode_imm8:$addr),
599 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
600 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
601 []>;
917 (ins t2addrmode_imm8:$addr),
918 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
919 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
920 []>;
602def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
921def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
603 (ins GPR:$base, t2am_imm8_offset:$offset),
604 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
605 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
606 []>;
607}
608
609// Store
922 (ins GPR:$base, t2am_imm8_offset:$offset),
923 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
924 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
925 []>;
926}
927
928// Store
610defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
611defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
612defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
929defm t2STR : T2I_st<0b10, "str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
930defm t2STRB : T2I_st<0b00, "strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
931defm t2STRH : T2I_st<0b01, "strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
613
614// Store doubleword
615let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
932
933// Store doubleword
934let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
616def t2STRDi8 : T2Ii8s4<(outs),
935def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
617 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
618 IIC_iStorer, "strd", "\t$src1, $addr", []>;
619
620// Indexed stores
936 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
937 IIC_iStorer, "strd", "\t$src1, $addr", []>;
938
939// Indexed stores
621def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb),
940def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
622 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
623 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
624 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
625 [(set GPR:$base_wb,
626 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
627
941 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
942 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
943 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
944 [(set GPR:$base_wb,
945 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
946
628def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb),
947def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
629 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
630 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
631 "str", "\t$src, [$base], $offset", "$base = $base_wb",
632 [(set GPR:$base_wb,
633 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
634
948 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
949 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
950 "str", "\t$src, [$base], $offset", "$base = $base_wb",
951 [(set GPR:$base_wb,
952 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
953
635def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb),
954def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
636 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
637 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
638 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
639 [(set GPR:$base_wb,
640 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
641
955 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
956 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
957 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
958 [(set GPR:$base_wb,
959 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
960
642def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb),
961def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
643 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
644 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
645 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
646 [(set GPR:$base_wb,
647 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
648
962 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
963 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
964 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
965 [(set GPR:$base_wb,
966 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
967
649def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb),
968def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
650 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
651 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
652 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
653 [(set GPR:$base_wb,
654 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
655
969 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
970 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
971 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
972 [(set GPR:$base_wb,
973 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
974
656def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
975def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
657 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
658 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
659 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
660 [(set GPR:$base_wb,
661 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
662
663
664// FIXME: ldrd / strd pre / post variants
665
666//===----------------------------------------------------------------------===//
667// Load / store multiple Instructions.
668//
669
670let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
671def t2LDM : T2XI<(outs),
672 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
976 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
977 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
978 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
979 [(set GPR:$base_wb,
980 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
981
982
983// FIXME: ldrd / strd pre / post variants
984
985//===----------------------------------------------------------------------===//
986// Load / store multiple Instructions.
987//
988
989let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
990def t2LDM : T2XI<(outs),
991 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
673 IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb", []>;
992 IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
993 let Inst{31-27} = 0b11101;
994 let Inst{26-25} = 0b00;
995 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
996 let Inst{22} = 0;
997 let Inst{21} = ?; // The W bit.
998 let Inst{20} = 1; // Load
999}
674
675let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
676def t2STM : T2XI<(outs),
677 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1000
1001let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1002def t2STM : T2XI<(outs),
1003 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
678 IIC_iStorem, "stm${addr:submode}${p}${addr:wide}\t$addr, $wb", []>;
1004 IIC_iStorem, "stm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
1005 let Inst{31-27} = 0b11101;
1006 let Inst{26-25} = 0b00;
1007 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1008 let Inst{22} = 0;
1009 let Inst{21} = ?; // The W bit.
1010 let Inst{20} = 0; // Store
1011}
679
680//===----------------------------------------------------------------------===//
681// Move Instructions.
682//
683
684let neverHasSideEffects = 1 in
685def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1012
1013//===----------------------------------------------------------------------===//
1014// Move Instructions.
1015//
1016
1017let neverHasSideEffects = 1 in
1018def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
686 "mov", ".w\t$dst, $src", []>;
1019 "mov", ".w\t$dst, $src", []> {
1020 let Inst{31-27} = 0b11101;
1021 let Inst{26-25} = 0b01;
1022 let Inst{24-21} = 0b0010;
1023 let Inst{20} = ?; // The S bit.
1024 let Inst{19-16} = 0b1111; // Rn
1025 let Inst{14-12} = 0b000;
1026 let Inst{7-4} = 0b0000;
1027}
687
688// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
689let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
690def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
691 "mov", ".w\t$dst, $src",
1028
1029// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1030let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1031def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1032 "mov", ".w\t$dst, $src",
692 [(set GPR:$dst, t2_so_imm:$src)]>;
1033 [(set GPR:$dst, t2_so_imm:$src)]> {
1034 let Inst{31-27} = 0b11110;
1035 let Inst{25} = 0;
1036 let Inst{24-21} = 0b0010;
1037 let Inst{20} = ?; // The S bit.
1038 let Inst{19-16} = 0b1111; // Rn
1039 let Inst{15} = 0;
1040}
693
694let isReMaterializable = 1, isAsCheapAsAMove = 1 in
695def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
696 "movw", "\t$dst, $src",
1041
1042let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1043def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1044 "movw", "\t$dst, $src",
697 [(set GPR:$dst, imm0_65535:$src)]>;
1045 [(set GPR:$dst, imm0_65535:$src)]> {
1046 let Inst{31-27} = 0b11110;
1047 let Inst{25} = 1;
1048 let Inst{24-21} = 0b0010;
1049 let Inst{20} = 0; // The S bit.
1050 let Inst{15} = 0;
1051}
698
699let Constraints = "$src = $dst" in
700def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
701 "movt", "\t$dst, $imm",
702 [(set GPR:$dst,
1052
1053let Constraints = "$src = $dst" in
1054def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
1055 "movt", "\t$dst, $imm",
1056 [(set GPR:$dst,
703 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]>;
1057 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]> {
1058 let Inst{31-27} = 0b11110;
1059 let Inst{25} = 1;
1060 let Inst{24-21} = 0b0110;
1061 let Inst{20} = 0; // The S bit.
1062 let Inst{15} = 0;
1063}
704
705def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>;
706
707//===----------------------------------------------------------------------===//
708// Extend Instructions.
709//
710
711// Sign extenders
712
1064
1065def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>;
1066
1067//===----------------------------------------------------------------------===//
1068// Extend Instructions.
1069//
1070
1071// Sign extenders
1072
713defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
714defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1073defm t2SXTB : T2I_unary_rrot<0b100, "sxtb",
1074 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1075defm t2SXTH : T2I_unary_rrot<0b000, "sxth",
1076 UnOpFrag<(sext_inreg node:$Src, i16)>>;
715
1077
716defm t2SXTAB : T2I_bin_rrot<"sxtab",
1078defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab",
717 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1079 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
718defm t2SXTAH : T2I_bin_rrot<"sxtah",
1080defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah",
719 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
720
721// TODO: SXT(A){B|H}16
722
723// Zero extenders
724
725let AddedComplexity = 16 in {
1081 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1082
1083// TODO: SXT(A){B|H}16
1084
1085// Zero extenders
1086
1087let AddedComplexity = 16 in {
726defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
727defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
728defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1088defm t2UXTB : T2I_unary_rrot<0b101, "uxtb",
1089 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1090defm t2UXTH : T2I_unary_rrot<0b001, "uxth",
1091 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1092defm t2UXTB16 : T2I_unary_rrot<0b011, "uxtb16",
1093 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
729
730def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
731 (t2UXTB16r_rot GPR:$Src, 24)>;
732def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
733 (t2UXTB16r_rot GPR:$Src, 8)>;
734
1094
1095def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1096 (t2UXTB16r_rot GPR:$Src, 24)>;
1097def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1098 (t2UXTB16r_rot GPR:$Src, 8)>;
1099
735defm t2UXTAB : T2I_bin_rrot<"uxtab",
1100defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
736 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1101 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
737defm t2UXTAH : T2I_bin_rrot<"uxtah",
1102defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah",
738 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
739}
740
741//===----------------------------------------------------------------------===//
742// Arithmetic Instructions.
743//
744
1103 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1104}
1105
1106//===----------------------------------------------------------------------===//
1107// Arithmetic Instructions.
1108//
1109
745defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
746defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1110defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1111 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1112defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1113 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
747
748// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1114
1115// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
749defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
750defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1116defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1117 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1118defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1119 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
751
1120
752defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
753defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1121defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1122 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1123defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1124 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
754
755// RSB
1125
1126// RSB
756defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
757defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1127defm t2RSB : T2I_rbin_is <0b1110, "rsb",
1128 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1129defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1130 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
758
759// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
760let AddedComplexity = 1 in
761def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
762 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
763def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
764 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
765def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
766 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
767
768
769//===----------------------------------------------------------------------===//
770// Shift and rotate Instructions.
771//
772
1131
1132// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1133let AddedComplexity = 1 in
1134def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1135 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1136def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1137 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1138def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1139 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1140
1141
1142//===----------------------------------------------------------------------===//
1143// Shift and rotate Instructions.
1144//
1145
773defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
774defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
775defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
776defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1146defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1147defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1148defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1149defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
777
778let Uses = [CPSR] in {
779def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
780 "rrx", "\t$dst, $src",
1150
1151let Uses = [CPSR] in {
1152def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1153 "rrx", "\t$dst, $src",
781 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
1154 [(set GPR:$dst, (ARMrrx GPR:$src))]> {
1155 let Inst{31-27} = 0b11101;
1156 let Inst{26-25} = 0b01;
1157 let Inst{24-21} = 0b0010;
1158 let Inst{20} = ?; // The S bit.
1159 let Inst{19-16} = 0b1111; // Rn
1160 let Inst{14-12} = 0b000;
1161 let Inst{7-4} = 0b0011;
782}
1162}
1163}
783
784let Defs = [CPSR] in {
785def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
786 "lsrs.w\t$dst, $src, #1",
1164
1165let Defs = [CPSR] in {
1166def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1167 "lsrs.w\t$dst, $src, #1",
787 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
1168 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]> {
1169 let Inst{31-27} = 0b11101;
1170 let Inst{26-25} = 0b01;
1171 let Inst{24-21} = 0b0010;
1172 let Inst{20} = 1; // The S bit.
1173 let Inst{19-16} = 0b1111; // Rn
1174 let Inst{5-4} = 0b01; // Shift type.
1175 // Shift amount = Inst{14-12:7-6} = 1.
1176 let Inst{14-12} = 0b000;
1177 let Inst{7-6} = 0b01;
1178}
788def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
789 "asrs.w\t$dst, $src, #1",
1179def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1180 "asrs.w\t$dst, $src, #1",
790 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
1181 [(set GPR:$dst, (ARMsra_flag GPR:$src))]> {
1182 let Inst{31-27} = 0b11101;
1183 let Inst{26-25} = 0b01;
1184 let Inst{24-21} = 0b0010;
1185 let Inst{20} = 1; // The S bit.
1186 let Inst{19-16} = 0b1111; // Rn
1187 let Inst{5-4} = 0b10; // Shift type.
1188 // Shift amount = Inst{14-12:7-6} = 1.
1189 let Inst{14-12} = 0b000;
1190 let Inst{7-6} = 0b01;
791}
1191}
1192}
792
793//===----------------------------------------------------------------------===//
794// Bitwise Instructions.
795//
796
1193
1194//===----------------------------------------------------------------------===//
1195// Bitwise Instructions.
1196//
1197
797defm t2AND : T2I_bin_w_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
798defm t2ORR : T2I_bin_w_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
799defm t2EOR : T2I_bin_w_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1198defm t2AND : T2I_bin_w_irs<0b0000, "and",
1199 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1200defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1201 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1202defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1203 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
800
1204
801defm t2BIC : T2I_bin_w_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1205defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1206 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
802
803let Constraints = "$src = $dst" in
804def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
805 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1207
1208let Constraints = "$src = $dst" in
1209def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1210 IIC_iUNAsi, "bfc", "\t$dst, $imm",
806 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
1211 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]> {
1212 let Inst{31-27} = 0b11110;
1213 let Inst{25} = 1;
1214 let Inst{24-20} = 0b10110;
1215 let Inst{19-16} = 0b1111; // Rn
1216 let Inst{15} = 0;
1217}
807
808def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1218
1219def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
809 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []>;
1220 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1221 let Inst{31-27} = 0b11110;
1222 let Inst{25} = 1;
1223 let Inst{24-20} = 0b10100;
1224 let Inst{15} = 0;
1225}
810
811def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1226
1227def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
812 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []>;
1228 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1229 let Inst{31-27} = 0b11110;
1230 let Inst{25} = 1;
1231 let Inst{24-20} = 0b11100;
1232 let Inst{15} = 0;
1233}
813
814// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
815
1234
1235// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
1236
816defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
1237defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS,
1238 (not node:$RHS))>>;
817
818// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
819let AddedComplexity = 1 in
1239
1240// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1241let AddedComplexity = 1 in
820defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
1242defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
821
822
823def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
824 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
825
826// FIXME: Disable this pattern on Darwin to workaround an assembler bug.
827def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
828 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
829 Requires<[IsThumb2]>;
830
831def : T2Pat<(t2_so_imm_not:$src),
832 (t2MVNi t2_so_imm_not:$src)>;
833
834//===----------------------------------------------------------------------===//
835// Multiply Instructions.
836//
837let isCommutable = 1 in
838def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
839 "mul", "\t$dst, $a, $b",
1243
1244
1245def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
1246 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
1247
1248// FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1249def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
1250 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
1251 Requires<[IsThumb2]>;
1252
1253def : T2Pat<(t2_so_imm_not:$src),
1254 (t2MVNi t2_so_imm_not:$src)>;
1255
1256//===----------------------------------------------------------------------===//
1257// Multiply Instructions.
1258//
1259let isCommutable = 1 in
1260def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1261 "mul", "\t$dst, $a, $b",
840 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1262 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]> {
1263 let Inst{31-27} = 0b11111;
1264 let Inst{26-23} = 0b0110;
1265 let Inst{22-20} = 0b000;
1266 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1267 let Inst{7-4} = 0b0000; // Multiply
1268}
841
842def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
843 "mla", "\t$dst, $a, $b, $c",
1269
1270def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1271 "mla", "\t$dst, $a, $b, $c",
844 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1272 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]> {
1273 let Inst{31-27} = 0b11111;
1274 let Inst{26-23} = 0b0110;
1275 let Inst{22-20} = 0b000;
1276 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1277 let Inst{7-4} = 0b0000; // Multiply
1278}
845
846def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
847 "mls", "\t$dst, $a, $b, $c",
1279
1280def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1281 "mls", "\t$dst, $a, $b, $c",
848 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
1282 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]> {
1283 let Inst{31-27} = 0b11111;
1284 let Inst{26-23} = 0b0110;
1285 let Inst{22-20} = 0b000;
1286 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1287 let Inst{7-4} = 0b0001; // Multiply and Subtract
1288}
849
850// Extra precision multiplies with low / high results
851let neverHasSideEffects = 1 in {
852let isCommutable = 1 in {
853def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1289
1290// Extra precision multiplies with low / high results
1291let neverHasSideEffects = 1 in {
1292let isCommutable = 1 in {
1293def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
854 "smull", "\t$ldst, $hdst, $a, $b", []>;
1294 "smull", "\t$ldst, $hdst, $a, $b", []> {
1295 let Inst{31-27} = 0b11111;
1296 let Inst{26-23} = 0b0111;
1297 let Inst{22-20} = 0b000;
1298 let Inst{7-4} = 0b0000;
1299}
855
856def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1300
1301def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
857 "umull", "\t$ldst, $hdst, $a, $b", []>;
1302 "umull", "\t$ldst, $hdst, $a, $b", []> {
1303 let Inst{31-27} = 0b11111;
1304 let Inst{26-23} = 0b0111;
1305 let Inst{22-20} = 0b010;
1306 let Inst{7-4} = 0b0000;
858}
1307}
1308} // isCommutable
859
860// Multiply + accumulate
861def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1309
1310// Multiply + accumulate
1311def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
862 "smlal", "\t$ldst, $hdst, $a, $b", []>;
1312 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1313 let Inst{31-27} = 0b11111;
1314 let Inst{26-23} = 0b0111;
1315 let Inst{22-20} = 0b100;
1316 let Inst{7-4} = 0b0000;
1317}
863
864def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1318
1319def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
865 "umlal", "\t$ldst, $hdst, $a, $b", []>;
1320 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1321 let Inst{31-27} = 0b11111;
1322 let Inst{26-23} = 0b0111;
1323 let Inst{22-20} = 0b110;
1324 let Inst{7-4} = 0b0000;
1325}
866
867def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1326
1327def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
868 "umaal", "\t$ldst, $hdst, $a, $b", []>;
1328 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1329 let Inst{31-27} = 0b11111;
1330 let Inst{26-23} = 0b0111;
1331 let Inst{22-20} = 0b110;
1332 let Inst{7-4} = 0b0110;
1333}
869} // neverHasSideEffects
870
871// Most significant word multiply
872def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
873 "smmul", "\t$dst, $a, $b",
1334} // neverHasSideEffects
1335
1336// Most significant word multiply
1337def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1338 "smmul", "\t$dst, $a, $b",
874 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>;
1339 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]> {
1340 let Inst{31-27} = 0b11111;
1341 let Inst{26-23} = 0b0110;
1342 let Inst{22-20} = 0b101;
1343 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1344 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1345}
875
876def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
877 "smmla", "\t$dst, $a, $b, $c",
1346
1347def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1348 "smmla", "\t$dst, $a, $b, $c",
878 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>;
1349 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]> {
1350 let Inst{31-27} = 0b11111;
1351 let Inst{26-23} = 0b0110;
1352 let Inst{22-20} = 0b101;
1353 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1354 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1355}
879
880
881def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
882 "smmls", "\t$dst, $a, $b, $c",
1356
1357
1358def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1359 "smmls", "\t$dst, $a, $b, $c",
883 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>;
1360 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]> {
1361 let Inst{31-27} = 0b11111;
1362 let Inst{26-23} = 0b0110;
1363 let Inst{22-20} = 0b110;
1364 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1365 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1366}
884
885multiclass T2I_smul<string opc, PatFrag opnode> {
886 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
887 !strconcat(opc, "bb"), "\t$dst, $a, $b",
888 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1367
1368multiclass T2I_smul<string opc, PatFrag opnode> {
1369 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1370 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1371 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
889 (sext_inreg GPR:$b, i16)))]>;
1372 (sext_inreg GPR:$b, i16)))]> {
1373 let Inst{31-27} = 0b11111;
1374 let Inst{26-23} = 0b0110;
1375 let Inst{22-20} = 0b001;
1376 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1377 let Inst{7-6} = 0b00;
1378 let Inst{5-4} = 0b00;
1379 }
890
891 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
892 !strconcat(opc, "bt"), "\t$dst, $a, $b",
893 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1380
1381 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1382 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1383 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
894 (sra GPR:$b, (i32 16))))]>;
1384 (sra GPR:$b, (i32 16))))]> {
1385 let Inst{31-27} = 0b11111;
1386 let Inst{26-23} = 0b0110;
1387 let Inst{22-20} = 0b001;
1388 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1389 let Inst{7-6} = 0b00;
1390 let Inst{5-4} = 0b01;
1391 }
895
896 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
897 !strconcat(opc, "tb"), "\t$dst, $a, $b",
898 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1392
1393 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1394 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1395 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
899 (sext_inreg GPR:$b, i16)))]>;
1396 (sext_inreg GPR:$b, i16)))]> {
1397 let Inst{31-27} = 0b11111;
1398 let Inst{26-23} = 0b0110;
1399 let Inst{22-20} = 0b001;
1400 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1401 let Inst{7-6} = 0b00;
1402 let Inst{5-4} = 0b10;
1403 }
900
901 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
902 !strconcat(opc, "tt"), "\t$dst, $a, $b",
903 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1404
1405 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1406 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1407 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
904 (sra GPR:$b, (i32 16))))]>;
1408 (sra GPR:$b, (i32 16))))]> {
1409 let Inst{31-27} = 0b11111;
1410 let Inst{26-23} = 0b0110;
1411 let Inst{22-20} = 0b001;
1412 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1413 let Inst{7-6} = 0b00;
1414 let Inst{5-4} = 0b11;
1415 }
905
906 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
907 !strconcat(opc, "wb"), "\t$dst, $a, $b",
908 [(set GPR:$dst, (sra (opnode GPR:$a,
1416
1417 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1418 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1419 [(set GPR:$dst, (sra (opnode GPR:$a,
909 (sext_inreg GPR:$b, i16)), (i32 16)))]>;
1420 (sext_inreg GPR:$b, i16)), (i32 16)))]> {
1421 let Inst{31-27} = 0b11111;
1422 let Inst{26-23} = 0b0110;
1423 let Inst{22-20} = 0b011;
1424 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1425 let Inst{7-6} = 0b00;
1426 let Inst{5-4} = 0b00;
1427 }
910
911 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
912 !strconcat(opc, "wt"), "\t$dst, $a, $b",
913 [(set GPR:$dst, (sra (opnode GPR:$a,
1428
1429 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1430 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1431 [(set GPR:$dst, (sra (opnode GPR:$a,
914 (sra GPR:$b, (i32 16))), (i32 16)))]>;
1432 (sra GPR:$b, (i32 16))), (i32 16)))]> {
1433 let Inst{31-27} = 0b11111;
1434 let Inst{26-23} = 0b0110;
1435 let Inst{22-20} = 0b011;
1436 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1437 let Inst{7-6} = 0b00;
1438 let Inst{5-4} = 0b01;
1439 }
915}
916
917
918multiclass T2I_smla<string opc, PatFrag opnode> {
919 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
920 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
921 [(set GPR:$dst, (add GPR:$acc,
922 (opnode (sext_inreg GPR:$a, i16),
1440}
1441
1442
1443multiclass T2I_smla<string opc, PatFrag opnode> {
1444 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1445 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1446 [(set GPR:$dst, (add GPR:$acc,
1447 (opnode (sext_inreg GPR:$a, i16),
923 (sext_inreg GPR:$b, i16))))]>;
1448 (sext_inreg GPR:$b, i16))))]> {
1449 let Inst{31-27} = 0b11111;
1450 let Inst{26-23} = 0b0110;
1451 let Inst{22-20} = 0b001;
1452 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1453 let Inst{7-6} = 0b00;
1454 let Inst{5-4} = 0b00;
1455 }
924
925 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
926 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
927 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1456
1457 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1458 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1459 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
928 (sra GPR:$b, (i32 16)))))]>;
1460 (sra GPR:$b, (i32 16)))))]> {
1461 let Inst{31-27} = 0b11111;
1462 let Inst{26-23} = 0b0110;
1463 let Inst{22-20} = 0b001;
1464 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1465 let Inst{7-6} = 0b00;
1466 let Inst{5-4} = 0b01;
1467 }
929
930 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
931 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
932 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1468
1469 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1470 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1471 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
933 (sext_inreg GPR:$b, i16))))]>;
1472 (sext_inreg GPR:$b, i16))))]> {
1473 let Inst{31-27} = 0b11111;
1474 let Inst{26-23} = 0b0110;
1475 let Inst{22-20} = 0b001;
1476 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1477 let Inst{7-6} = 0b00;
1478 let Inst{5-4} = 0b10;
1479 }
934
935 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
936 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
937 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1480
1481 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1482 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1483 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
938 (sra GPR:$b, (i32 16)))))]>;
1484 (sra GPR:$b, (i32 16)))))]> {
1485 let Inst{31-27} = 0b11111;
1486 let Inst{26-23} = 0b0110;
1487 let Inst{22-20} = 0b001;
1488 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1489 let Inst{7-6} = 0b00;
1490 let Inst{5-4} = 0b11;
1491 }
939
940 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
941 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
942 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1492
1493 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1494 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1495 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
943 (sext_inreg GPR:$b, i16)), (i32 16))))]>;
1496 (sext_inreg GPR:$b, i16)), (i32 16))))]> {
1497 let Inst{31-27} = 0b11111;
1498 let Inst{26-23} = 0b0110;
1499 let Inst{22-20} = 0b011;
1500 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1501 let Inst{7-6} = 0b00;
1502 let Inst{5-4} = 0b00;
1503 }
944
945 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
946 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
947 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1504
1505 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1506 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1507 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
948 (sra GPR:$b, (i32 16))), (i32 16))))]>;
1508 (sra GPR:$b, (i32 16))), (i32 16))))]> {
1509 let Inst{31-27} = 0b11111;
1510 let Inst{26-23} = 0b0110;
1511 let Inst{22-20} = 0b011;
1512 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1513 let Inst{7-6} = 0b00;
1514 let Inst{5-4} = 0b01;
1515 }
949}
950
951defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
952defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
953
954// TODO: Halfword multiple accumulate long: SMLAL<x><y>
955// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
956
957
958//===----------------------------------------------------------------------===//
959// Misc. Arithmetic Instructions.
960//
961
1516}
1517
1518defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1519defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1520
1521// TODO: Halfword multiple accumulate long: SMLAL<x><y>
1522// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1523
1524
1525//===----------------------------------------------------------------------===//
1526// Misc. Arithmetic Instructions.
1527//
1528
962def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
963 "clz", "\t$dst, $src",
964 [(set GPR:$dst, (ctlz GPR:$src))]>;
1529class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops, InstrItinClass itin,
1530 string opc, string asm, list<dag> pattern>
1531 : T2I<oops, iops, itin, opc, asm, pattern> {
1532 let Inst{31-27} = 0b11111;
1533 let Inst{26-22} = 0b01010;
1534 let Inst{21-20} = op1;
1535 let Inst{15-12} = 0b1111;
1536 let Inst{7-6} = 0b10;
1537 let Inst{5-4} = op2;
1538}
965
1539
966def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
967 "rev", ".w\t$dst, $src",
968 [(set GPR:$dst, (bswap GPR:$src))]>;
1540def t2CLZ : T2I_misc<0b11, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1541 "clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>;
969
1542
970def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
971 "rev16", ".w\t$dst, $src",
1543def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1544 "rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>;
1545
1546def t2REV16 : T2I_misc<0b01, 0b01, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1547 "rev16", ".w\t$dst, $src",
972 [(set GPR:$dst,
973 (or (and (srl GPR:$src, (i32 8)), 0xFF),
974 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
975 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
976 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
977
1548 [(set GPR:$dst,
1549 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1550 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1551 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1552 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
1553
978def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
979 "revsh", ".w\t$dst, $src",
1554def t2REVSH : T2I_misc<0b01, 0b11, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1555 "revsh", ".w\t$dst, $src",
980 [(set GPR:$dst,
981 (sext_inreg
982 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
983 (shl GPR:$src, (i32 8))), i16))]>;
984
985def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
986 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
987 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
988 (and (shl GPR:$src2, (i32 imm:$shamt)),
1556 [(set GPR:$dst,
1557 (sext_inreg
1558 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1559 (shl GPR:$src, (i32 8))), i16))]>;
1560
1561def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1562 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
1563 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1564 (and (shl GPR:$src2, (i32 imm:$shamt)),
989 0xFFFF0000)))]>;
1565 0xFFFF0000)))]> {
1566 let Inst{31-27} = 0b11101;
1567 let Inst{26-25} = 0b01;
1568 let Inst{24-20} = 0b01100;
1569 let Inst{5} = 0; // BT form
1570 let Inst{4} = 0;
1571}
990
991// Alternate cases for PKHBT where identities eliminate some nodes.
992def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
993 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
994def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
995 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
996
997def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
998 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
999 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1000 (and (sra GPR:$src2, imm16_31:$shamt),
1572
1573// Alternate cases for PKHBT where identities eliminate some nodes.
1574def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1575 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
1576def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1577 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1578
1579def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1580 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
1581 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1582 (and (sra GPR:$src2, imm16_31:$shamt),
1001 0xFFFF)))]>;
1583 0xFFFF)))]> {
1584 let Inst{31-27} = 0b11101;
1585 let Inst{26-25} = 0b01;
1586 let Inst{24-20} = 0b01100;
1587 let Inst{5} = 1; // TB form
1588 let Inst{4} = 0;
1589}
1002
1003// Alternate cases for PKHTB where identities eliminate some nodes. Note that
1004// a shift amount of 0 is *not legal* here, it is PKHBT instead.
1005def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1006 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
1007def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
1008 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1009 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1010
1011//===----------------------------------------------------------------------===//
1012// Comparison Instructions...
1013//
1014
1590
1591// Alternate cases for PKHTB where identities eliminate some nodes. Note that
1592// a shift amount of 0 is *not legal* here, it is PKHBT instead.
1593def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1594 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
1595def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
1596 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1597 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1598
1599//===----------------------------------------------------------------------===//
1600// Comparison Instructions...
1601//
1602
1015defm t2CMP : T2I_cmp_is<"cmp",
1016 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1017defm t2CMPz : T2I_cmp_is<"cmp",
1018 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1603defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
1604 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1605defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
1606 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1019
1607
1020defm t2CMN : T2I_cmp_is<"cmn",
1021 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1022defm t2CMNz : T2I_cmp_is<"cmn",
1023 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1608defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
1609 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1610defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
1611 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1024
1025def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
1026 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1027
1028def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
1029 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1030
1612
1613def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
1614 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1615
1616def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
1617 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1618
1031defm t2TST : T2I_cmp_is<"tst",
1032 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
1033defm t2TEQ : T2I_cmp_is<"teq",
1034 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
1619defm t2TST : T2I_cmp_irs<0b0000, "tst",
1620 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
1621defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
1622 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
1035
1036// A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
1037// Short range conditional branch. Looks awesome for loops. Need to figure
1038// out how to use this one.
1039
1040
1041// Conditional moves
1042// FIXME: should be able to write a pattern for ARMcmov, but can't use
1043// a two-value operand where a dag node expects two operands. :(
1044def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr,
1045 "mov", ".w\t$dst, $true",
1046 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1623
1624// A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
1625// Short range conditional branch. Looks awesome for loops. Need to figure
1626// out how to use this one.
1627
1628
1629// Conditional moves
1630// FIXME: should be able to write a pattern for ARMcmov, but can't use
1631// a two-value operand where a dag node expects two operands. :(
1632def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr,
1633 "mov", ".w\t$dst, $true",
1634 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1047 RegConstraint<"$false = $dst">;
1635 RegConstraint<"$false = $dst"> {
1636 let Inst{31-27} = 0b11101;
1637 let Inst{26-25} = 0b01;
1638 let Inst{24-21} = 0b0010;
1639 let Inst{20} = 0; // The S bit.
1640 let Inst{19-16} = 0b1111; // Rn
1641 let Inst{14-12} = 0b000;
1642 let Inst{7-4} = 0b0000;
1643}
1048
1049def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
1050 IIC_iCMOVi, "mov", ".w\t$dst, $true",
1051[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1644
1645def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
1646 IIC_iCMOVi, "mov", ".w\t$dst, $true",
1647[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1052 RegConstraint<"$false = $dst">;
1648 RegConstraint<"$false = $dst"> {
1649 let Inst{31-27} = 0b11110;
1650 let Inst{25} = 0;
1651 let Inst{24-21} = 0b0010;
1652 let Inst{20} = 0; // The S bit.
1653 let Inst{19-16} = 0b1111; // Rn
1654 let Inst{15} = 0;
1655}
1053
1656
1054def t2MOVCClsl : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1055 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
1056 RegConstraint<"$false = $dst">;
1057def t2MOVCClsr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1058 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
1059 RegConstraint<"$false = $dst">;
1060def t2MOVCCasr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1061 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
1062 RegConstraint<"$false = $dst">;
1063def t2MOVCCror : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1064 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
1065 RegConstraint<"$false = $dst">;
1657class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
1658 string opc, string asm, list<dag> pattern>
1659 : T2I<oops, iops, itin, opc, asm, pattern> {
1660 let Inst{31-27} = 0b11101;
1661 let Inst{26-25} = 0b01;
1662 let Inst{24-21} = 0b0010;
1663 let Inst{20} = 0; // The S bit.
1664 let Inst{19-16} = 0b1111; // Rn
1665 let Inst{5-4} = opcod; // Shift type.
1666}
1667def t2MOVCClsl : T2I_movcc_sh<0b00, (outs GPR:$dst),
1668 (ins GPR:$false, GPR:$true, i32imm:$rhs),
1669 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
1670 RegConstraint<"$false = $dst">;
1671def t2MOVCClsr : T2I_movcc_sh<0b01, (outs GPR:$dst),
1672 (ins GPR:$false, GPR:$true, i32imm:$rhs),
1673 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
1674 RegConstraint<"$false = $dst">;
1675def t2MOVCCasr : T2I_movcc_sh<0b10, (outs GPR:$dst),
1676 (ins GPR:$false, GPR:$true, i32imm:$rhs),
1677 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
1678 RegConstraint<"$false = $dst">;
1679def t2MOVCCror : T2I_movcc_sh<0b11, (outs GPR:$dst),
1680 (ins GPR:$false, GPR:$true, i32imm:$rhs),
1681 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
1682 RegConstraint<"$false = $dst">;
1066
1067//===----------------------------------------------------------------------===//
1068// Atomic operations intrinsics
1069//
1070
1071// memory barriers protect the atomic sequences
1072let hasSideEffects = 1 in {
1073def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
1074 Pseudo, NoItinerary,
1075 "dmb", "",
1076 [(ARMMemBarrierV7)]>,
1077 Requires<[IsThumb2]> {
1683
1684//===----------------------------------------------------------------------===//
1685// Atomic operations intrinsics
1686//
1687
1688// memory barriers protect the atomic sequences
1689let hasSideEffects = 1 in {
1690def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
1691 Pseudo, NoItinerary,
1692 "dmb", "",
1693 [(ARMMemBarrierV7)]>,
1694 Requires<[IsThumb2]> {
1695 let Inst{31-4} = 0xF3BF8F5;
1078 // FIXME: add support for options other than a full system DMB
1696 // FIXME: add support for options other than a full system DMB
1697 let Inst{3-0} = 0b1111;
1079}
1080
1081def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
1082 Pseudo, NoItinerary,
1083 "dsb", "",
1084 [(ARMSyncBarrierV7)]>,
1085 Requires<[IsThumb2]> {
1698}
1699
1700def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
1701 Pseudo, NoItinerary,
1702 "dsb", "",
1703 [(ARMSyncBarrierV7)]>,
1704 Requires<[IsThumb2]> {
1705 let Inst{31-4} = 0xF3BF8F4;
1086 // FIXME: add support for options other than a full system DSB
1706 // FIXME: add support for options other than a full system DSB
1707 let Inst{3-0} = 0b1111;
1087}
1088}
1089
1708}
1709}
1710
1711class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1712 InstrItinClass itin, string opc, string asm, string cstr,
1713 list<dag> pattern, bits<4> rt2 = 0b1111>
1714 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
1715 let Inst{31-27} = 0b11101;
1716 let Inst{26-20} = 0b0001101;
1717 let Inst{11-8} = rt2;
1718 let Inst{7-6} = 0b01;
1719 let Inst{5-4} = opcod;
1720 let Inst{3-0} = 0b1111;
1721}
1722class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1723 InstrItinClass itin, string opc, string asm, string cstr,
1724 list<dag> pattern, bits<4> rt2 = 0b1111>
1725 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
1726 let Inst{31-27} = 0b11101;
1727 let Inst{26-20} = 0b0001100;
1728 let Inst{11-8} = rt2;
1729 let Inst{7-6} = 0b01;
1730 let Inst{5-4} = opcod;
1731}
1732
1090let mayLoad = 1 in {
1733let mayLoad = 1 in {
1091def t2LDREXB : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
1092 Size4Bytes, NoItinerary,
1093 "ldrexb", "\t$dest, [$ptr]", "",
1094 []>;
1095def t2LDREXH : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
1096 Size4Bytes, NoItinerary,
1097 "ldrexh", "\t$dest, [$ptr]", "",
1098 []>;
1734def t2LDREXB : T2I_ldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
1735 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
1736 "", []>;
1737def t2LDREXH : T2I_ldrex<0b01, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
1738 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
1739 "", []>;
1099def t2LDREX : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
1740def t2LDREX : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
1100 Size4Bytes, NoItinerary,
1101 "ldrex", "\t$dest, [$ptr]", "",
1102 []>;
1103def t2LDREXD : Thumb2I<(outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
1104 AddrModeNone, Size4Bytes, NoItinerary,
1105 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
1106 []>;
1741 Size4Bytes, NoItinerary,
1742 "ldrex", "\t$dest, [$ptr]", "",
1743 []> {
1744 let Inst{31-27} = 0b11101;
1745 let Inst{26-20} = 0b0000101;
1746 let Inst{11-8} = 0b1111;
1747 let Inst{7-0} = 0b00000000; // imm8 = 0
1107}
1748}
1749def t2LDREXD : T2I_ldrex<0b11, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
1750 AddrModeNone, Size4Bytes, NoItinerary,
1751 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
1752 [], {?, ?, ?, ?}>;
1753}
1108
1754
1109let mayStore = 1 in {
1110def t2STREXB : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr),
1111 AddrModeNone, Size4Bytes, NoItinerary,
1112 "strexb", "\t$success, $src, [$ptr]", "",
1113 []>;
1114def t2STREXH : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr),
1115 AddrModeNone, Size4Bytes, NoItinerary,
1116 "strexh", "\t$success, $src, [$ptr]", "",
1117 []>;
1755let mayStore = 1, Constraints = "@earlyclobber $success" in {
1756def t2STREXB : T2I_strex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
1757 AddrModeNone, Size4Bytes, NoItinerary,
1758 "strexb", "\t$success, $src, [$ptr]", "", []>;
1759def t2STREXH : T2I_strex<0b01, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
1760 AddrModeNone, Size4Bytes, NoItinerary,
1761 "strexh", "\t$success, $src, [$ptr]", "", []>;
1118def t2STREX : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr),
1762def t2STREX : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr),
1119 AddrModeNone, Size4Bytes, NoItinerary,
1120 "strex", "\t$success, $src, [$ptr]", "",
1121 []>;
1122def t2STREXD : Thumb2I<(outs GPR:$success),
1123 (ins GPR:$src, GPR:$src2, GPR:$ptr),
1124 AddrModeNone, Size4Bytes, NoItinerary,
1125 "strexd", "\t$success, $src, $src2, [$ptr]", "",
1126 []>;
1763 AddrModeNone, Size4Bytes, NoItinerary,
1764 "strex", "\t$success, $src, [$ptr]", "",
1765 []> {
1766 let Inst{31-27} = 0b11101;
1767 let Inst{26-20} = 0b0000100;
1768 let Inst{7-0} = 0b00000000; // imm8 = 0
1127}
1769}
1770def t2STREXD : T2I_strex<0b11, (outs GPR:$success),
1771 (ins GPR:$src, GPR:$src2, GPR:$ptr),
1772 AddrModeNone, Size4Bytes, NoItinerary,
1773 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
1774 {?, ?, ?, ?}>;
1775}
1128
1129//===----------------------------------------------------------------------===//
1130// TLS Instructions
1131//
1132
1133// __aeabi_read_tp preserves the registers r1-r3.
1134let isCall = 1,
1135 Defs = [R0, R12, LR, CPSR] in {
1136 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
1137 "bl\t__aeabi_read_tp",
1776
1777//===----------------------------------------------------------------------===//
1778// TLS Instructions
1779//
1780
1781// __aeabi_read_tp preserves the registers r1-r3.
1782let isCall = 1,
1783 Defs = [R0, R12, LR, CPSR] in {
1784 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
1785 "bl\t__aeabi_read_tp",
1138 [(set R0, ARMthread_pointer)]>;
1786 [(set R0, ARMthread_pointer)]> {
1787 let Inst{31-27} = 0b11110;
1788 let Inst{15-14} = 0b11;
1789 let Inst{12} = 1;
1790 }
1139}
1140
1141//===----------------------------------------------------------------------===//
1142// SJLJ Exception handling intrinsics
1143// eh_sjlj_setjmp() is an instruction sequence to store the return
1144// address and save #0 in R0 for the non-longjmp case.
1145// Since by its nature we may be coming from some other function to get
1146// here, and we're using the stack frame for the containing function to

--- 31 unchanged lines hidden (view full) ---

1178// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
1179// operand list.
1180// FIXME: Should pc be an implicit operand like PICADD, etc?
1181let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1182 hasExtraDefRegAllocReq = 1 in
1183 def t2LDM_RET : T2XI<(outs),
1184 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1185 IIC_Br, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb",
1791}
1792
1793//===----------------------------------------------------------------------===//
1794// SJLJ Exception handling intrinsics
1795// eh_sjlj_setjmp() is an instruction sequence to store the return
1796// address and save #0 in R0 for the non-longjmp case.
1797// Since by its nature we may be coming from some other function to get
1798// here, and we're using the stack frame for the containing function to

--- 31 unchanged lines hidden (view full) ---

1830// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
1831// operand list.
1832// FIXME: Should pc be an implicit operand like PICADD, etc?
1833let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1834 hasExtraDefRegAllocReq = 1 in
1835 def t2LDM_RET : T2XI<(outs),
1836 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1837 IIC_Br, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb",
1186 []>;
1838 []> {
1839 let Inst{31-27} = 0b11101;
1840 let Inst{26-25} = 0b00;
1841 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1842 let Inst{22} = 0;
1843 let Inst{21} = ?; // The W bit.
1844 let Inst{20} = 1; // Load
1845}
1187
1188let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1189let isPredicable = 1 in
1190def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
1191 "b.w\t$target",
1846
1847let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1848let isPredicable = 1 in
1849def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
1850 "b.w\t$target",
1192 [(br bb:$target)]>;
1851 [(br bb:$target)]> {
1852 let Inst{31-27} = 0b11110;
1853 let Inst{15-14} = 0b10;
1854 let Inst{12} = 1;
1855}
1193
1194let isNotDuplicable = 1, isIndirectBranch = 1 in {
1195def t2BR_JT :
1196 T2JTI<(outs),
1197 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
1198 IIC_Br, "mov\tpc, $target\n$jt",
1856
1857let isNotDuplicable = 1, isIndirectBranch = 1 in {
1858def t2BR_JT :
1859 T2JTI<(outs),
1860 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
1861 IIC_Br, "mov\tpc, $target\n$jt",
1199 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
1862 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
1863 let Inst{31-27} = 0b11101;
1864 let Inst{26-20} = 0b0100100;
1865 let Inst{19-16} = 0b1111;
1866 let Inst{14-12} = 0b000;
1867 let Inst{11-8} = 0b1111; // Rd = pc
1868 let Inst{7-4} = 0b0000;
1869}
1200
1201// FIXME: Add a non-pc based case that can be predicated.
1202def t2TBB :
1203 T2JTI<(outs),
1204 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
1870
1871// FIXME: Add a non-pc based case that can be predicated.
1872def t2TBB :
1873 T2JTI<(outs),
1874 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
1205 IIC_Br, "tbb\t$index\n$jt", []>;
1875 IIC_Br, "tbb\t$index\n$jt", []> {
1876 let Inst{31-27} = 0b11101;
1877 let Inst{26-20} = 0b0001101;
1878 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
1879 let Inst{15-8} = 0b11110000;
1880 let Inst{7-4} = 0b0000; // B form
1881}
1206
1207def t2TBH :
1208 T2JTI<(outs),
1209 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
1882
1883def t2TBH :
1884 T2JTI<(outs),
1885 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
1210 IIC_Br, "tbh\t$index\n$jt", []>;
1886 IIC_Br, "tbh\t$index\n$jt", []> {
1887 let Inst{31-27} = 0b11101;
1888 let Inst{26-20} = 0b0001101;
1889 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
1890 let Inst{15-8} = 0b11110000;
1891 let Inst{7-4} = 0b0001; // H form
1892}
1211} // isNotDuplicable, isIndirectBranch
1212
1213} // isBranch, isTerminator, isBarrier
1214
1215// FIXME: should be able to write a pattern for ARMBrcond, but can't use
1216// a two-value operand where a dag node expects two operands. :(
1217let isBranch = 1, isTerminator = 1 in
1218def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
1219 "b", ".w\t$target",
1893} // isNotDuplicable, isIndirectBranch
1894
1895} // isBranch, isTerminator, isBarrier
1896
1897// FIXME: should be able to write a pattern for ARMBrcond, but can't use
1898// a two-value operand where a dag node expects two operands. :(
1899let isBranch = 1, isTerminator = 1 in
1900def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
1901 "b", ".w\t$target",
1220 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
1902 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
1903 let Inst{31-27} = 0b11110;
1904 let Inst{15-14} = 0b10;
1905 let Inst{12} = 0;
1906}
1221
1222
1223// IT block
1224def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
1225 AddrModeNone, Size2Bytes, IIC_iALUx,
1907
1908
1909// IT block
1910def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
1911 AddrModeNone, Size2Bytes, IIC_iALUx,
1226 "it$mask\t$cc", "", []>;
1912 "it$mask\t$cc", "", []> {
1913 // 16-bit instruction.
1914 let Inst{31-16} = 0x0000;
1915 let Inst{15-8} = 0b10111111;
1916}
1227
1228//===----------------------------------------------------------------------===//
1229// Non-Instruction Patterns
1230//
1231
1232// Two piece so_imms.
1233def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS),
1234 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),

--- 38 unchanged lines hidden --- 		1917
1918//===----------------------------------------------------------------------===//
1919// Non-Instruction Patterns
1920//
1921
1922// Two piece so_imms.
1923def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS),
1924 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),

--- 38 unchanged lines hidden ---