1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
18#include "ARMSubtarget.h"
19#include "llvm/Target/TargetLowering.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include <vector>
23
24namespace llvm {
25 class ARMConstantPoolValue;
26
27 namespace ARMISD {
28 // ARM Specific DAG Nodes
29 enum NodeType {
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
34 // TargetExternalSymbol, and TargetGlobalAddress.
35 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
36
37 CALL, // Function call.
38 CALL_PRED, // Function call that's predicable.
39 CALL_NOLINK, // Function call with branch not branch-and-link.
40 tCALL, // Thumb function call.
41 BRCOND, // Conditional branch.
42 BR_JT, // Jumptable branch.
43 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
44 RET_FLAG, // Return with a flag operand.
45
46 PIC_ADD, // Add with a PC operand and a PIC label.
47
48 CMP, // ARM compare instructions.
49 CMPZ, // ARM compare that sets only Z flag.
50 CMPFP, // ARM VFP compare instruction, sets FPSCR.
51 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
52 FMSTAT, // ARM fmstat instruction.
53 CMOV, // ARM conditional move instructions.
54 CNEG, // ARM conditional negate instructions.
55
56 FTOSI, // FP to sint within a FP register.
57 FTOUI, // FP to uint within a FP register.
58 SITOF, // sint to FP within a FP register.
59 UITOF, // uint to FP within a FP register.
60
61 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
62 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
63 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
64
65 FMRRD, // double to two gprs.
66 FMDRR, // Two gprs to double.
67
68 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
69 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
70
71 THREAD_POINTER,
72
73 DYN_ALLOC, // Dynamic allocation on the stack.
74
75 VCEQ, // Vector compare equal.
76 VCGE, // Vector compare greater than or equal.
77 VCGEU, // Vector compare unsigned greater than or equal.
78 VCGT, // Vector compare greater than.
79 VCGTU, // Vector compare unsigned greater than.
80 VTST, // Vector test bits.
81
82 // Vector shift by immediate:
83 VSHL, // ...left
84 VSHRs, // ...right (signed)
85 VSHRu, // ...right (unsigned)
86 VSHLLs, // ...left long (signed)
87 VSHLLu, // ...left long (unsigned)
88 VSHLLi, // ...left long (with maximum shift count)
89 VSHRN, // ...right narrow
90
91 // Vector rounding shift by immediate:
92 VRSHRs, // ...right (signed)
93 VRSHRu, // ...right (unsigned)
94 VRSHRN, // ...right narrow
95
96 // Vector saturating shift by immediate:
97 VQSHLs, // ...left (signed)
98 VQSHLu, // ...left (unsigned)
99 VQSHLsu, // ...left (signed to unsigned)
100 VQSHRNs, // ...right narrow (signed)
101 VQSHRNu, // ...right narrow (unsigned)
102 VQSHRNsu, // ...right narrow (signed to unsigned)
103
104 // Vector saturating rounding shift by immediate:
105 VQRSHRNs, // ...right narrow (signed)
106 VQRSHRNu, // ...right narrow (unsigned)
107 VQRSHRNsu, // ...right narrow (signed to unsigned)
108
109 // Vector shift and insert:
110 VSLI, // ...left
111 VSRI, // ...right
112
113 // Vector get lane (VMOV scalar to ARM core register)
114 // (These are used for 8- and 16-bit element types only.)
115 VGETLANEu, // zero-extend vector extract element
116 VGETLANEs, // sign-extend vector extract element
117
118 // Vector duplicate:
119 VDUP,
120 VDUPLANE,
121
122 // Vector shuffles:
123 VEXT, // extract
124 VREV64, // reverse elements within 64-bit doublewords
125 VREV32, // reverse elements within 32-bit words
126 VREV16, // reverse elements within 16-bit halfwords
127 VZIP, // zip (interleave)
128 VUZP, // unzip (deinterleave)
129 VTRN // transpose
130 };
131 }
132
133 /// Define some predicates that are used for node matching.
134 namespace ARM {
135 /// getVMOVImm - If this is a build_vector of constants which can be
136 /// formed by using a VMOV instruction of the specified element size,
137 /// return the constant being splatted. The ByteSize field indicates the
138 /// number of bytes of each element [1248].
139 SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
| 1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
18#include "ARMSubtarget.h"
19#include "llvm/Target/TargetLowering.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include <vector>
23
24namespace llvm {
25 class ARMConstantPoolValue;
26
27 namespace ARMISD {
28 // ARM Specific DAG Nodes
29 enum NodeType {
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
34 // TargetExternalSymbol, and TargetGlobalAddress.
35 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
36
37 CALL, // Function call.
38 CALL_PRED, // Function call that's predicable.
39 CALL_NOLINK, // Function call with branch not branch-and-link.
40 tCALL, // Thumb function call.
41 BRCOND, // Conditional branch.
42 BR_JT, // Jumptable branch.
43 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
44 RET_FLAG, // Return with a flag operand.
45
46 PIC_ADD, // Add with a PC operand and a PIC label.
47
48 CMP, // ARM compare instructions.
49 CMPZ, // ARM compare that sets only Z flag.
50 CMPFP, // ARM VFP compare instruction, sets FPSCR.
51 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
52 FMSTAT, // ARM fmstat instruction.
53 CMOV, // ARM conditional move instructions.
54 CNEG, // ARM conditional negate instructions.
55
56 FTOSI, // FP to sint within a FP register.
57 FTOUI, // FP to uint within a FP register.
58 SITOF, // sint to FP within a FP register.
59 UITOF, // uint to FP within a FP register.
60
61 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
62 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
63 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
64
65 FMRRD, // double to two gprs.
66 FMDRR, // Two gprs to double.
67
68 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
69 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
70
71 THREAD_POINTER,
72
73 DYN_ALLOC, // Dynamic allocation on the stack.
74
75 VCEQ, // Vector compare equal.
76 VCGE, // Vector compare greater than or equal.
77 VCGEU, // Vector compare unsigned greater than or equal.
78 VCGT, // Vector compare greater than.
79 VCGTU, // Vector compare unsigned greater than.
80 VTST, // Vector test bits.
81
82 // Vector shift by immediate:
83 VSHL, // ...left
84 VSHRs, // ...right (signed)
85 VSHRu, // ...right (unsigned)
86 VSHLLs, // ...left long (signed)
87 VSHLLu, // ...left long (unsigned)
88 VSHLLi, // ...left long (with maximum shift count)
89 VSHRN, // ...right narrow
90
91 // Vector rounding shift by immediate:
92 VRSHRs, // ...right (signed)
93 VRSHRu, // ...right (unsigned)
94 VRSHRN, // ...right narrow
95
96 // Vector saturating shift by immediate:
97 VQSHLs, // ...left (signed)
98 VQSHLu, // ...left (unsigned)
99 VQSHLsu, // ...left (signed to unsigned)
100 VQSHRNs, // ...right narrow (signed)
101 VQSHRNu, // ...right narrow (unsigned)
102 VQSHRNsu, // ...right narrow (signed to unsigned)
103
104 // Vector saturating rounding shift by immediate:
105 VQRSHRNs, // ...right narrow (signed)
106 VQRSHRNu, // ...right narrow (unsigned)
107 VQRSHRNsu, // ...right narrow (signed to unsigned)
108
109 // Vector shift and insert:
110 VSLI, // ...left
111 VSRI, // ...right
112
113 // Vector get lane (VMOV scalar to ARM core register)
114 // (These are used for 8- and 16-bit element types only.)
115 VGETLANEu, // zero-extend vector extract element
116 VGETLANEs, // sign-extend vector extract element
117
118 // Vector duplicate:
119 VDUP,
120 VDUPLANE,
121
122 // Vector shuffles:
123 VEXT, // extract
124 VREV64, // reverse elements within 64-bit doublewords
125 VREV32, // reverse elements within 32-bit words
126 VREV16, // reverse elements within 16-bit halfwords
127 VZIP, // zip (interleave)
128 VUZP, // unzip (deinterleave)
129 VTRN // transpose
130 };
131 }
132
133 /// Define some predicates that are used for node matching.
134 namespace ARM {
135 /// getVMOVImm - If this is a build_vector of constants which can be
136 /// formed by using a VMOV instruction of the specified element size,
137 /// return the constant being splatted. The ByteSize field indicates the
138 /// number of bytes of each element [1248].
139 SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
|
| 140
141 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
142 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
143 /// instruction, returns its 8-bit integer representation. Otherwise,
144 /// returns -1.
145 int getVFPf32Imm(const APFloat &FPImm);
146 int getVFPf64Imm(const APFloat &FPImm);
|
140 }
141
142 //===--------------------------------------------------------------------===//
143 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
144
145 class ARMTargetLowering : public TargetLowering {
146 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
147 public:
148 explicit ARMTargetLowering(TargetMachine &TM);
149
150 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
151
152 /// ReplaceNodeResults - Replace the results of node with an illegal result
153 /// type with new values built out of custom code.
154 ///
155 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
156 SelectionDAG &DAG);
157
158 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
159
160 virtual const char *getTargetNodeName(unsigned Opcode) const;
161
162 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
163 MachineBasicBlock *MBB,
164 DenseMap<MachineBasicBlock*, MachineBasicBlock*>*) const;
165
166 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
167 /// unaligned memory accesses. of the specified type.
168 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
169 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
170
171 /// isLegalAddressingMode - Return true if the addressing mode represented
172 /// by AM is legal for this target, for a load/store of the specified type.
173 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
174 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
175
176 /// getPreIndexedAddressParts - returns true by value, base pointer and
177 /// offset pointer and addressing mode by reference if the node's address
178 /// can be legally represented as pre-indexed load / store address.
179 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
180 SDValue &Offset,
181 ISD::MemIndexedMode &AM,
182 SelectionDAG &DAG) const;
183
184 /// getPostIndexedAddressParts - returns true by value, base pointer and
185 /// offset pointer and addressing mode by reference if this node can be
186 /// combined with a load / store to form a post-indexed load / store.
187 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
188 SDValue &Base, SDValue &Offset,
189 ISD::MemIndexedMode &AM,
190 SelectionDAG &DAG) const;
191
192 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
193 const APInt &Mask,
194 APInt &KnownZero,
195 APInt &KnownOne,
196 const SelectionDAG &DAG,
197 unsigned Depth) const;
198
199
200 ConstraintType getConstraintType(const std::string &Constraint) const;
201 std::pair<unsigned, const TargetRegisterClass*>
202 getRegForInlineAsmConstraint(const std::string &Constraint,
203 EVT VT) const;
204 std::vector<unsigned>
205 getRegClassForInlineAsmConstraint(const std::string &Constraint,
206 EVT VT) const;
207
208 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
209 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
210 /// true it means one of the asm constraint of the inline asm instruction
211 /// being processed is 'm'.
212 virtual void LowerAsmOperandForConstraint(SDValue Op,
213 char ConstraintLetter,
214 bool hasMemory,
215 std::vector<SDValue> &Ops,
216 SelectionDAG &DAG) const;
217
218 virtual const ARMSubtarget* getSubtarget() {
219 return Subtarget;
220 }
221
222 /// getFunctionAlignment - Return the Log2 alignment of this function.
223 virtual unsigned getFunctionAlignment(const Function *F) const;
224
225 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
226 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
| 147 }
148
149 //===--------------------------------------------------------------------===//
150 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
151
152 class ARMTargetLowering : public TargetLowering {
153 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
154 public:
155 explicit ARMTargetLowering(TargetMachine &TM);
156
157 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
158
159 /// ReplaceNodeResults - Replace the results of node with an illegal result
160 /// type with new values built out of custom code.
161 ///
162 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
163 SelectionDAG &DAG);
164
165 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
166
167 virtual const char *getTargetNodeName(unsigned Opcode) const;
168
169 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
170 MachineBasicBlock *MBB,
171 DenseMap<MachineBasicBlock*, MachineBasicBlock*>*) const;
172
173 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
174 /// unaligned memory accesses. of the specified type.
175 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
176 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
177
178 /// isLegalAddressingMode - Return true if the addressing mode represented
179 /// by AM is legal for this target, for a load/store of the specified type.
180 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
181 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
182
183 /// getPreIndexedAddressParts - returns true by value, base pointer and
184 /// offset pointer and addressing mode by reference if the node's address
185 /// can be legally represented as pre-indexed load / store address.
186 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
187 SDValue &Offset,
188 ISD::MemIndexedMode &AM,
189 SelectionDAG &DAG) const;
190
191 /// getPostIndexedAddressParts - returns true by value, base pointer and
192 /// offset pointer and addressing mode by reference if this node can be
193 /// combined with a load / store to form a post-indexed load / store.
194 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
195 SDValue &Base, SDValue &Offset,
196 ISD::MemIndexedMode &AM,
197 SelectionDAG &DAG) const;
198
199 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
200 const APInt &Mask,
201 APInt &KnownZero,
202 APInt &KnownOne,
203 const SelectionDAG &DAG,
204 unsigned Depth) const;
205
206
207 ConstraintType getConstraintType(const std::string &Constraint) const;
208 std::pair<unsigned, const TargetRegisterClass*>
209 getRegForInlineAsmConstraint(const std::string &Constraint,
210 EVT VT) const;
211 std::vector<unsigned>
212 getRegClassForInlineAsmConstraint(const std::string &Constraint,
213 EVT VT) const;
214
215 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
216 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
217 /// true it means one of the asm constraint of the inline asm instruction
218 /// being processed is 'm'.
219 virtual void LowerAsmOperandForConstraint(SDValue Op,
220 char ConstraintLetter,
221 bool hasMemory,
222 std::vector<SDValue> &Ops,
223 SelectionDAG &DAG) const;
224
225 virtual const ARMSubtarget* getSubtarget() {
226 return Subtarget;
227 }
228
229 /// getFunctionAlignment - Return the Log2 alignment of this function.
230 virtual unsigned getFunctionAlignment(const Function *F) const;
231
232 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
233 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
|
| 234
235 /// isFPImmLegal - Returns true if the target can instruction select the
236 /// specified FP immediate natively. If false, the legalizer will
237 /// materialize the FP immediate as a load from a constant pool.
238 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
239
|
227 private:
228 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
229 /// make the right decision when generating code for different targets.
230 const ARMSubtarget *Subtarget;
231
232 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
233 ///
234 unsigned ARMPCLabelIndex;
235
236 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
237 void addDRTypeForNEON(EVT VT);
238 void addQRTypeForNEON(EVT VT);
239
240 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
241 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
242 SDValue Chain, SDValue &Arg,
243 RegsToPassVector &RegsToPass,
244 CCValAssign &VA, CCValAssign &NextVA,
245 SDValue &StackPtr,
246 SmallVector<SDValue, 8> &MemOpChains,
247 ISD::ArgFlagsTy Flags);
248 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
249 SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
250
251 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const;
252 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
253 DebugLoc dl, SelectionDAG &DAG,
254 const CCValAssign &VA,
255 ISD::ArgFlagsTy Flags);
256 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG);
257 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
| 240 private:
241 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
242 /// make the right decision when generating code for different targets.
243 const ARMSubtarget *Subtarget;
244
245 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
246 ///
247 unsigned ARMPCLabelIndex;
248
249 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
250 void addDRTypeForNEON(EVT VT);
251 void addQRTypeForNEON(EVT VT);
252
253 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
254 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
255 SDValue Chain, SDValue &Arg,
256 RegsToPassVector &RegsToPass,
257 CCValAssign &VA, CCValAssign &NextVA,
258 SDValue &StackPtr,
259 SmallVector<SDValue, 8> &MemOpChains,
260 ISD::ArgFlagsTy Flags);
261 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
262 SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
263
264 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const;
265 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
266 DebugLoc dl, SelectionDAG &DAG,
267 const CCValAssign &VA,
268 ISD::ArgFlagsTy Flags);
269 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG);
270 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
|
| 271 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
|
258 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
259 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
260 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
261 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
262 SelectionDAG &DAG);
263 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
264 SelectionDAG &DAG);
265 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
266 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
267 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
268 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
269
270 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
271 SDValue Chain,
272 SDValue Dst, SDValue Src,
273 SDValue Size, unsigned Align,
274 bool AlwaysInline,
275 const Value *DstSV, uint64_t DstSVOff,
276 const Value *SrcSV, uint64_t SrcSVOff);
277 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
278 CallingConv::ID CallConv, bool isVarArg,
279 const SmallVectorImpl<ISD::InputArg> &Ins,
280 DebugLoc dl, SelectionDAG &DAG,
281 SmallVectorImpl<SDValue> &InVals);
282
283 virtual SDValue
284 LowerFormalArguments(SDValue Chain,
285 CallingConv::ID CallConv, bool isVarArg,
286 const SmallVectorImpl<ISD::InputArg> &Ins,
287 DebugLoc dl, SelectionDAG &DAG,
288 SmallVectorImpl<SDValue> &InVals);
289
290 virtual SDValue
291 LowerCall(SDValue Chain, SDValue Callee,
292 CallingConv::ID CallConv, bool isVarArg,
293 bool isTailCall,
294 const SmallVectorImpl<ISD::OutputArg> &Outs,
295 const SmallVectorImpl<ISD::InputArg> &Ins,
296 DebugLoc dl, SelectionDAG &DAG,
297 SmallVectorImpl<SDValue> &InVals);
298
299 virtual SDValue
300 LowerReturn(SDValue Chain,
301 CallingConv::ID CallConv, bool isVarArg,
302 const SmallVectorImpl<ISD::OutputArg> &Outs,
303 DebugLoc dl, SelectionDAG &DAG);
304 };
305}
306
307#endif // ARMISELLOWERING_H
| 272 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
273 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
274 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
275 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
276 SelectionDAG &DAG);
277 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
278 SelectionDAG &DAG);
279 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
280 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
281 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
282 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
283
284 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
285 SDValue Chain,
286 SDValue Dst, SDValue Src,
287 SDValue Size, unsigned Align,
288 bool AlwaysInline,
289 const Value *DstSV, uint64_t DstSVOff,
290 const Value *SrcSV, uint64_t SrcSVOff);
291 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
292 CallingConv::ID CallConv, bool isVarArg,
293 const SmallVectorImpl<ISD::InputArg> &Ins,
294 DebugLoc dl, SelectionDAG &DAG,
295 SmallVectorImpl<SDValue> &InVals);
296
297 virtual SDValue
298 LowerFormalArguments(SDValue Chain,
299 CallingConv::ID CallConv, bool isVarArg,
300 const SmallVectorImpl<ISD::InputArg> &Ins,
301 DebugLoc dl, SelectionDAG &DAG,
302 SmallVectorImpl<SDValue> &InVals);
303
304 virtual SDValue
305 LowerCall(SDValue Chain, SDValue Callee,
306 CallingConv::ID CallConv, bool isVarArg,
307 bool isTailCall,
308 const SmallVectorImpl<ISD::OutputArg> &Outs,
309 const SmallVectorImpl<ISD::InputArg> &Ins,
310 DebugLoc dl, SelectionDAG &DAG,
311 SmallVectorImpl<SDValue> &InVals);
312
313 virtual SDValue
314 LowerReturn(SDValue Chain,
315 CallingConv::ID CallConv, bool isVarArg,
316 const SmallVectorImpl<ISD::OutputArg> &Outs,
317 DebugLoc dl, SelectionDAG &DAG);
318 };
319}
320
321#endif // ARMISELLOWERING_H
|