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ARMISelDAGToDAG.cpp (207618) ARMISelDAGToDAG.cpp (207631)
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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22#include "llvm/LLVMContext.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/SelectionDAG.h"
27#include "llvm/CodeGen/SelectionDAGISel.h"
28#include "llvm/Target/TargetLowering.h"
29#include "llvm/Target/TargetOptions.h"
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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22#include "llvm/LLVMContext.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/SelectionDAG.h"
27#include "llvm/CodeGen/SelectionDAGISel.h"
28#include "llvm/Target/TargetLowering.h"
29#include "llvm/Target/TargetOptions.h"
30#include "llvm/Support/CommandLine.h"
30#include "llvm/Support/Compiler.h"
31#include "llvm/Support/Debug.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/raw_ostream.h"
34
35using namespace llvm;
36
31#include "llvm/Support/Compiler.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35
36using namespace llvm;
37
38static cl::opt<bool>
39UseRegSeq("neon-reg-sequence", cl::Hidden,
40 cl::desc("Use reg_sequence to model ld / st of multiple neon regs"));
41
37//===--------------------------------------------------------------------===//
38/// ARMDAGToDAGISel - ARM specific code to select ARM machine
39/// instructions for SelectionDAG operations.
40///
41namespace {
42class ARMDAGToDAGISel : public SelectionDAGISel {
43 ARMBaseTargetMachine &TM;
44

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934
935 return NULL;
936}
937
938/// PairDRegs - Insert a pair of double registers into an implicit def to
939/// form a quad register.
940SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
941 DebugLoc dl = V0.getNode()->getDebugLoc();
42//===--------------------------------------------------------------------===//
43/// ARMDAGToDAGISel - ARM specific code to select ARM machine
44/// instructions for SelectionDAG operations.
45///
46namespace {
47class ARMDAGToDAGISel : public SelectionDAGISel {
48 ARMBaseTargetMachine &TM;
49

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939
940 return NULL;
941}
942
943/// PairDRegs - Insert a pair of double registers into an implicit def to
944/// form a quad register.
945SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
946 DebugLoc dl = V0.getNode()->getDebugLoc();
942 SDValue Undef =
943 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0);
944 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
945 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
947 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
948 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
949 if (UseRegSeq) {
950 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
951 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
952 }
953 SDValue Undef =
954 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0);
946 SDNode *Pair = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
947 VT, Undef, V0, SubReg0);
948 return CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
949 VT, SDValue(Pair, 0), V1, SubReg1);
950}
951
952/// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type
953/// for a 64-bit subregister of the vector.

--- 1035 unchanged lines hidden --- 		955 SDNode *Pair = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
956 VT, Undef, V0, SubReg0);
957 return CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
958 VT, SDValue(Pair, 0), V1, SubReg1);
959}
960
961/// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type
962/// for a 64-bit subregister of the vector.

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