| ARMBaseInstrInfo.h (198090) | ARMBaseInstrInfo.h (198892) |
|---|---|
| 1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information -------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 117 unchanged lines hidden (view full) --- 126 // it doesn't have a Rn operand. 127 UnaryDP = 1 << 15, 128 129 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into 130 // a 16-bit Thumb instruction if certain conditions are met. 131 Xform16Bit = 1 << 16, 132 133 //===------------------------------------------------------------------===// | 1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information -------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 117 unchanged lines hidden (view full) --- 126 // it doesn't have a Rn operand. 127 UnaryDP = 1 << 15, 128 129 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into 130 // a 16-bit Thumb instruction if certain conditions are met. 131 Xform16Bit = 1 << 16, 132 133 //===------------------------------------------------------------------===// |
| 134 // Code domain. 135 DomainShift = 17, 136 DomainMask = 3 << DomainShift, 137 DomainGeneral = 0 << DomainShift, 138 DomainVFP = 1 << DomainShift, 139 DomainNEON = 2 << DomainShift, 140 141 //===------------------------------------------------------------------===// |
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| 134 // Field shifts - such shifts are used to set field while generating 135 // machine instructions. 136 M_BitShift = 5, 137 ShiftImmShift = 5, 138 ShiftShift = 7, 139 N_BitShift = 7, 140 ImmHiShift = 8, 141 SoRotImmShift = 8, --- 10 unchanged lines hidden (view full) --- 152 U_BitShift = 23, 153 P_BitShift = 24, 154 I_BitShift = 25, 155 CondShift = 28 156 }; 157} 158 159class ARMBaseInstrInfo : public TargetInstrInfoImpl { | 142 // Field shifts - such shifts are used to set field while generating 143 // machine instructions. 144 M_BitShift = 5, 145 ShiftImmShift = 5, 146 ShiftShift = 7, 147 N_BitShift = 7, 148 ImmHiShift = 8, 149 SoRotImmShift = 8, --- 10 unchanged lines hidden (view full) --- 160 U_BitShift = 23, 161 P_BitShift = 24, 162 I_BitShift = 25, 163 CondShift = 28 164 }; 165} 166 167class ARMBaseInstrInfo : public TargetInstrInfoImpl { |
| 168 const ARMSubtarget& Subtarget; |
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| 160protected: 161 // Can be only subclassed. | 169protected: 170 // Can be only subclassed. |
| 162 explicit ARMBaseInstrInfo(); | 171 explicit ARMBaseInstrInfo(const ARMSubtarget &STI); |
| 163public: 164 // Return the non-pre/post incrementing version of 'Opc'. Return 0 165 // if there is not such an opcode. 166 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0; 167 168 // Return true if the block does not fall through. 169 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0; 170 171 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 172 MachineBasicBlock::iterator &MBBI, 173 LiveVariables *LV) const; 174 175 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0; | 172public: 173 // Return the non-pre/post incrementing version of 'Opc'. Return 0 174 // if there is not such an opcode. 175 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0; 176 177 // Return true if the block does not fall through. 178 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0; 179 180 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 181 MachineBasicBlock::iterator &MBBI, 182 LiveVariables *LV) const; 183 184 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0; |
| 185 const ARMSubtarget &getSubtarget() const { return Subtarget; } |
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| 176 177 // Branch analysis. 178 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 179 MachineBasicBlock *&FBB, 180 SmallVectorImpl<MachineOperand> &Cond, 181 bool AllowModify) const; 182 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 183 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, --- 104 unchanged lines hidden (view full) --- 288} 289 290static inline 291bool isJumpTableBranchOpcode(int Opc) { 292 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd || 293 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; 294} 295 | 186 187 // Branch analysis. 188 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 189 MachineBasicBlock *&FBB, 190 SmallVectorImpl<MachineOperand> &Cond, 191 bool AllowModify) const; 192 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 193 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, --- 104 unchanged lines hidden (view full) --- 298} 299 300static inline 301bool isJumpTableBranchOpcode(int Opc) { 302 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd || 303 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; 304} 305 |
| 306static inline 307bool isIndirectBranchOpcode(int Opc) { 308 return Opc == ARM::BRIND || Opc == ARM::tBRIND; 309} 310 |
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| 296/// getInstrPredicate - If instruction is predicated, returns its predicate 297/// condition, otherwise returns AL. It also returns the condition code 298/// register by reference. 299ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 300 301int getMatchingCondBranchOpcode(int Opc); 302 303/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of --- 30 unchanged lines hidden --- | 311/// getInstrPredicate - If instruction is predicated, returns its predicate 312/// condition, otherwise returns AL. It also returns the condition code 313/// register by reference. 314ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 315 316int getMatchingCondBranchOpcode(int Opc); 317 318/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of --- 30 unchanged lines hidden --- |