1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information -------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "ARMRegisterInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22namespace llvm {
23
24/// ARMII - This namespace holds all of the target specific flags that
25/// instruction info tracks.
26///
27namespace ARMII {
28 enum {
29 //===------------------------------------------------------------------===//
30 // Instruction Flags.
31
32 //===------------------------------------------------------------------===//
33 // This four-bit field describes the addressing mode used.
34
35 AddrModeMask = 0xf,
36 AddrModeNone = 0,
37 AddrMode1 = 1,
38 AddrMode2 = 2,
39 AddrMode3 = 3,
40 AddrMode4 = 4,
41 AddrMode5 = 5,
42 AddrMode6 = 6,
43 AddrModeT1_1 = 7,
44 AddrModeT1_2 = 8,
45 AddrModeT1_4 = 9,
46 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
47 AddrModeT2_i12 = 11,
48 AddrModeT2_i8 = 12,
49 AddrModeT2_so = 13,
50 AddrModeT2_pc = 14, // +/- i12 for pc relative data
51 AddrModeT2_i8s4 = 15, // i8 * 4
52
53 // Size* - Flags to keep track of the size of an instruction.
54 SizeShift = 4,
55 SizeMask = 7 << SizeShift,
56 SizeSpecial = 1, // 0 byte pseudo or special case.
57 Size8Bytes = 2,
58 Size4Bytes = 3,
59 Size2Bytes = 4,
60
61 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
62 // and store ops
63 IndexModeShift = 7,
64 IndexModeMask = 3 << IndexModeShift,
65 IndexModePre = 1,
66 IndexModePost = 2,
67
68 //===------------------------------------------------------------------===//
69 // Instruction encoding formats.
70 //
71 FormShift = 9,
72 FormMask = 0x3f << FormShift,
73
74 // Pseudo instructions
75 Pseudo = 0 << FormShift,
76
77 // Multiply instructions
78 MulFrm = 1 << FormShift,
79
80 // Branch instructions
81 BrFrm = 2 << FormShift,
82 BrMiscFrm = 3 << FormShift,
83
84 // Data Processing instructions
85 DPFrm = 4 << FormShift,
86 DPSoRegFrm = 5 << FormShift,
87
88 // Load and Store
89 LdFrm = 6 << FormShift,
90 StFrm = 7 << FormShift,
91 LdMiscFrm = 8 << FormShift,
92 StMiscFrm = 9 << FormShift,
93 LdStMulFrm = 10 << FormShift,
94
95 // Miscellaneous arithmetic instructions
96 ArithMiscFrm = 11 << FormShift,
97
98 // Extend instructions
99 ExtFrm = 12 << FormShift,
100
101 // VFP formats
102 VFPUnaryFrm = 13 << FormShift,
103 VFPBinaryFrm = 14 << FormShift,
104 VFPConv1Frm = 15 << FormShift,
105 VFPConv2Frm = 16 << FormShift,
106 VFPConv3Frm = 17 << FormShift,
107 VFPConv4Frm = 18 << FormShift,
108 VFPConv5Frm = 19 << FormShift,
109 VFPLdStFrm = 20 << FormShift,
110 VFPLdStMulFrm = 21 << FormShift,
111 VFPMiscFrm = 22 << FormShift,
112
113 // Thumb format
114 ThumbFrm = 23 << FormShift,
115
116 // NEON format
117 NEONFrm = 24 << FormShift,
118 NEONGetLnFrm = 25 << FormShift,
119 NEONSetLnFrm = 26 << FormShift,
120 NEONDupFrm = 27 << FormShift,
121
122 //===------------------------------------------------------------------===//
123 // Misc flags.
124
125 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
126 // it doesn't have a Rn operand.
127 UnaryDP = 1 << 15,
128
129 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
130 // a 16-bit Thumb instruction if certain conditions are met.
131 Xform16Bit = 1 << 16,
132
133 //===------------------------------------------------------------------===//
| 1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information -------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "ARMRegisterInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22namespace llvm {
23
24/// ARMII - This namespace holds all of the target specific flags that
25/// instruction info tracks.
26///
27namespace ARMII {
28 enum {
29 //===------------------------------------------------------------------===//
30 // Instruction Flags.
31
32 //===------------------------------------------------------------------===//
33 // This four-bit field describes the addressing mode used.
34
35 AddrModeMask = 0xf,
36 AddrModeNone = 0,
37 AddrMode1 = 1,
38 AddrMode2 = 2,
39 AddrMode3 = 3,
40 AddrMode4 = 4,
41 AddrMode5 = 5,
42 AddrMode6 = 6,
43 AddrModeT1_1 = 7,
44 AddrModeT1_2 = 8,
45 AddrModeT1_4 = 9,
46 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
47 AddrModeT2_i12 = 11,
48 AddrModeT2_i8 = 12,
49 AddrModeT2_so = 13,
50 AddrModeT2_pc = 14, // +/- i12 for pc relative data
51 AddrModeT2_i8s4 = 15, // i8 * 4
52
53 // Size* - Flags to keep track of the size of an instruction.
54 SizeShift = 4,
55 SizeMask = 7 << SizeShift,
56 SizeSpecial = 1, // 0 byte pseudo or special case.
57 Size8Bytes = 2,
58 Size4Bytes = 3,
59 Size2Bytes = 4,
60
61 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
62 // and store ops
63 IndexModeShift = 7,
64 IndexModeMask = 3 << IndexModeShift,
65 IndexModePre = 1,
66 IndexModePost = 2,
67
68 //===------------------------------------------------------------------===//
69 // Instruction encoding formats.
70 //
71 FormShift = 9,
72 FormMask = 0x3f << FormShift,
73
74 // Pseudo instructions
75 Pseudo = 0 << FormShift,
76
77 // Multiply instructions
78 MulFrm = 1 << FormShift,
79
80 // Branch instructions
81 BrFrm = 2 << FormShift,
82 BrMiscFrm = 3 << FormShift,
83
84 // Data Processing instructions
85 DPFrm = 4 << FormShift,
86 DPSoRegFrm = 5 << FormShift,
87
88 // Load and Store
89 LdFrm = 6 << FormShift,
90 StFrm = 7 << FormShift,
91 LdMiscFrm = 8 << FormShift,
92 StMiscFrm = 9 << FormShift,
93 LdStMulFrm = 10 << FormShift,
94
95 // Miscellaneous arithmetic instructions
96 ArithMiscFrm = 11 << FormShift,
97
98 // Extend instructions
99 ExtFrm = 12 << FormShift,
100
101 // VFP formats
102 VFPUnaryFrm = 13 << FormShift,
103 VFPBinaryFrm = 14 << FormShift,
104 VFPConv1Frm = 15 << FormShift,
105 VFPConv2Frm = 16 << FormShift,
106 VFPConv3Frm = 17 << FormShift,
107 VFPConv4Frm = 18 << FormShift,
108 VFPConv5Frm = 19 << FormShift,
109 VFPLdStFrm = 20 << FormShift,
110 VFPLdStMulFrm = 21 << FormShift,
111 VFPMiscFrm = 22 << FormShift,
112
113 // Thumb format
114 ThumbFrm = 23 << FormShift,
115
116 // NEON format
117 NEONFrm = 24 << FormShift,
118 NEONGetLnFrm = 25 << FormShift,
119 NEONSetLnFrm = 26 << FormShift,
120 NEONDupFrm = 27 << FormShift,
121
122 //===------------------------------------------------------------------===//
123 // Misc flags.
124
125 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
126 // it doesn't have a Rn operand.
127 UnaryDP = 1 << 15,
128
129 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
130 // a 16-bit Thumb instruction if certain conditions are met.
131 Xform16Bit = 1 << 16,
132
133 //===------------------------------------------------------------------===//
|
| 134 // Code domain.
135 DomainShift = 17,
136 DomainMask = 3 << DomainShift,
137 DomainGeneral = 0 << DomainShift,
138 DomainVFP = 1 << DomainShift,
139 DomainNEON = 2 << DomainShift,
140
141 //===------------------------------------------------------------------===//
|
134 // Field shifts - such shifts are used to set field while generating
135 // machine instructions.
136 M_BitShift = 5,
137 ShiftImmShift = 5,
138 ShiftShift = 7,
139 N_BitShift = 7,
140 ImmHiShift = 8,
141 SoRotImmShift = 8,
142 RegRsShift = 8,
143 ExtRotImmShift = 10,
144 RegRdLoShift = 12,
145 RegRdShift = 12,
146 RegRdHiShift = 16,
147 RegRnShift = 16,
148 S_BitShift = 20,
149 W_BitShift = 21,
150 AM3_I_BitShift = 22,
151 D_BitShift = 22,
152 U_BitShift = 23,
153 P_BitShift = 24,
154 I_BitShift = 25,
155 CondShift = 28
156 };
157}
158
159class ARMBaseInstrInfo : public TargetInstrInfoImpl {
| 142 // Field shifts - such shifts are used to set field while generating
143 // machine instructions.
144 M_BitShift = 5,
145 ShiftImmShift = 5,
146 ShiftShift = 7,
147 N_BitShift = 7,
148 ImmHiShift = 8,
149 SoRotImmShift = 8,
150 RegRsShift = 8,
151 ExtRotImmShift = 10,
152 RegRdLoShift = 12,
153 RegRdShift = 12,
154 RegRdHiShift = 16,
155 RegRnShift = 16,
156 S_BitShift = 20,
157 W_BitShift = 21,
158 AM3_I_BitShift = 22,
159 D_BitShift = 22,
160 U_BitShift = 23,
161 P_BitShift = 24,
162 I_BitShift = 25,
163 CondShift = 28
164 };
165}
166
167class ARMBaseInstrInfo : public TargetInstrInfoImpl {
|
| 168 const ARMSubtarget& Subtarget;
|
160protected:
161 // Can be only subclassed.
| 169protected:
170 // Can be only subclassed.
|
162 explicit ARMBaseInstrInfo();
| 171 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
|
163public:
164 // Return the non-pre/post incrementing version of 'Opc'. Return 0
165 // if there is not such an opcode.
166 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
167
168 // Return true if the block does not fall through.
169 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0;
170
171 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
172 MachineBasicBlock::iterator &MBBI,
173 LiveVariables *LV) const;
174
175 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
| 172public:
173 // Return the non-pre/post incrementing version of 'Opc'. Return 0
174 // if there is not such an opcode.
175 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
176
177 // Return true if the block does not fall through.
178 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0;
179
180 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
181 MachineBasicBlock::iterator &MBBI,
182 LiveVariables *LV) const;
183
184 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
|
| 185 const ARMSubtarget &getSubtarget() const { return Subtarget; }
|
176
177 // Branch analysis.
178 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
179 MachineBasicBlock *&FBB,
180 SmallVectorImpl<MachineOperand> &Cond,
181 bool AllowModify) const;
182 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
183 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
184 MachineBasicBlock *FBB,
185 const SmallVectorImpl<MachineOperand> &Cond) const;
186
187 virtual
188 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
189
190 // Predication support.
191 bool isPredicated(const MachineInstr *MI) const {
192 int PIdx = MI->findFirstPredOperandIdx();
193 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
194 }
195
196 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
197 int PIdx = MI->findFirstPredOperandIdx();
198 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
199 : ARMCC::AL;
200 }
201
202 virtual
203 bool PredicateInstruction(MachineInstr *MI,
204 const SmallVectorImpl<MachineOperand> &Pred) const;
205
206 virtual
207 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
208 const SmallVectorImpl<MachineOperand> &Pred2) const;
209
210 virtual bool DefinesPredicate(MachineInstr *MI,
211 std::vector<MachineOperand> &Pred) const;
212
213 /// GetInstSize - Returns the size of the specified MachineInstr.
214 ///
215 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
216
217 /// Return true if the instruction is a register to register move and return
218 /// the source and dest operands and their sub-register indices by reference.
219 virtual bool isMoveInstr(const MachineInstr &MI,
220 unsigned &SrcReg, unsigned &DstReg,
221 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
222
223 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
224 int &FrameIndex) const;
225 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
226 int &FrameIndex) const;
227
228 virtual bool copyRegToReg(MachineBasicBlock &MBB,
229 MachineBasicBlock::iterator I,
230 unsigned DestReg, unsigned SrcReg,
231 const TargetRegisterClass *DestRC,
232 const TargetRegisterClass *SrcRC) const;
233
234 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
235 MachineBasicBlock::iterator MBBI,
236 unsigned SrcReg, bool isKill, int FrameIndex,
237 const TargetRegisterClass *RC) const;
238
239 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
240 MachineBasicBlock::iterator MBBI,
241 unsigned DestReg, int FrameIndex,
242 const TargetRegisterClass *RC) const;
243
244 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
245 const SmallVectorImpl<unsigned> &Ops) const;
246
247 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
248 MachineInstr* MI,
249 const SmallVectorImpl<unsigned> &Ops,
250 int FrameIndex) const;
251
252 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
253 MachineInstr* MI,
254 const SmallVectorImpl<unsigned> &Ops,
255 MachineInstr* LoadMI) const;
256
257};
258
259static inline
260const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
261 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
262}
263
264static inline
265const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
266 return MIB.addReg(0);
267}
268
269static inline
270const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
271 bool isDead = false) {
272 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
273}
274
275static inline
276const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
277 return MIB.addReg(0);
278}
279
280static inline
281bool isUncondBranchOpcode(int Opc) {
282 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
283}
284
285static inline
286bool isCondBranchOpcode(int Opc) {
287 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
288}
289
290static inline
291bool isJumpTableBranchOpcode(int Opc) {
292 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
293 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
294}
295
| 186
187 // Branch analysis.
188 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
189 MachineBasicBlock *&FBB,
190 SmallVectorImpl<MachineOperand> &Cond,
191 bool AllowModify) const;
192 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
193 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
194 MachineBasicBlock *FBB,
195 const SmallVectorImpl<MachineOperand> &Cond) const;
196
197 virtual
198 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
199
200 // Predication support.
201 bool isPredicated(const MachineInstr *MI) const {
202 int PIdx = MI->findFirstPredOperandIdx();
203 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
204 }
205
206 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
207 int PIdx = MI->findFirstPredOperandIdx();
208 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
209 : ARMCC::AL;
210 }
211
212 virtual
213 bool PredicateInstruction(MachineInstr *MI,
214 const SmallVectorImpl<MachineOperand> &Pred) const;
215
216 virtual
217 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
218 const SmallVectorImpl<MachineOperand> &Pred2) const;
219
220 virtual bool DefinesPredicate(MachineInstr *MI,
221 std::vector<MachineOperand> &Pred) const;
222
223 /// GetInstSize - Returns the size of the specified MachineInstr.
224 ///
225 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
226
227 /// Return true if the instruction is a register to register move and return
228 /// the source and dest operands and their sub-register indices by reference.
229 virtual bool isMoveInstr(const MachineInstr &MI,
230 unsigned &SrcReg, unsigned &DstReg,
231 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
232
233 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
234 int &FrameIndex) const;
235 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
236 int &FrameIndex) const;
237
238 virtual bool copyRegToReg(MachineBasicBlock &MBB,
239 MachineBasicBlock::iterator I,
240 unsigned DestReg, unsigned SrcReg,
241 const TargetRegisterClass *DestRC,
242 const TargetRegisterClass *SrcRC) const;
243
244 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
245 MachineBasicBlock::iterator MBBI,
246 unsigned SrcReg, bool isKill, int FrameIndex,
247 const TargetRegisterClass *RC) const;
248
249 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
250 MachineBasicBlock::iterator MBBI,
251 unsigned DestReg, int FrameIndex,
252 const TargetRegisterClass *RC) const;
253
254 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
255 const SmallVectorImpl<unsigned> &Ops) const;
256
257 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
258 MachineInstr* MI,
259 const SmallVectorImpl<unsigned> &Ops,
260 int FrameIndex) const;
261
262 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
263 MachineInstr* MI,
264 const SmallVectorImpl<unsigned> &Ops,
265 MachineInstr* LoadMI) const;
266
267};
268
269static inline
270const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
271 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
272}
273
274static inline
275const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
276 return MIB.addReg(0);
277}
278
279static inline
280const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
281 bool isDead = false) {
282 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
283}
284
285static inline
286const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
287 return MIB.addReg(0);
288}
289
290static inline
291bool isUncondBranchOpcode(int Opc) {
292 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
293}
294
295static inline
296bool isCondBranchOpcode(int Opc) {
297 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
298}
299
300static inline
301bool isJumpTableBranchOpcode(int Opc) {
302 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
303 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
304}
305
|
| 306static inline
307bool isIndirectBranchOpcode(int Opc) {
308 return Opc == ARM::BRIND || Opc == ARM::tBRIND;
309}
310
|
296/// getInstrPredicate - If instruction is predicated, returns its predicate
297/// condition, otherwise returns AL. It also returns the condition code
298/// register by reference.
299ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
300
301int getMatchingCondBranchOpcode(int Opc);
302
303/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
304/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
305/// code.
306void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
307 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
308 unsigned DestReg, unsigned BaseReg, int NumBytes,
309 ARMCC::CondCodes Pred, unsigned PredReg,
310 const ARMBaseInstrInfo &TII);
311
312void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
313 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
314 unsigned DestReg, unsigned BaseReg, int NumBytes,
315 ARMCC::CondCodes Pred, unsigned PredReg,
316 const ARMBaseInstrInfo &TII);
317
318
319/// rewriteARMFrameIndex / rewriteT2FrameIndex -
320/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
321/// offset could not be handled directly in MI, and return the left-over
322/// portion by reference.
323bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
324 unsigned FrameReg, int &Offset,
325 const ARMBaseInstrInfo &TII);
326
327bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
328 unsigned FrameReg, int &Offset,
329 const ARMBaseInstrInfo &TII);
330
331} // End llvm namespace
332
333#endif
| 311/// getInstrPredicate - If instruction is predicated, returns its predicate
312/// condition, otherwise returns AL. It also returns the condition code
313/// register by reference.
314ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
315
316int getMatchingCondBranchOpcode(int Opc);
317
318/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
319/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
320/// code.
321void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
322 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
323 unsigned DestReg, unsigned BaseReg, int NumBytes,
324 ARMCC::CondCodes Pred, unsigned PredReg,
325 const ARMBaseInstrInfo &TII);
326
327void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
328 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
329 unsigned DestReg, unsigned BaseReg, int NumBytes,
330 ARMCC::CondCodes Pred, unsigned PredReg,
331 const ARMBaseInstrInfo &TII);
332
333
334/// rewriteARMFrameIndex / rewriteT2FrameIndex -
335/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
336/// offset could not be handled directly in MI, and return the left-over
337/// portion by reference.
338bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
339 unsigned FrameReg, int &Offset,
340 const ARMBaseInstrInfo &TII);
341
342bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
343 unsigned FrameReg, int &Offset,
344 const ARMBaseInstrInfo &TII);
345
346} // End llvm namespace
347
348#endif
|