1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information -------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 117 unchanged lines hidden (view full) ---

126 // it doesn't have a Rn operand.
127 UnaryDP = 1 << 15,
128
129 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
130 // a 16-bit Thumb instruction if certain conditions are met.
131 Xform16Bit = 1 << 16,
132
133 //===------------------------------------------------------------------===//
134 // Field shifts - such shifts are used to set field while generating
135 // machine instructions.
136 M_BitShift = 5,
137 ShiftImmShift = 5,
138 ShiftShift = 7,
139 N_BitShift = 7,
140 ImmHiShift = 8,
141 SoRotImmShift = 8,

--- 10 unchanged lines hidden (view full) ---

152 U_BitShift = 23,
153 P_BitShift = 24,
154 I_BitShift = 25,
155 CondShift = 28
156 };
157}
158
159class ARMBaseInstrInfo : public TargetInstrInfoImpl {
160protected:
161 // Can be only subclassed.
162 explicit ARMBaseInstrInfo();
163public:
164 // Return the non-pre/post incrementing version of 'Opc'. Return 0
165 // if there is not such an opcode.
166 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
167
168 // Return true if the block does not fall through.
169 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0;
170
171 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
172 MachineBasicBlock::iterator &MBBI,
173 LiveVariables *LV) const;
174
175 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
176
177 // Branch analysis.
178 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
179 MachineBasicBlock *&FBB,
180 SmallVectorImpl<MachineOperand> &Cond,
181 bool AllowModify) const;
182 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
183 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,

--- 104 unchanged lines hidden (view full) ---

288}
289
290static inline
291bool isJumpTableBranchOpcode(int Opc) {
292 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
293 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
294}
295
296/// getInstrPredicate - If instruction is predicated, returns its predicate
297/// condition, otherwise returns AL. It also returns the condition code
298/// register by reference.
299ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
300
301int getMatchingCondBranchOpcode(int Opc);
302
303/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of

--- 30 unchanged lines hidden ---