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ARMBaseInstrInfo.cpp (198090) ARMBaseInstrInfo.cpp (198892)
1//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMBaseInstrInfo.h"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMGenInstrInfo.inc"
18#include "ARMMachineFunctionInfo.h"
1//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMBaseInstrInfo.h"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMGenInstrInfo.inc"
18#include "ARMMachineFunctionInfo.h"
19#include "ARMRegisterInfo.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/CodeGen/LiveVariables.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineJumpTableInfo.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/MC/MCAsmInfo.h"
27#include "llvm/Support/CommandLine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/LiveVariables.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineJumpTableInfo.h"
25#include "llvm/CodeGen/MachineMemOperand.h"
26#include "llvm/CodeGen/PseudoSourceValue.h"
27#include "llvm/MC/MCAsmInfo.h"
28#include "llvm/Support/CommandLine.h"
29#include "llvm/Support/Debug.h"
28#include "llvm/Support/ErrorHandling.h"
29using namespace llvm;
30
31static cl::opt<bool>
32EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
33 cl::desc("Enable ARM 2-addr to 3-addr conv"));
34
30#include "llvm/Support/ErrorHandling.h"
31using namespace llvm;
32
33static cl::opt<bool>
34EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
35 cl::desc("Enable ARM 2-addr to 3-addr conv"));
36
35ARMBaseInstrInfo::ARMBaseInstrInfo()
36 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) {
37ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
38 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
39 Subtarget(STI) {
37}
38
39MachineInstr *
40ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
41 MachineBasicBlock::iterator &MBBI,
42 LiveVariables *LV) const {
43 // FIXME: Thumb2 support.
44

--- 199 unchanged lines hidden (view full) ---

244 if (AllowModify)
245 I->eraseFromParent();
246 return false;
247 }
248
249 // ...likewise if it ends with a branch table followed by an unconditional
250 // branch. The branch folder can create these, and we must get rid of them for
251 // correctness of Thumb constant islands.
40}
41
42MachineInstr *
43ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
44 MachineBasicBlock::iterator &MBBI,
45 LiveVariables *LV) const {
46 // FIXME: Thumb2 support.
47

--- 199 unchanged lines hidden (view full) ---

247 if (AllowModify)
248 I->eraseFromParent();
249 return false;
250 }
251
252 // ...likewise if it ends with a branch table followed by an unconditional
253 // branch. The branch folder can create these, and we must get rid of them for
254 // correctness of Thumb constant islands.
252 if (isJumpTableBranchOpcode(SecondLastOpc) &&
255 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
256 isIndirectBranchOpcode(SecondLastOpc)) &&
253 isUncondBranchOpcode(LastOpc)) {
254 I = LastInst;
255 if (AllowModify)
256 I->eraseFromParent();
257 return true;
258 }
259
260 // Otherwise, can't handle this.

--- 178 unchanged lines hidden (view full) ---

439 switch (Opc) {
440 case ARM::CONSTPOOL_ENTRY:
441 // If this machine instr is a constant pool entry, its size is recorded as
442 // operand #2.
443 return MI->getOperand(2).getImm();
444 case ARM::Int_eh_sjlj_setjmp:
445 return 24;
446 case ARM::t2Int_eh_sjlj_setjmp:
257 isUncondBranchOpcode(LastOpc)) {
258 I = LastInst;
259 if (AllowModify)
260 I->eraseFromParent();
261 return true;
262 }
263
264 // Otherwise, can't handle this.

--- 178 unchanged lines hidden (view full) ---

443 switch (Opc) {
444 case ARM::CONSTPOOL_ENTRY:
445 // If this machine instr is a constant pool entry, its size is recorded as
446 // operand #2.
447 return MI->getOperand(2).getImm();
448 case ARM::Int_eh_sjlj_setjmp:
449 return 24;
450 case ARM::t2Int_eh_sjlj_setjmp:
447 return 20;
451 return 22;
448 case ARM::BR_JTr:
449 case ARM::BR_JTm:
450 case ARM::BR_JTadd:
451 case ARM::tBR_JTr:
452 case ARM::t2BR_JT:
453 case ARM::t2TBB:
454 case ARM::t2TBH: {
455 // These are jumptable branches, i.e. a branch followed by an inlined

--- 42 unchanged lines hidden (view full) ---

498 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
499 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
500
501 switch (MI.getOpcode()) {
502 default: break;
503 case ARM::FCPYS:
504 case ARM::FCPYD:
505 case ARM::VMOVD:
452 case ARM::BR_JTr:
453 case ARM::BR_JTm:
454 case ARM::BR_JTadd:
455 case ARM::tBR_JTr:
456 case ARM::t2BR_JT:
457 case ARM::t2TBB:
458 case ARM::t2TBH: {
459 // These are jumptable branches, i.e. a branch followed by an inlined

--- 42 unchanged lines hidden (view full) ---

502 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
503 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
504
505 switch (MI.getOpcode()) {
506 default: break;
507 case ARM::FCPYS:
508 case ARM::FCPYD:
509 case ARM::VMOVD:
506 case ARM::VMOVQ: {
510 case ARM::VMOVQ: {
507 SrcReg = MI.getOperand(1).getReg();
508 DstReg = MI.getOperand(0).getReg();
509 return true;
510 }
511 case ARM::MOVr:
512 case ARM::tMOVr:
513 case ARM::tMOVgpr2tgpr:
514 case ARM::tMOVtgpr2gpr:

--- 95 unchanged lines hidden (view full) ---

610 MachineBasicBlock::iterator I,
611 unsigned DestReg, unsigned SrcReg,
612 const TargetRegisterClass *DestRC,
613 const TargetRegisterClass *SrcRC) const {
614 DebugLoc DL = DebugLoc::getUnknownLoc();
615 if (I != MBB.end()) DL = I->getDebugLoc();
616
617 if (DestRC != SrcRC) {
511 SrcReg = MI.getOperand(1).getReg();
512 DstReg = MI.getOperand(0).getReg();
513 return true;
514 }
515 case ARM::MOVr:
516 case ARM::tMOVr:
517 case ARM::tMOVgpr2tgpr:
518 case ARM::tMOVtgpr2gpr:

--- 95 unchanged lines hidden (view full) ---

614 MachineBasicBlock::iterator I,
615 unsigned DestReg, unsigned SrcReg,
616 const TargetRegisterClass *DestRC,
617 const TargetRegisterClass *SrcRC) const {
618 DebugLoc DL = DebugLoc::getUnknownLoc();
619 if (I != MBB.end()) DL = I->getDebugLoc();
620
621 if (DestRC != SrcRC) {
618 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies
619 // Allow QPR / QPR_VFP2 cross-class copies
620 if (DestRC == ARM::DPRRegisterClass) {
621 if (SrcRC == ARM::DPR_VFP2RegisterClass ||
622 SrcRC == ARM::DPR_8RegisterClass) {
623 } else
624 return false;
625 } else if (DestRC == ARM::DPR_VFP2RegisterClass) {
626 if (SrcRC == ARM::DPRRegisterClass ||
627 SrcRC == ARM::DPR_8RegisterClass) {
628 } else
629 return false;
630 } else if (DestRC == ARM::DPR_8RegisterClass) {
631 if (SrcRC == ARM::DPRRegisterClass ||
632 SrcRC == ARM::DPR_VFP2RegisterClass) {
633 } else
634 return false;
635 } else if ((DestRC == ARM::QPRRegisterClass &&
636 SrcRC == ARM::QPR_VFP2RegisterClass) ||
637 (DestRC == ARM::QPR_VFP2RegisterClass &&
638 SrcRC == ARM::QPRRegisterClass)) {
639 } else
622 if (DestRC->getSize() != SrcRC->getSize())
640 return false;
623 return false;
624
625 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
626 // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
627 if (DestRC->getSize() != 8 && DestRC->getSize() != 16)
628 return false;
641 }
642
643 if (DestRC == ARM::GPRRegisterClass) {
644 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
645 DestReg).addReg(SrcReg)));
646 } else if (DestRC == ARM::SPRRegisterClass) {
647 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
648 .addReg(SrcReg));
629 }
630
631 if (DestRC == ARM::GPRRegisterClass) {
632 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
633 DestReg).addReg(SrcReg)));
634 } else if (DestRC == ARM::SPRRegisterClass) {
635 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
636 .addReg(SrcReg));
649 } else if ((DestRC == ARM::DPRRegisterClass) ||
650 (DestRC == ARM::DPR_VFP2RegisterClass) ||
651 (DestRC == ARM::DPR_8RegisterClass)) {
637 } else if (DestRC == ARM::DPRRegisterClass) {
652 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
653 .addReg(SrcReg));
638 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
639 .addReg(SrcReg));
640 } else if (DestRC == ARM::DPR_VFP2RegisterClass ||
641 DestRC == ARM::DPR_8RegisterClass ||
642 SrcRC == ARM::DPR_VFP2RegisterClass ||
643 SrcRC == ARM::DPR_8RegisterClass) {
644 // Always use neon reg-reg move if source or dest is NEON-only regclass.
645 BuildMI(MBB, I, DL, get(ARM::VMOVD), DestReg).addReg(SrcReg);
654 } else if (DestRC == ARM::QPRRegisterClass ||
646 } else if (DestRC == ARM::QPRRegisterClass ||
655 DestRC == ARM::QPR_VFP2RegisterClass) {
647 DestRC == ARM::QPR_VFP2RegisterClass ||
648 DestRC == ARM::QPR_8RegisterClass) {
656 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
657 } else {
658 return false;
659 }
660
661 return true;
662}
663

--- 58 unchanged lines hidden (view full) ---

722 RC == ARM::DPR_8RegisterClass) {
723 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
724 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
725 } else if (RC == ARM::SPRRegisterClass) {
726 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
727 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
728 } else {
729 assert((RC == ARM::QPRRegisterClass ||
649 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
650 } else {
651 return false;
652 }
653
654 return true;
655}
656

--- 58 unchanged lines hidden (view full) ---

715 RC == ARM::DPR_8RegisterClass) {
716 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
717 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
718 } else if (RC == ARM::SPRRegisterClass) {
719 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
720 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
721 } else {
722 assert((RC == ARM::QPRRegisterClass ||
730 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
723 RC == ARM::QPR_VFP2RegisterClass ||
724 RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
731 // FIXME: Neon instructions should support predicates
725 // FIXME: Neon instructions should support predicates
732 BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO);
726 BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0).
727 addMemOperand(MMO);
733 }
734}
735
736MachineInstr *ARMBaseInstrInfo::
737foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
738 const SmallVectorImpl<unsigned> &Ops, int FI) const {
739 if (Ops.size() != 1) return NULL;
740
741 unsigned OpNum = Ops[0];
742 unsigned Opc = MI->getOpcode();
743 MachineInstr *NewMI = NULL;
744 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
745 // If it is updating CPSR, then it cannot be folded.
746 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
747 return NULL;
748 unsigned Pred = MI->getOperand(2).getImm();
749 unsigned PredReg = MI->getOperand(3).getReg();
750 if (OpNum == 0) { // move -> store
751 unsigned SrcReg = MI->getOperand(1).getReg();
728 }
729}
730
731MachineInstr *ARMBaseInstrInfo::
732foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
733 const SmallVectorImpl<unsigned> &Ops, int FI) const {
734 if (Ops.size() != 1) return NULL;
735
736 unsigned OpNum = Ops[0];
737 unsigned Opc = MI->getOpcode();
738 MachineInstr *NewMI = NULL;
739 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
740 // If it is updating CPSR, then it cannot be folded.
741 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
742 return NULL;
743 unsigned Pred = MI->getOperand(2).getImm();
744 unsigned PredReg = MI->getOperand(3).getReg();
745 if (OpNum == 0) { // move -> store
746 unsigned SrcReg = MI->getOperand(1).getReg();
747 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
752 bool isKill = MI->getOperand(1).isKill();
753 bool isUndef = MI->getOperand(1).isUndef();
754 if (Opc == ARM::MOVr)
755 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
748 bool isKill = MI->getOperand(1).isKill();
749 bool isUndef = MI->getOperand(1).isUndef();
750 if (Opc == ARM::MOVr)
751 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
756 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
752 .addReg(SrcReg,
753 getKillRegState(isKill) | getUndefRegState(isUndef),
754 SrcSubReg)
757 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
758 else // ARM::t2MOVr
759 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
755 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
756 else // ARM::t2MOVr
757 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
760 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
758 .addReg(SrcReg,
759 getKillRegState(isKill) | getUndefRegState(isUndef),
760 SrcSubReg)
761 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
762 } else { // move -> load
763 unsigned DstReg = MI->getOperand(0).getReg();
761 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
762 } else { // move -> load
763 unsigned DstReg = MI->getOperand(0).getReg();
764 unsigned DstSubReg = MI->getOperand(0).getSubReg();
764 bool isDead = MI->getOperand(0).isDead();
765 bool isUndef = MI->getOperand(0).isUndef();
766 if (Opc == ARM::MOVr)
767 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
768 .addReg(DstReg,
769 RegState::Define |
770 getDeadRegState(isDead) |
765 bool isDead = MI->getOperand(0).isDead();
766 bool isUndef = MI->getOperand(0).isUndef();
767 if (Opc == ARM::MOVr)
768 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
769 .addReg(DstReg,
770 RegState::Define |
771 getDeadRegState(isDead) |
771 getUndefRegState(isUndef))
772 getUndefRegState(isUndef), DstSubReg)
772 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
773 else // ARM::t2MOVr
774 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
775 .addReg(DstReg,
776 RegState::Define |
777 getDeadRegState(isDead) |
773 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
774 else // ARM::t2MOVr
775 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
776 .addReg(DstReg,
777 RegState::Define |
778 getDeadRegState(isDead) |
778 getUndefRegState(isUndef))
779 getUndefRegState(isUndef), DstSubReg)
779 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
780 }
781 } else if (Opc == ARM::tMOVgpr2gpr ||
782 Opc == ARM::tMOVtgpr2gpr ||
783 Opc == ARM::tMOVgpr2tgpr) {
784 if (OpNum == 0) { // move -> store
785 unsigned SrcReg = MI->getOperand(1).getReg();
780 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
781 }
782 } else if (Opc == ARM::tMOVgpr2gpr ||
783 Opc == ARM::tMOVtgpr2gpr ||
784 Opc == ARM::tMOVgpr2tgpr) {
785 if (OpNum == 0) { // move -> store
786 unsigned SrcReg = MI->getOperand(1).getReg();
787 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
786 bool isKill = MI->getOperand(1).isKill();
787 bool isUndef = MI->getOperand(1).isUndef();
788 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
788 bool isKill = MI->getOperand(1).isKill();
789 bool isUndef = MI->getOperand(1).isUndef();
790 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
789 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
791 .addReg(SrcReg,
792 getKillRegState(isKill) | getUndefRegState(isUndef),
793 SrcSubReg)
790 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
791 } else { // move -> load
792 unsigned DstReg = MI->getOperand(0).getReg();
794 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
795 } else { // move -> load
796 unsigned DstReg = MI->getOperand(0).getReg();
797 unsigned DstSubReg = MI->getOperand(0).getSubReg();
793 bool isDead = MI->getOperand(0).isDead();
794 bool isUndef = MI->getOperand(0).isUndef();
795 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
796 .addReg(DstReg,
797 RegState::Define |
798 getDeadRegState(isDead) |
798 bool isDead = MI->getOperand(0).isDead();
799 bool isUndef = MI->getOperand(0).isUndef();
800 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
801 .addReg(DstReg,
802 RegState::Define |
803 getDeadRegState(isDead) |
799 getUndefRegState(isUndef))
804 getUndefRegState(isUndef),
805 DstSubReg)
800 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
801 }
802 } else if (Opc == ARM::FCPYS) {
803 unsigned Pred = MI->getOperand(2).getImm();
804 unsigned PredReg = MI->getOperand(3).getReg();
805 if (OpNum == 0) { // move -> store
806 unsigned SrcReg = MI->getOperand(1).getReg();
806 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
807 }
808 } else if (Opc == ARM::FCPYS) {
809 unsigned Pred = MI->getOperand(2).getImm();
810 unsigned PredReg = MI->getOperand(3).getReg();
811 if (OpNum == 0) { // move -> store
812 unsigned SrcReg = MI->getOperand(1).getReg();
813 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
807 bool isKill = MI->getOperand(1).isKill();
808 bool isUndef = MI->getOperand(1).isUndef();
809 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
814 bool isKill = MI->getOperand(1).isKill();
815 bool isUndef = MI->getOperand(1).isUndef();
816 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
810 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
817 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
818 SrcSubReg)
811 .addFrameIndex(FI)
812 .addImm(0).addImm(Pred).addReg(PredReg);
813 } else { // move -> load
814 unsigned DstReg = MI->getOperand(0).getReg();
819 .addFrameIndex(FI)
820 .addImm(0).addImm(Pred).addReg(PredReg);
821 } else { // move -> load
822 unsigned DstReg = MI->getOperand(0).getReg();
823 unsigned DstSubReg = MI->getOperand(0).getSubReg();
815 bool isDead = MI->getOperand(0).isDead();
816 bool isUndef = MI->getOperand(0).isUndef();
817 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
818 .addReg(DstReg,
819 RegState::Define |
820 getDeadRegState(isDead) |
824 bool isDead = MI->getOperand(0).isDead();
825 bool isUndef = MI->getOperand(0).isUndef();
826 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
827 .addReg(DstReg,
828 RegState::Define |
829 getDeadRegState(isDead) |
821 getUndefRegState(isUndef))
830 getUndefRegState(isUndef),
831 DstSubReg)
822 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
823 }
824 }
825 else if (Opc == ARM::FCPYD) {
826 unsigned Pred = MI->getOperand(2).getImm();
827 unsigned PredReg = MI->getOperand(3).getReg();
828 if (OpNum == 0) { // move -> store
829 unsigned SrcReg = MI->getOperand(1).getReg();
832 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
833 }
834 }
835 else if (Opc == ARM::FCPYD) {
836 unsigned Pred = MI->getOperand(2).getImm();
837 unsigned PredReg = MI->getOperand(3).getReg();
838 if (OpNum == 0) { // move -> store
839 unsigned SrcReg = MI->getOperand(1).getReg();
840 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
830 bool isKill = MI->getOperand(1).isKill();
831 bool isUndef = MI->getOperand(1).isUndef();
832 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
841 bool isKill = MI->getOperand(1).isKill();
842 bool isUndef = MI->getOperand(1).isUndef();
843 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
833 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
844 .addReg(SrcReg,
845 getKillRegState(isKill) | getUndefRegState(isUndef),
846 SrcSubReg)
834 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
835 } else { // move -> load
836 unsigned DstReg = MI->getOperand(0).getReg();
847 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
848 } else { // move -> load
849 unsigned DstReg = MI->getOperand(0).getReg();
850 unsigned DstSubReg = MI->getOperand(0).getSubReg();
837 bool isDead = MI->getOperand(0).isDead();
838 bool isUndef = MI->getOperand(0).isUndef();
839 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
840 .addReg(DstReg,
841 RegState::Define |
842 getDeadRegState(isDead) |
851 bool isDead = MI->getOperand(0).isDead();
852 bool isUndef = MI->getOperand(0).isUndef();
853 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
854 .addReg(DstReg,
855 RegState::Define |
856 getDeadRegState(isDead) |
843 getUndefRegState(isUndef))
857 getUndefRegState(isUndef),
858 DstSubReg)
844 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
845 }
846 }
847
848 return NewMI;
849}
850
851MachineInstr*

--- 209 unchanged lines hidden --- 		859 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
860 }
861 }
862
863 return NewMI;
864}
865
866MachineInstr*

--- 209 unchanged lines hidden ---