1//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Base ARM implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMBaseInstrInfo.h" 15#include "ARM.h" 16#include "ARMAddressingModes.h" 17#include "ARMGenInstrInfo.inc" 18#include "ARMMachineFunctionInfo.h"
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19#include "ARMRegisterInfo.h" |
20#include "llvm/ADT/STLExtras.h" 21#include "llvm/CodeGen/LiveVariables.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/MachineJumpTableInfo.h" 25#include "llvm/CodeGen/MachineMemOperand.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/MC/MCAsmInfo.h" 28#include "llvm/Support/CommandLine.h"
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29#include "llvm/Support/Debug.h" |
30#include "llvm/Support/ErrorHandling.h" 31using namespace llvm; 32 33static cl::opt<bool> 34EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 35 cl::desc("Enable ARM 2-addr to 3-addr conv")); 36
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35ARMBaseInstrInfo::ARMBaseInstrInfo()
36 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) {
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37ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 38 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), 39 Subtarget(STI) { |
40} 41 42MachineInstr * 43ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 44 MachineBasicBlock::iterator &MBBI, 45 LiveVariables *LV) const { 46 // FIXME: Thumb2 support. 47 48 if (!EnableARM3Addr) 49 return NULL; 50 51 MachineInstr *MI = MBBI; 52 MachineFunction &MF = *MI->getParent()->getParent(); 53 unsigned TSFlags = MI->getDesc().TSFlags; 54 bool isPre = false; 55 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 56 default: return NULL; 57 case ARMII::IndexModePre: 58 isPre = true; 59 break; 60 case ARMII::IndexModePost: 61 break; 62 } 63 64 // Try splitting an indexed load/store to an un-indexed one plus an add/sub 65 // operation. 66 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 67 if (MemOpc == 0) 68 return NULL; 69 70 MachineInstr *UpdateMI = NULL; 71 MachineInstr *MemMI = NULL; 72 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 73 const TargetInstrDesc &TID = MI->getDesc(); 74 unsigned NumOps = TID.getNumOperands(); 75 bool isLoad = !TID.mayStore(); 76 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 77 const MachineOperand &Base = MI->getOperand(2); 78 const MachineOperand &Offset = MI->getOperand(NumOps-3); 79 unsigned WBReg = WB.getReg(); 80 unsigned BaseReg = Base.getReg(); 81 unsigned OffReg = Offset.getReg(); 82 unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 83 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 84 switch (AddrMode) { 85 default: 86 assert(false && "Unknown indexed op!"); 87 return NULL; 88 case ARMII::AddrMode2: { 89 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 90 unsigned Amt = ARM_AM::getAM2Offset(OffImm); 91 if (OffReg == 0) { 92 if (ARM_AM::getSOImmVal(Amt) == -1) 93 // Can't encode it in a so_imm operand. This transformation will 94 // add more than 1 instruction. Abandon! 95 return NULL; 96 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 97 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 98 .addReg(BaseReg).addImm(Amt) 99 .addImm(Pred).addReg(0).addReg(0); 100 } else if (Amt != 0) { 101 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 102 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 103 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 104 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 105 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 106 .addImm(Pred).addReg(0).addReg(0); 107 } else 108 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 109 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 110 .addReg(BaseReg).addReg(OffReg) 111 .addImm(Pred).addReg(0).addReg(0); 112 break; 113 } 114 case ARMII::AddrMode3 : { 115 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 116 unsigned Amt = ARM_AM::getAM3Offset(OffImm); 117 if (OffReg == 0) 118 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 119 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 120 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 121 .addReg(BaseReg).addImm(Amt) 122 .addImm(Pred).addReg(0).addReg(0); 123 else 124 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 125 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 126 .addReg(BaseReg).addReg(OffReg) 127 .addImm(Pred).addReg(0).addReg(0); 128 break; 129 } 130 } 131 132 std::vector<MachineInstr*> NewMIs; 133 if (isPre) { 134 if (isLoad) 135 MemMI = BuildMI(MF, MI->getDebugLoc(), 136 get(MemOpc), MI->getOperand(0).getReg()) 137 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 138 else 139 MemMI = BuildMI(MF, MI->getDebugLoc(), 140 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 141 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 142 NewMIs.push_back(MemMI); 143 NewMIs.push_back(UpdateMI); 144 } else { 145 if (isLoad) 146 MemMI = BuildMI(MF, MI->getDebugLoc(), 147 get(MemOpc), MI->getOperand(0).getReg()) 148 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 149 else 150 MemMI = BuildMI(MF, MI->getDebugLoc(), 151 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 152 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 153 if (WB.isDead()) 154 UpdateMI->getOperand(0).setIsDead(); 155 NewMIs.push_back(UpdateMI); 156 NewMIs.push_back(MemMI); 157 } 158 159 // Transfer LiveVariables states, kill / dead info. 160 if (LV) { 161 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 162 MachineOperand &MO = MI->getOperand(i); 163 if (MO.isReg() && MO.getReg() && 164 TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 165 unsigned Reg = MO.getReg(); 166 167 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 168 if (MO.isDef()) { 169 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 170 if (MO.isDead()) 171 LV->addVirtualRegisterDead(Reg, NewMI); 172 } 173 if (MO.isUse() && MO.isKill()) { 174 for (unsigned j = 0; j < 2; ++j) { 175 // Look at the two new MI's in reverse order. 176 MachineInstr *NewMI = NewMIs[j]; 177 if (!NewMI->readsRegister(Reg)) 178 continue; 179 LV->addVirtualRegisterKilled(Reg, NewMI); 180 if (VI.removeKill(MI)) 181 VI.Kills.push_back(NewMI); 182 break; 183 } 184 } 185 } 186 } 187 } 188 189 MFI->insert(MBBI, NewMIs[1]); 190 MFI->insert(MBBI, NewMIs[0]); 191 return NewMIs[0]; 192} 193 194// Branch analysis. 195bool 196ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 197 MachineBasicBlock *&FBB, 198 SmallVectorImpl<MachineOperand> &Cond, 199 bool AllowModify) const { 200 // If the block has no terminators, it just falls into the block after it. 201 MachineBasicBlock::iterator I = MBB.end(); 202 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) 203 return false; 204 205 // Get the last instruction in the block. 206 MachineInstr *LastInst = I; 207 208 // If there is only one terminator instruction, process it. 209 unsigned LastOpc = LastInst->getOpcode(); 210 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 211 if (isUncondBranchOpcode(LastOpc)) { 212 TBB = LastInst->getOperand(0).getMBB(); 213 return false; 214 } 215 if (isCondBranchOpcode(LastOpc)) { 216 // Block ends with fall-through condbranch. 217 TBB = LastInst->getOperand(0).getMBB(); 218 Cond.push_back(LastInst->getOperand(1)); 219 Cond.push_back(LastInst->getOperand(2)); 220 return false; 221 } 222 return true; // Can't handle indirect branch. 223 } 224 225 // Get the instruction before it if it is a terminator. 226 MachineInstr *SecondLastInst = I; 227 228 // If there are three terminators, we don't know what sort of block this is. 229 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 230 return true; 231 232 // If the block ends with a B and a Bcc, handle it. 233 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 234 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 235 TBB = SecondLastInst->getOperand(0).getMBB(); 236 Cond.push_back(SecondLastInst->getOperand(1)); 237 Cond.push_back(SecondLastInst->getOperand(2)); 238 FBB = LastInst->getOperand(0).getMBB(); 239 return false; 240 } 241 242 // If the block ends with two unconditional branches, handle it. The second 243 // one is not executed, so remove it. 244 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 245 TBB = SecondLastInst->getOperand(0).getMBB(); 246 I = LastInst; 247 if (AllowModify) 248 I->eraseFromParent(); 249 return false; 250 } 251 252 // ...likewise if it ends with a branch table followed by an unconditional 253 // branch. The branch folder can create these, and we must get rid of them for 254 // correctness of Thumb constant islands.
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252 if (isJumpTableBranchOpcode(SecondLastOpc) &&
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255 if ((isJumpTableBranchOpcode(SecondLastOpc) || 256 isIndirectBranchOpcode(SecondLastOpc)) && |
257 isUncondBranchOpcode(LastOpc)) { 258 I = LastInst; 259 if (AllowModify) 260 I->eraseFromParent(); 261 return true; 262 } 263 264 // Otherwise, can't handle this. 265 return true; 266} 267 268 269unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 270 MachineBasicBlock::iterator I = MBB.end(); 271 if (I == MBB.begin()) return 0; 272 --I; 273 if (!isUncondBranchOpcode(I->getOpcode()) && 274 !isCondBranchOpcode(I->getOpcode())) 275 return 0; 276 277 // Remove the branch. 278 I->eraseFromParent(); 279 280 I = MBB.end(); 281 282 if (I == MBB.begin()) return 1; 283 --I; 284 if (!isCondBranchOpcode(I->getOpcode())) 285 return 1; 286 287 // Remove the branch. 288 I->eraseFromParent(); 289 return 2; 290} 291 292unsigned 293ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 294 MachineBasicBlock *FBB, 295 const SmallVectorImpl<MachineOperand> &Cond) const { 296 // FIXME this should probably have a DebugLoc argument 297 DebugLoc dl = DebugLoc::getUnknownLoc(); 298 299 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 300 int BOpc = !AFI->isThumbFunction() 301 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 302 int BccOpc = !AFI->isThumbFunction() 303 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 304 305 // Shouldn't be a fall through. 306 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 307 assert((Cond.size() == 2 || Cond.size() == 0) && 308 "ARM branch conditions have two components!"); 309 310 if (FBB == 0) { 311 if (Cond.empty()) // Unconditional branch? 312 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB); 313 else 314 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 315 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 316 return 1; 317 } 318 319 // Two-way conditional branch. 320 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 321 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 322 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB); 323 return 2; 324} 325 326bool ARMBaseInstrInfo:: 327ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 328 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 329 Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 330 return false; 331} 332 333bool ARMBaseInstrInfo:: 334PredicateInstruction(MachineInstr *MI, 335 const SmallVectorImpl<MachineOperand> &Pred) const { 336 unsigned Opc = MI->getOpcode(); 337 if (isUncondBranchOpcode(Opc)) { 338 MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 339 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 340 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 341 return true; 342 } 343 344 int PIdx = MI->findFirstPredOperandIdx(); 345 if (PIdx != -1) { 346 MachineOperand &PMO = MI->getOperand(PIdx); 347 PMO.setImm(Pred[0].getImm()); 348 MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 349 return true; 350 } 351 return false; 352} 353 354bool ARMBaseInstrInfo:: 355SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 356 const SmallVectorImpl<MachineOperand> &Pred2) const { 357 if (Pred1.size() > 2 || Pred2.size() > 2) 358 return false; 359 360 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 361 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 362 if (CC1 == CC2) 363 return true; 364 365 switch (CC1) { 366 default: 367 return false; 368 case ARMCC::AL: 369 return true; 370 case ARMCC::HS: 371 return CC2 == ARMCC::HI; 372 case ARMCC::LS: 373 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 374 case ARMCC::GE: 375 return CC2 == ARMCC::GT; 376 case ARMCC::LE: 377 return CC2 == ARMCC::LT; 378 } 379} 380 381bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 382 std::vector<MachineOperand> &Pred) const { 383 // FIXME: This confuses implicit_def with optional CPSR def. 384 const TargetInstrDesc &TID = MI->getDesc(); 385 if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 386 return false; 387 388 bool Found = false; 389 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 390 const MachineOperand &MO = MI->getOperand(i); 391 if (MO.isReg() && MO.getReg() == ARM::CPSR) { 392 Pred.push_back(MO); 393 Found = true; 394 } 395 } 396 397 return Found; 398} 399 400 401/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing 402static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 403 unsigned JTI) DISABLE_INLINE; 404static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 405 unsigned JTI) { 406 return JT[JTI].MBBs.size(); 407} 408 409/// GetInstSize - Return the size of the specified MachineInstr. 410/// 411unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 412 const MachineBasicBlock &MBB = *MI->getParent(); 413 const MachineFunction *MF = MBB.getParent(); 414 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 415 416 // Basic size info comes from the TSFlags field. 417 const TargetInstrDesc &TID = MI->getDesc(); 418 unsigned TSFlags = TID.TSFlags; 419 420 unsigned Opc = MI->getOpcode(); 421 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 422 default: { 423 // If this machine instr is an inline asm, measure it. 424 if (MI->getOpcode() == ARM::INLINEASM) 425 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 426 if (MI->isLabel()) 427 return 0; 428 switch (Opc) { 429 default: 430 llvm_unreachable("Unknown or unset size field for instr!"); 431 case TargetInstrInfo::IMPLICIT_DEF: 432 case TargetInstrInfo::KILL: 433 case TargetInstrInfo::DBG_LABEL: 434 case TargetInstrInfo::EH_LABEL: 435 return 0; 436 } 437 break; 438 } 439 case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 440 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 441 case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 442 case ARMII::SizeSpecial: { 443 switch (Opc) { 444 case ARM::CONSTPOOL_ENTRY: 445 // If this machine instr is a constant pool entry, its size is recorded as 446 // operand #2. 447 return MI->getOperand(2).getImm(); 448 case ARM::Int_eh_sjlj_setjmp: 449 return 24; 450 case ARM::t2Int_eh_sjlj_setjmp:
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447 return 20;
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451 return 22; |
452 case ARM::BR_JTr: 453 case ARM::BR_JTm: 454 case ARM::BR_JTadd: 455 case ARM::tBR_JTr: 456 case ARM::t2BR_JT: 457 case ARM::t2TBB: 458 case ARM::t2TBH: { 459 // These are jumptable branches, i.e. a branch followed by an inlined 460 // jumptable. The size is 4 + 4 * number of entries. For TBB, each 461 // entry is one byte; TBH two byte each. 462 unsigned EntrySize = (Opc == ARM::t2TBB) 463 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4); 464 unsigned NumOps = TID.getNumOperands(); 465 MachineOperand JTOP = 466 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 467 unsigned JTI = JTOP.getIndex(); 468 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 469 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 470 assert(JTI < JT.size()); 471 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 472 // 4 aligned. The assembler / linker may add 2 byte padding just before 473 // the JT entries. The size does not include this padding; the 474 // constant islands pass does separate bookkeeping for it. 475 // FIXME: If we know the size of the function is less than (1 << 16) *2 476 // bytes, we can use 16-bit entries instead. Then there won't be an 477 // alignment issue. 478 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 479 unsigned NumEntries = getNumJTEntries(JT, JTI); 480 if (Opc == ARM::t2TBB && (NumEntries & 1)) 481 // Make sure the instruction that follows TBB is 2-byte aligned. 482 // FIXME: Constant island pass should insert an "ALIGN" instruction 483 // instead. 484 ++NumEntries; 485 return NumEntries * EntrySize + InstSize; 486 } 487 default: 488 // Otherwise, pseudo-instruction sizes are zero. 489 return 0; 490 } 491 } 492 } 493 return 0; // Not reached 494} 495 496/// Return true if the instruction is a register to register move and 497/// leave the source and dest operands in the passed parameters. 498/// 499bool 500ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI, 501 unsigned &SrcReg, unsigned &DstReg, 502 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 503 SrcSubIdx = DstSubIdx = 0; // No sub-registers. 504 505 switch (MI.getOpcode()) { 506 default: break; 507 case ARM::FCPYS: 508 case ARM::FCPYD: 509 case ARM::VMOVD:
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506 case ARM::VMOVQ: {
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510 case ARM::VMOVQ: { |
511 SrcReg = MI.getOperand(1).getReg(); 512 DstReg = MI.getOperand(0).getReg(); 513 return true; 514 } 515 case ARM::MOVr: 516 case ARM::tMOVr: 517 case ARM::tMOVgpr2tgpr: 518 case ARM::tMOVtgpr2gpr: 519 case ARM::tMOVgpr2gpr: 520 case ARM::t2MOVr: { 521 assert(MI.getDesc().getNumOperands() >= 2 && 522 MI.getOperand(0).isReg() && 523 MI.getOperand(1).isReg() && 524 "Invalid ARM MOV instruction"); 525 SrcReg = MI.getOperand(1).getReg(); 526 DstReg = MI.getOperand(0).getReg(); 527 return true; 528 } 529 } 530 531 return false; 532} 533 534unsigned 535ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 536 int &FrameIndex) const { 537 switch (MI->getOpcode()) { 538 default: break; 539 case ARM::LDR: 540 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 541 if (MI->getOperand(1).isFI() && 542 MI->getOperand(2).isReg() && 543 MI->getOperand(3).isImm() && 544 MI->getOperand(2).getReg() == 0 && 545 MI->getOperand(3).getImm() == 0) { 546 FrameIndex = MI->getOperand(1).getIndex(); 547 return MI->getOperand(0).getReg(); 548 } 549 break; 550 case ARM::t2LDRi12: 551 case ARM::tRestore: 552 if (MI->getOperand(1).isFI() && 553 MI->getOperand(2).isImm() && 554 MI->getOperand(2).getImm() == 0) { 555 FrameIndex = MI->getOperand(1).getIndex(); 556 return MI->getOperand(0).getReg(); 557 } 558 break; 559 case ARM::FLDD: 560 case ARM::FLDS: 561 if (MI->getOperand(1).isFI() && 562 MI->getOperand(2).isImm() && 563 MI->getOperand(2).getImm() == 0) { 564 FrameIndex = MI->getOperand(1).getIndex(); 565 return MI->getOperand(0).getReg(); 566 } 567 break; 568 } 569 570 return 0; 571} 572 573unsigned 574ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 575 int &FrameIndex) const { 576 switch (MI->getOpcode()) { 577 default: break; 578 case ARM::STR: 579 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 580 if (MI->getOperand(1).isFI() && 581 MI->getOperand(2).isReg() && 582 MI->getOperand(3).isImm() && 583 MI->getOperand(2).getReg() == 0 && 584 MI->getOperand(3).getImm() == 0) { 585 FrameIndex = MI->getOperand(1).getIndex(); 586 return MI->getOperand(0).getReg(); 587 } 588 break; 589 case ARM::t2STRi12: 590 case ARM::tSpill: 591 if (MI->getOperand(1).isFI() && 592 MI->getOperand(2).isImm() && 593 MI->getOperand(2).getImm() == 0) { 594 FrameIndex = MI->getOperand(1).getIndex(); 595 return MI->getOperand(0).getReg(); 596 } 597 break; 598 case ARM::FSTD: 599 case ARM::FSTS: 600 if (MI->getOperand(1).isFI() && 601 MI->getOperand(2).isImm() && 602 MI->getOperand(2).getImm() == 0) { 603 FrameIndex = MI->getOperand(1).getIndex(); 604 return MI->getOperand(0).getReg(); 605 } 606 break; 607 } 608 609 return 0; 610} 611 612bool 613ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 614 MachineBasicBlock::iterator I, 615 unsigned DestReg, unsigned SrcReg, 616 const TargetRegisterClass *DestRC, 617 const TargetRegisterClass *SrcRC) const { 618 DebugLoc DL = DebugLoc::getUnknownLoc(); 619 if (I != MBB.end()) DL = I->getDebugLoc(); 620 621 if (DestRC != SrcRC) {
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618 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies
619 // Allow QPR / QPR_VFP2 cross-class copies
620 if (DestRC == ARM::DPRRegisterClass) {
621 if (SrcRC == ARM::DPR_VFP2RegisterClass ||
622 SrcRC == ARM::DPR_8RegisterClass) {
623 } else
624 return false;
625 } else if (DestRC == ARM::DPR_VFP2RegisterClass) {
626 if (SrcRC == ARM::DPRRegisterClass ||
627 SrcRC == ARM::DPR_8RegisterClass) {
628 } else
629 return false;
630 } else if (DestRC == ARM::DPR_8RegisterClass) {
631 if (SrcRC == ARM::DPRRegisterClass ||
632 SrcRC == ARM::DPR_VFP2RegisterClass) {
633 } else
634 return false;
635 } else if ((DestRC == ARM::QPRRegisterClass &&
636 SrcRC == ARM::QPR_VFP2RegisterClass) ||
637 (DestRC == ARM::QPR_VFP2RegisterClass &&
638 SrcRC == ARM::QPRRegisterClass)) {
639 } else
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622 if (DestRC->getSize() != SrcRC->getSize()) |
623 return false;
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624 625 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies. 626 // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies. 627 if (DestRC->getSize() != 8 && DestRC->getSize() != 16) 628 return false; |
629 } 630 631 if (DestRC == ARM::GPRRegisterClass) { 632 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), 633 DestReg).addReg(SrcReg))); 634 } else if (DestRC == ARM::SPRRegisterClass) { 635 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg) 636 .addReg(SrcReg));
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649 } else if ((DestRC == ARM::DPRRegisterClass) ||
650 (DestRC == ARM::DPR_VFP2RegisterClass) ||
651 (DestRC == ARM::DPR_8RegisterClass)) {
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637 } else if (DestRC == ARM::DPRRegisterClass) { |
638 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg) 639 .addReg(SrcReg));
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640 } else if (DestRC == ARM::DPR_VFP2RegisterClass || 641 DestRC == ARM::DPR_8RegisterClass || 642 SrcRC == ARM::DPR_VFP2RegisterClass || 643 SrcRC == ARM::DPR_8RegisterClass) { 644 // Always use neon reg-reg move if source or dest is NEON-only regclass. 645 BuildMI(MBB, I, DL, get(ARM::VMOVD), DestReg).addReg(SrcReg); |
646 } else if (DestRC == ARM::QPRRegisterClass ||
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655 DestRC == ARM::QPR_VFP2RegisterClass) {
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647 DestRC == ARM::QPR_VFP2RegisterClass || 648 DestRC == ARM::QPR_8RegisterClass) { |
649 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg); 650 } else { 651 return false; 652 } 653 654 return true; 655} 656 657void ARMBaseInstrInfo:: 658storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 659 unsigned SrcReg, bool isKill, int FI, 660 const TargetRegisterClass *RC) const { 661 DebugLoc DL = DebugLoc::getUnknownLoc(); 662 if (I != MBB.end()) DL = I->getDebugLoc(); 663 MachineFunction &MF = *MBB.getParent(); 664 MachineFrameInfo &MFI = *MF.getFrameInfo(); 665 666 MachineMemOperand *MMO = 667 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 668 MachineMemOperand::MOStore, 0, 669 MFI.getObjectSize(FI), 670 MFI.getObjectAlignment(FI)); 671 672 if (RC == ARM::GPRRegisterClass) { 673 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) 674 .addReg(SrcReg, getKillRegState(isKill)) 675 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 676 } else if (RC == ARM::DPRRegisterClass || 677 RC == ARM::DPR_VFP2RegisterClass || 678 RC == ARM::DPR_8RegisterClass) { 679 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD)) 680 .addReg(SrcReg, getKillRegState(isKill)) 681 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 682 } else if (RC == ARM::SPRRegisterClass) { 683 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS)) 684 .addReg(SrcReg, getKillRegState(isKill)) 685 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 686 } else { 687 assert((RC == ARM::QPRRegisterClass || 688 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!"); 689 // FIXME: Neon instructions should support predicates 690 BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill)) 691 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 692 } 693} 694 695void ARMBaseInstrInfo:: 696loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 697 unsigned DestReg, int FI, 698 const TargetRegisterClass *RC) const { 699 DebugLoc DL = DebugLoc::getUnknownLoc(); 700 if (I != MBB.end()) DL = I->getDebugLoc(); 701 MachineFunction &MF = *MBB.getParent(); 702 MachineFrameInfo &MFI = *MF.getFrameInfo(); 703 704 MachineMemOperand *MMO = 705 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 706 MachineMemOperand::MOLoad, 0, 707 MFI.getObjectSize(FI), 708 MFI.getObjectAlignment(FI)); 709 710 if (RC == ARM::GPRRegisterClass) { 711 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) 712 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 713 } else if (RC == ARM::DPRRegisterClass || 714 RC == ARM::DPR_VFP2RegisterClass || 715 RC == ARM::DPR_8RegisterClass) { 716 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg) 717 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 718 } else if (RC == ARM::SPRRegisterClass) { 719 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg) 720 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 721 } else { 722 assert((RC == ARM::QPRRegisterClass ||
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730 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
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723 RC == ARM::QPR_VFP2RegisterClass || 724 RC == ARM::QPR_8RegisterClass) && "Unknown regclass!"); |
725 // FIXME: Neon instructions should support predicates
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732 BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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726 BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0). 727 addMemOperand(MMO); |
728 } 729} 730 731MachineInstr *ARMBaseInstrInfo:: 732foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 733 const SmallVectorImpl<unsigned> &Ops, int FI) const { 734 if (Ops.size() != 1) return NULL; 735 736 unsigned OpNum = Ops[0]; 737 unsigned Opc = MI->getOpcode(); 738 MachineInstr *NewMI = NULL; 739 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 740 // If it is updating CPSR, then it cannot be folded. 741 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead()) 742 return NULL; 743 unsigned Pred = MI->getOperand(2).getImm(); 744 unsigned PredReg = MI->getOperand(3).getReg(); 745 if (OpNum == 0) { // move -> store 746 unsigned SrcReg = MI->getOperand(1).getReg();
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747 unsigned SrcSubReg = MI->getOperand(1).getSubReg(); |
748 bool isKill = MI->getOperand(1).isKill(); 749 bool isUndef = MI->getOperand(1).isUndef(); 750 if (Opc == ARM::MOVr) 751 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
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756 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
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752 .addReg(SrcReg, 753 getKillRegState(isKill) | getUndefRegState(isUndef), 754 SrcSubReg) |
755 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 756 else // ARM::t2MOVr 757 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
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760 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
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758 .addReg(SrcReg, 759 getKillRegState(isKill) | getUndefRegState(isUndef), 760 SrcSubReg) |
761 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 762 } else { // move -> load 763 unsigned DstReg = MI->getOperand(0).getReg();
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764 unsigned DstSubReg = MI->getOperand(0).getSubReg(); |
765 bool isDead = MI->getOperand(0).isDead(); 766 bool isUndef = MI->getOperand(0).isUndef(); 767 if (Opc == ARM::MOVr) 768 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) 769 .addReg(DstReg, 770 RegState::Define | 771 getDeadRegState(isDead) |
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771 getUndefRegState(isUndef))
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772 getUndefRegState(isUndef), DstSubReg) |
773 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 774 else // ARM::t2MOVr 775 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 776 .addReg(DstReg, 777 RegState::Define | 778 getDeadRegState(isDead) |
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778 getUndefRegState(isUndef))
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779 getUndefRegState(isUndef), DstSubReg) |
780 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 781 } 782 } else if (Opc == ARM::tMOVgpr2gpr || 783 Opc == ARM::tMOVtgpr2gpr || 784 Opc == ARM::tMOVgpr2tgpr) { 785 if (OpNum == 0) { // move -> store 786 unsigned SrcReg = MI->getOperand(1).getReg();
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787 unsigned SrcSubReg = MI->getOperand(1).getSubReg(); |
788 bool isKill = MI->getOperand(1).isKill(); 789 bool isUndef = MI->getOperand(1).isUndef(); 790 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
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789 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
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791 .addReg(SrcReg, 792 getKillRegState(isKill) | getUndefRegState(isUndef), 793 SrcSubReg) |
794 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 795 } else { // move -> load 796 unsigned DstReg = MI->getOperand(0).getReg();
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797 unsigned DstSubReg = MI->getOperand(0).getSubReg(); |
798 bool isDead = MI->getOperand(0).isDead(); 799 bool isUndef = MI->getOperand(0).isUndef(); 800 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 801 .addReg(DstReg, 802 RegState::Define | 803 getDeadRegState(isDead) |
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799 getUndefRegState(isUndef))
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804 getUndefRegState(isUndef), 805 DstSubReg) |
806 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 807 } 808 } else if (Opc == ARM::FCPYS) { 809 unsigned Pred = MI->getOperand(2).getImm(); 810 unsigned PredReg = MI->getOperand(3).getReg(); 811 if (OpNum == 0) { // move -> store 812 unsigned SrcReg = MI->getOperand(1).getReg();
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813 unsigned SrcSubReg = MI->getOperand(1).getSubReg(); |
814 bool isKill = MI->getOperand(1).isKill(); 815 bool isUndef = MI->getOperand(1).isUndef(); 816 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
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810 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
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817 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef), 818 SrcSubReg) |
819 .addFrameIndex(FI) 820 .addImm(0).addImm(Pred).addReg(PredReg); 821 } else { // move -> load 822 unsigned DstReg = MI->getOperand(0).getReg();
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823 unsigned DstSubReg = MI->getOperand(0).getSubReg(); |
824 bool isDead = MI->getOperand(0).isDead(); 825 bool isUndef = MI->getOperand(0).isUndef(); 826 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS)) 827 .addReg(DstReg, 828 RegState::Define | 829 getDeadRegState(isDead) |
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821 getUndefRegState(isUndef))
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830 getUndefRegState(isUndef), 831 DstSubReg) |
832 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 833 } 834 } 835 else if (Opc == ARM::FCPYD) { 836 unsigned Pred = MI->getOperand(2).getImm(); 837 unsigned PredReg = MI->getOperand(3).getReg(); 838 if (OpNum == 0) { // move -> store 839 unsigned SrcReg = MI->getOperand(1).getReg();
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840 unsigned SrcSubReg = MI->getOperand(1).getSubReg(); |
841 bool isKill = MI->getOperand(1).isKill(); 842 bool isUndef = MI->getOperand(1).isUndef(); 843 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
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833 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
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844 .addReg(SrcReg, 845 getKillRegState(isKill) | getUndefRegState(isUndef), 846 SrcSubReg) |
847 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 848 } else { // move -> load 849 unsigned DstReg = MI->getOperand(0).getReg();
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850 unsigned DstSubReg = MI->getOperand(0).getSubReg(); |
851 bool isDead = MI->getOperand(0).isDead(); 852 bool isUndef = MI->getOperand(0).isUndef(); 853 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD)) 854 .addReg(DstReg, 855 RegState::Define | 856 getDeadRegState(isDead) |
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843 getUndefRegState(isUndef))
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857 getUndefRegState(isUndef), 858 DstSubReg) |
859 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 860 } 861 } 862 863 return NewMI; 864} 865 866MachineInstr* 867ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 868 MachineInstr* MI, 869 const SmallVectorImpl<unsigned> &Ops, 870 MachineInstr* LoadMI) const { 871 // FIXME 872 return 0; 873} 874 875bool 876ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 877 const SmallVectorImpl<unsigned> &Ops) const { 878 if (Ops.size() != 1) return false; 879 880 unsigned Opc = MI->getOpcode(); 881 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 882 // If it is updating CPSR, then it cannot be folded. 883 return MI->getOperand(4).getReg() != ARM::CPSR || 884 MI->getOperand(4).isDead(); 885 } else if (Opc == ARM::tMOVgpr2gpr || 886 Opc == ARM::tMOVtgpr2gpr || 887 Opc == ARM::tMOVgpr2tgpr) { 888 return true; 889 } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) { 890 return true; 891 } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) { 892 return false; // FIXME 893 } 894 895 return false; 896} 897 898/// getInstrPredicate - If instruction is predicated, returns its predicate 899/// condition, otherwise returns AL. It also returns the condition code 900/// register by reference. 901ARMCC::CondCodes 902llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 903 int PIdx = MI->findFirstPredOperandIdx(); 904 if (PIdx == -1) { 905 PredReg = 0; 906 return ARMCC::AL; 907 } 908 909 PredReg = MI->getOperand(PIdx+1).getReg(); 910 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 911} 912 913 914int llvm::getMatchingCondBranchOpcode(int Opc) { 915 if (Opc == ARM::B) 916 return ARM::Bcc; 917 else if (Opc == ARM::tB) 918 return ARM::tBcc; 919 else if (Opc == ARM::t2B) 920 return ARM::t2Bcc; 921 922 llvm_unreachable("Unknown unconditional branch opcode!"); 923 return 0; 924} 925 926 927void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 928 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 929 unsigned DestReg, unsigned BaseReg, int NumBytes, 930 ARMCC::CondCodes Pred, unsigned PredReg, 931 const ARMBaseInstrInfo &TII) { 932 bool isSub = NumBytes < 0; 933 if (isSub) NumBytes = -NumBytes; 934 935 while (NumBytes) { 936 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 937 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 938 assert(ThisVal && "Didn't extract field correctly"); 939 940 // We will handle these bits from offset, clear them. 941 NumBytes &= ~ThisVal; 942 943 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 944 945 // Build the new ADD / SUB. 946 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 947 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 948 .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 949 .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 950 BaseReg = DestReg; 951 } 952} 953 954bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 955 unsigned FrameReg, int &Offset, 956 const ARMBaseInstrInfo &TII) { 957 unsigned Opcode = MI.getOpcode(); 958 const TargetInstrDesc &Desc = MI.getDesc(); 959 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 960 bool isSub = false; 961 962 // Memory operands in inline assembly always use AddrMode2. 963 if (Opcode == ARM::INLINEASM) 964 AddrMode = ARMII::AddrMode2; 965 966 if (Opcode == ARM::ADDri) { 967 Offset += MI.getOperand(FrameRegIdx+1).getImm(); 968 if (Offset == 0) { 969 // Turn it into a move. 970 MI.setDesc(TII.get(ARM::MOVr)); 971 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 972 MI.RemoveOperand(FrameRegIdx+1); 973 Offset = 0; 974 return true; 975 } else if (Offset < 0) { 976 Offset = -Offset; 977 isSub = true; 978 MI.setDesc(TII.get(ARM::SUBri)); 979 } 980 981 // Common case: small offset, fits into instruction. 982 if (ARM_AM::getSOImmVal(Offset) != -1) { 983 // Replace the FrameIndex with sp / fp 984 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 985 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 986 Offset = 0; 987 return true; 988 } 989 990 // Otherwise, pull as much of the immedidate into this ADDri/SUBri 991 // as possible. 992 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 993 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 994 995 // We will handle these bits from offset, clear them. 996 Offset &= ~ThisImmVal; 997 998 // Get the properly encoded SOImmVal field. 999 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 1000 "Bit extraction didn't work?"); 1001 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 1002 } else { 1003 unsigned ImmIdx = 0; 1004 int InstrOffs = 0; 1005 unsigned NumBits = 0; 1006 unsigned Scale = 1; 1007 switch (AddrMode) { 1008 case ARMII::AddrMode2: { 1009 ImmIdx = FrameRegIdx+2; 1010 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 1011 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1012 InstrOffs *= -1; 1013 NumBits = 12; 1014 break; 1015 } 1016 case ARMII::AddrMode3: { 1017 ImmIdx = FrameRegIdx+2; 1018 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 1019 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1020 InstrOffs *= -1; 1021 NumBits = 8; 1022 break; 1023 } 1024 case ARMII::AddrMode4: 1025 // Can't fold any offset even if it's zero. 1026 return false; 1027 case ARMII::AddrMode5: { 1028 ImmIdx = FrameRegIdx+1; 1029 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 1030 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1031 InstrOffs *= -1; 1032 NumBits = 8; 1033 Scale = 4; 1034 break; 1035 } 1036 default: 1037 llvm_unreachable("Unsupported addressing mode!"); 1038 break; 1039 } 1040 1041 Offset += InstrOffs * Scale; 1042 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 1043 if (Offset < 0) { 1044 Offset = -Offset; 1045 isSub = true; 1046 } 1047 1048 // Attempt to fold address comp. if opcode has offset bits 1049 if (NumBits > 0) { 1050 // Common case: small offset, fits into instruction. 1051 MachineOperand &ImmOp = MI.getOperand(ImmIdx); 1052 int ImmedOffset = Offset / Scale; 1053 unsigned Mask = (1 << NumBits) - 1; 1054 if ((unsigned)Offset <= Mask * Scale) { 1055 // Replace the FrameIndex with sp 1056 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1057 if (isSub) 1058 ImmedOffset |= 1 << NumBits; 1059 ImmOp.ChangeToImmediate(ImmedOffset); 1060 Offset = 0; 1061 return true; 1062 } 1063 1064 // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 1065 ImmedOffset = ImmedOffset & Mask; 1066 if (isSub) 1067 ImmedOffset |= 1 << NumBits; 1068 ImmOp.ChangeToImmediate(ImmedOffset); 1069 Offset &= ~(Mask*Scale); 1070 } 1071 } 1072 1073 Offset = (isSub) ? -Offset : Offset; 1074 return Offset == 0; 1075}
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