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ARMBaseInstrInfo.cpp (198090) ARMBaseInstrInfo.cpp (198892)
1//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMBaseInstrInfo.h"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMGenInstrInfo.inc"
18#include "ARMMachineFunctionInfo.h"
1//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMBaseInstrInfo.h"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMGenInstrInfo.inc"
18#include "ARMMachineFunctionInfo.h"
19#include "ARMRegisterInfo.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/CodeGen/LiveVariables.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineJumpTableInfo.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/MC/MCAsmInfo.h"
27#include "llvm/Support/CommandLine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/LiveVariables.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineJumpTableInfo.h"
25#include "llvm/CodeGen/MachineMemOperand.h"
26#include "llvm/CodeGen/PseudoSourceValue.h"
27#include "llvm/MC/MCAsmInfo.h"
28#include "llvm/Support/CommandLine.h"
29#include "llvm/Support/Debug.h"
28#include "llvm/Support/ErrorHandling.h"
29using namespace llvm;
30
31static cl::opt<bool>
32EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
33 cl::desc("Enable ARM 2-addr to 3-addr conv"));
34
30#include "llvm/Support/ErrorHandling.h"
31using namespace llvm;
32
33static cl::opt<bool>
34EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
35 cl::desc("Enable ARM 2-addr to 3-addr conv"));
36
35ARMBaseInstrInfo::ARMBaseInstrInfo()
36 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) {
37ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
38 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
39 Subtarget(STI) {
37}
38
39MachineInstr *
40ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
41 MachineBasicBlock::iterator &MBBI,
42 LiveVariables *LV) const {
43 // FIXME: Thumb2 support.
44
45 if (!EnableARM3Addr)
46 return NULL;
47
48 MachineInstr *MI = MBBI;
49 MachineFunction &MF = *MI->getParent()->getParent();
50 unsigned TSFlags = MI->getDesc().TSFlags;
51 bool isPre = false;
52 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
53 default: return NULL;
54 case ARMII::IndexModePre:
55 isPre = true;
56 break;
57 case ARMII::IndexModePost:
58 break;
59 }
60
61 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
62 // operation.
63 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
64 if (MemOpc == 0)
65 return NULL;
66
67 MachineInstr *UpdateMI = NULL;
68 MachineInstr *MemMI = NULL;
69 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
70 const TargetInstrDesc &TID = MI->getDesc();
71 unsigned NumOps = TID.getNumOperands();
72 bool isLoad = !TID.mayStore();
73 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
74 const MachineOperand &Base = MI->getOperand(2);
75 const MachineOperand &Offset = MI->getOperand(NumOps-3);
76 unsigned WBReg = WB.getReg();
77 unsigned BaseReg = Base.getReg();
78 unsigned OffReg = Offset.getReg();
79 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
80 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
81 switch (AddrMode) {
82 default:
83 assert(false && "Unknown indexed op!");
84 return NULL;
85 case ARMII::AddrMode2: {
86 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
87 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
88 if (OffReg == 0) {
89 if (ARM_AM::getSOImmVal(Amt) == -1)
90 // Can't encode it in a so_imm operand. This transformation will
91 // add more than 1 instruction. Abandon!
92 return NULL;
93 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
94 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
95 .addReg(BaseReg).addImm(Amt)
96 .addImm(Pred).addReg(0).addReg(0);
97 } else if (Amt != 0) {
98 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
99 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
100 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
101 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
102 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
103 .addImm(Pred).addReg(0).addReg(0);
104 } else
105 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
106 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
107 .addReg(BaseReg).addReg(OffReg)
108 .addImm(Pred).addReg(0).addReg(0);
109 break;
110 }
111 case ARMII::AddrMode3 : {
112 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
113 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
114 if (OffReg == 0)
115 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
116 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
117 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
118 .addReg(BaseReg).addImm(Amt)
119 .addImm(Pred).addReg(0).addReg(0);
120 else
121 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
122 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
123 .addReg(BaseReg).addReg(OffReg)
124 .addImm(Pred).addReg(0).addReg(0);
125 break;
126 }
127 }
128
129 std::vector<MachineInstr*> NewMIs;
130 if (isPre) {
131 if (isLoad)
132 MemMI = BuildMI(MF, MI->getDebugLoc(),
133 get(MemOpc), MI->getOperand(0).getReg())
134 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
135 else
136 MemMI = BuildMI(MF, MI->getDebugLoc(),
137 get(MemOpc)).addReg(MI->getOperand(1).getReg())
138 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
139 NewMIs.push_back(MemMI);
140 NewMIs.push_back(UpdateMI);
141 } else {
142 if (isLoad)
143 MemMI = BuildMI(MF, MI->getDebugLoc(),
144 get(MemOpc), MI->getOperand(0).getReg())
145 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
146 else
147 MemMI = BuildMI(MF, MI->getDebugLoc(),
148 get(MemOpc)).addReg(MI->getOperand(1).getReg())
149 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
150 if (WB.isDead())
151 UpdateMI->getOperand(0).setIsDead();
152 NewMIs.push_back(UpdateMI);
153 NewMIs.push_back(MemMI);
154 }
155
156 // Transfer LiveVariables states, kill / dead info.
157 if (LV) {
158 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
159 MachineOperand &MO = MI->getOperand(i);
160 if (MO.isReg() && MO.getReg() &&
161 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
162 unsigned Reg = MO.getReg();
163
164 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
165 if (MO.isDef()) {
166 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
167 if (MO.isDead())
168 LV->addVirtualRegisterDead(Reg, NewMI);
169 }
170 if (MO.isUse() && MO.isKill()) {
171 for (unsigned j = 0; j < 2; ++j) {
172 // Look at the two new MI's in reverse order.
173 MachineInstr *NewMI = NewMIs[j];
174 if (!NewMI->readsRegister(Reg))
175 continue;
176 LV->addVirtualRegisterKilled(Reg, NewMI);
177 if (VI.removeKill(MI))
178 VI.Kills.push_back(NewMI);
179 break;
180 }
181 }
182 }
183 }
184 }
185
186 MFI->insert(MBBI, NewMIs[1]);
187 MFI->insert(MBBI, NewMIs[0]);
188 return NewMIs[0];
189}
190
191// Branch analysis.
192bool
193ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
194 MachineBasicBlock *&FBB,
195 SmallVectorImpl<MachineOperand> &Cond,
196 bool AllowModify) const {
197 // If the block has no terminators, it just falls into the block after it.
198 MachineBasicBlock::iterator I = MBB.end();
199 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
200 return false;
201
202 // Get the last instruction in the block.
203 MachineInstr *LastInst = I;
204
205 // If there is only one terminator instruction, process it.
206 unsigned LastOpc = LastInst->getOpcode();
207 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
208 if (isUncondBranchOpcode(LastOpc)) {
209 TBB = LastInst->getOperand(0).getMBB();
210 return false;
211 }
212 if (isCondBranchOpcode(LastOpc)) {
213 // Block ends with fall-through condbranch.
214 TBB = LastInst->getOperand(0).getMBB();
215 Cond.push_back(LastInst->getOperand(1));
216 Cond.push_back(LastInst->getOperand(2));
217 return false;
218 }
219 return true; // Can't handle indirect branch.
220 }
221
222 // Get the instruction before it if it is a terminator.
223 MachineInstr *SecondLastInst = I;
224
225 // If there are three terminators, we don't know what sort of block this is.
226 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
227 return true;
228
229 // If the block ends with a B and a Bcc, handle it.
230 unsigned SecondLastOpc = SecondLastInst->getOpcode();
231 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
232 TBB = SecondLastInst->getOperand(0).getMBB();
233 Cond.push_back(SecondLastInst->getOperand(1));
234 Cond.push_back(SecondLastInst->getOperand(2));
235 FBB = LastInst->getOperand(0).getMBB();
236 return false;
237 }
238
239 // If the block ends with two unconditional branches, handle it. The second
240 // one is not executed, so remove it.
241 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
242 TBB = SecondLastInst->getOperand(0).getMBB();
243 I = LastInst;
244 if (AllowModify)
245 I->eraseFromParent();
246 return false;
247 }
248
249 // ...likewise if it ends with a branch table followed by an unconditional
250 // branch. The branch folder can create these, and we must get rid of them for
251 // correctness of Thumb constant islands.
40}
41
42MachineInstr *
43ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
44 MachineBasicBlock::iterator &MBBI,
45 LiveVariables *LV) const {
46 // FIXME: Thumb2 support.
47
48 if (!EnableARM3Addr)
49 return NULL;
50
51 MachineInstr *MI = MBBI;
52 MachineFunction &MF = *MI->getParent()->getParent();
53 unsigned TSFlags = MI->getDesc().TSFlags;
54 bool isPre = false;
55 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
56 default: return NULL;
57 case ARMII::IndexModePre:
58 isPre = true;
59 break;
60 case ARMII::IndexModePost:
61 break;
62 }
63
64 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
65 // operation.
66 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
67 if (MemOpc == 0)
68 return NULL;
69
70 MachineInstr *UpdateMI = NULL;
71 MachineInstr *MemMI = NULL;
72 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
73 const TargetInstrDesc &TID = MI->getDesc();
74 unsigned NumOps = TID.getNumOperands();
75 bool isLoad = !TID.mayStore();
76 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
77 const MachineOperand &Base = MI->getOperand(2);
78 const MachineOperand &Offset = MI->getOperand(NumOps-3);
79 unsigned WBReg = WB.getReg();
80 unsigned BaseReg = Base.getReg();
81 unsigned OffReg = Offset.getReg();
82 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
83 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
84 switch (AddrMode) {
85 default:
86 assert(false && "Unknown indexed op!");
87 return NULL;
88 case ARMII::AddrMode2: {
89 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
90 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
91 if (OffReg == 0) {
92 if (ARM_AM::getSOImmVal(Amt) == -1)
93 // Can't encode it in a so_imm operand. This transformation will
94 // add more than 1 instruction. Abandon!
95 return NULL;
96 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
97 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
98 .addReg(BaseReg).addImm(Amt)
99 .addImm(Pred).addReg(0).addReg(0);
100 } else if (Amt != 0) {
101 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
102 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
103 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
104 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
105 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
106 .addImm(Pred).addReg(0).addReg(0);
107 } else
108 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
109 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
110 .addReg(BaseReg).addReg(OffReg)
111 .addImm(Pred).addReg(0).addReg(0);
112 break;
113 }
114 case ARMII::AddrMode3 : {
115 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
116 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
117 if (OffReg == 0)
118 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
119 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
120 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
121 .addReg(BaseReg).addImm(Amt)
122 .addImm(Pred).addReg(0).addReg(0);
123 else
124 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
125 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
126 .addReg(BaseReg).addReg(OffReg)
127 .addImm(Pred).addReg(0).addReg(0);
128 break;
129 }
130 }
131
132 std::vector<MachineInstr*> NewMIs;
133 if (isPre) {
134 if (isLoad)
135 MemMI = BuildMI(MF, MI->getDebugLoc(),
136 get(MemOpc), MI->getOperand(0).getReg())
137 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
138 else
139 MemMI = BuildMI(MF, MI->getDebugLoc(),
140 get(MemOpc)).addReg(MI->getOperand(1).getReg())
141 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
142 NewMIs.push_back(MemMI);
143 NewMIs.push_back(UpdateMI);
144 } else {
145 if (isLoad)
146 MemMI = BuildMI(MF, MI->getDebugLoc(),
147 get(MemOpc), MI->getOperand(0).getReg())
148 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
149 else
150 MemMI = BuildMI(MF, MI->getDebugLoc(),
151 get(MemOpc)).addReg(MI->getOperand(1).getReg())
152 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
153 if (WB.isDead())
154 UpdateMI->getOperand(0).setIsDead();
155 NewMIs.push_back(UpdateMI);
156 NewMIs.push_back(MemMI);
157 }
158
159 // Transfer LiveVariables states, kill / dead info.
160 if (LV) {
161 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
162 MachineOperand &MO = MI->getOperand(i);
163 if (MO.isReg() && MO.getReg() &&
164 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
165 unsigned Reg = MO.getReg();
166
167 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
168 if (MO.isDef()) {
169 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
170 if (MO.isDead())
171 LV->addVirtualRegisterDead(Reg, NewMI);
172 }
173 if (MO.isUse() && MO.isKill()) {
174 for (unsigned j = 0; j < 2; ++j) {
175 // Look at the two new MI's in reverse order.
176 MachineInstr *NewMI = NewMIs[j];
177 if (!NewMI->readsRegister(Reg))
178 continue;
179 LV->addVirtualRegisterKilled(Reg, NewMI);
180 if (VI.removeKill(MI))
181 VI.Kills.push_back(NewMI);
182 break;
183 }
184 }
185 }
186 }
187 }
188
189 MFI->insert(MBBI, NewMIs[1]);
190 MFI->insert(MBBI, NewMIs[0]);
191 return NewMIs[0];
192}
193
194// Branch analysis.
195bool
196ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
197 MachineBasicBlock *&FBB,
198 SmallVectorImpl<MachineOperand> &Cond,
199 bool AllowModify) const {
200 // If the block has no terminators, it just falls into the block after it.
201 MachineBasicBlock::iterator I = MBB.end();
202 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
203 return false;
204
205 // Get the last instruction in the block.
206 MachineInstr *LastInst = I;
207
208 // If there is only one terminator instruction, process it.
209 unsigned LastOpc = LastInst->getOpcode();
210 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
211 if (isUncondBranchOpcode(LastOpc)) {
212 TBB = LastInst->getOperand(0).getMBB();
213 return false;
214 }
215 if (isCondBranchOpcode(LastOpc)) {
216 // Block ends with fall-through condbranch.
217 TBB = LastInst->getOperand(0).getMBB();
218 Cond.push_back(LastInst->getOperand(1));
219 Cond.push_back(LastInst->getOperand(2));
220 return false;
221 }
222 return true; // Can't handle indirect branch.
223 }
224
225 // Get the instruction before it if it is a terminator.
226 MachineInstr *SecondLastInst = I;
227
228 // If there are three terminators, we don't know what sort of block this is.
229 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
230 return true;
231
232 // If the block ends with a B and a Bcc, handle it.
233 unsigned SecondLastOpc = SecondLastInst->getOpcode();
234 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
235 TBB = SecondLastInst->getOperand(0).getMBB();
236 Cond.push_back(SecondLastInst->getOperand(1));
237 Cond.push_back(SecondLastInst->getOperand(2));
238 FBB = LastInst->getOperand(0).getMBB();
239 return false;
240 }
241
242 // If the block ends with two unconditional branches, handle it. The second
243 // one is not executed, so remove it.
244 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
245 TBB = SecondLastInst->getOperand(0).getMBB();
246 I = LastInst;
247 if (AllowModify)
248 I->eraseFromParent();
249 return false;
250 }
251
252 // ...likewise if it ends with a branch table followed by an unconditional
253 // branch. The branch folder can create these, and we must get rid of them for
254 // correctness of Thumb constant islands.
252 if (isJumpTableBranchOpcode(SecondLastOpc) &&
255 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
256 isIndirectBranchOpcode(SecondLastOpc)) &&
253 isUncondBranchOpcode(LastOpc)) {
254 I = LastInst;
255 if (AllowModify)
256 I->eraseFromParent();
257 return true;
258 }
259
260 // Otherwise, can't handle this.
261 return true;
262}
263
264
265unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
266 MachineBasicBlock::iterator I = MBB.end();
267 if (I == MBB.begin()) return 0;
268 --I;
269 if (!isUncondBranchOpcode(I->getOpcode()) &&
270 !isCondBranchOpcode(I->getOpcode()))
271 return 0;
272
273 // Remove the branch.
274 I->eraseFromParent();
275
276 I = MBB.end();
277
278 if (I == MBB.begin()) return 1;
279 --I;
280 if (!isCondBranchOpcode(I->getOpcode()))
281 return 1;
282
283 // Remove the branch.
284 I->eraseFromParent();
285 return 2;
286}
287
288unsigned
289ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
290 MachineBasicBlock *FBB,
291 const SmallVectorImpl<MachineOperand> &Cond) const {
292 // FIXME this should probably have a DebugLoc argument
293 DebugLoc dl = DebugLoc::getUnknownLoc();
294
295 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
296 int BOpc = !AFI->isThumbFunction()
297 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
298 int BccOpc = !AFI->isThumbFunction()
299 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
300
301 // Shouldn't be a fall through.
302 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
303 assert((Cond.size() == 2 || Cond.size() == 0) &&
304 "ARM branch conditions have two components!");
305
306 if (FBB == 0) {
307 if (Cond.empty()) // Unconditional branch?
308 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
309 else
310 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
311 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
312 return 1;
313 }
314
315 // Two-way conditional branch.
316 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
317 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
318 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
319 return 2;
320}
321
322bool ARMBaseInstrInfo::
323ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
324 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
325 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
326 return false;
327}
328
329bool ARMBaseInstrInfo::
330PredicateInstruction(MachineInstr *MI,
331 const SmallVectorImpl<MachineOperand> &Pred) const {
332 unsigned Opc = MI->getOpcode();
333 if (isUncondBranchOpcode(Opc)) {
334 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
335 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
336 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
337 return true;
338 }
339
340 int PIdx = MI->findFirstPredOperandIdx();
341 if (PIdx != -1) {
342 MachineOperand &PMO = MI->getOperand(PIdx);
343 PMO.setImm(Pred[0].getImm());
344 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
345 return true;
346 }
347 return false;
348}
349
350bool ARMBaseInstrInfo::
351SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
352 const SmallVectorImpl<MachineOperand> &Pred2) const {
353 if (Pred1.size() > 2 || Pred2.size() > 2)
354 return false;
355
356 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
357 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
358 if (CC1 == CC2)
359 return true;
360
361 switch (CC1) {
362 default:
363 return false;
364 case ARMCC::AL:
365 return true;
366 case ARMCC::HS:
367 return CC2 == ARMCC::HI;
368 case ARMCC::LS:
369 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
370 case ARMCC::GE:
371 return CC2 == ARMCC::GT;
372 case ARMCC::LE:
373 return CC2 == ARMCC::LT;
374 }
375}
376
377bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
378 std::vector<MachineOperand> &Pred) const {
379 // FIXME: This confuses implicit_def with optional CPSR def.
380 const TargetInstrDesc &TID = MI->getDesc();
381 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
382 return false;
383
384 bool Found = false;
385 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
386 const MachineOperand &MO = MI->getOperand(i);
387 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
388 Pred.push_back(MO);
389 Found = true;
390 }
391 }
392
393 return Found;
394}
395
396
397/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
398static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
399 unsigned JTI) DISABLE_INLINE;
400static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
401 unsigned JTI) {
402 return JT[JTI].MBBs.size();
403}
404
405/// GetInstSize - Return the size of the specified MachineInstr.
406///
407unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
408 const MachineBasicBlock &MBB = *MI->getParent();
409 const MachineFunction *MF = MBB.getParent();
410 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
411
412 // Basic size info comes from the TSFlags field.
413 const TargetInstrDesc &TID = MI->getDesc();
414 unsigned TSFlags = TID.TSFlags;
415
416 unsigned Opc = MI->getOpcode();
417 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
418 default: {
419 // If this machine instr is an inline asm, measure it.
420 if (MI->getOpcode() == ARM::INLINEASM)
421 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
422 if (MI->isLabel())
423 return 0;
424 switch (Opc) {
425 default:
426 llvm_unreachable("Unknown or unset size field for instr!");
427 case TargetInstrInfo::IMPLICIT_DEF:
428 case TargetInstrInfo::KILL:
429 case TargetInstrInfo::DBG_LABEL:
430 case TargetInstrInfo::EH_LABEL:
431 return 0;
432 }
433 break;
434 }
435 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
436 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
437 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
438 case ARMII::SizeSpecial: {
439 switch (Opc) {
440 case ARM::CONSTPOOL_ENTRY:
441 // If this machine instr is a constant pool entry, its size is recorded as
442 // operand #2.
443 return MI->getOperand(2).getImm();
444 case ARM::Int_eh_sjlj_setjmp:
445 return 24;
446 case ARM::t2Int_eh_sjlj_setjmp:
257 isUncondBranchOpcode(LastOpc)) {
258 I = LastInst;
259 if (AllowModify)
260 I->eraseFromParent();
261 return true;
262 }
263
264 // Otherwise, can't handle this.
265 return true;
266}
267
268
269unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
270 MachineBasicBlock::iterator I = MBB.end();
271 if (I == MBB.begin()) return 0;
272 --I;
273 if (!isUncondBranchOpcode(I->getOpcode()) &&
274 !isCondBranchOpcode(I->getOpcode()))
275 return 0;
276
277 // Remove the branch.
278 I->eraseFromParent();
279
280 I = MBB.end();
281
282 if (I == MBB.begin()) return 1;
283 --I;
284 if (!isCondBranchOpcode(I->getOpcode()))
285 return 1;
286
287 // Remove the branch.
288 I->eraseFromParent();
289 return 2;
290}
291
292unsigned
293ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
294 MachineBasicBlock *FBB,
295 const SmallVectorImpl<MachineOperand> &Cond) const {
296 // FIXME this should probably have a DebugLoc argument
297 DebugLoc dl = DebugLoc::getUnknownLoc();
298
299 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
300 int BOpc = !AFI->isThumbFunction()
301 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
302 int BccOpc = !AFI->isThumbFunction()
303 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
304
305 // Shouldn't be a fall through.
306 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
307 assert((Cond.size() == 2 || Cond.size() == 0) &&
308 "ARM branch conditions have two components!");
309
310 if (FBB == 0) {
311 if (Cond.empty()) // Unconditional branch?
312 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
313 else
314 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
315 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
316 return 1;
317 }
318
319 // Two-way conditional branch.
320 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
321 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
322 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
323 return 2;
324}
325
326bool ARMBaseInstrInfo::
327ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
328 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
329 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
330 return false;
331}
332
333bool ARMBaseInstrInfo::
334PredicateInstruction(MachineInstr *MI,
335 const SmallVectorImpl<MachineOperand> &Pred) const {
336 unsigned Opc = MI->getOpcode();
337 if (isUncondBranchOpcode(Opc)) {
338 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
339 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
340 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
341 return true;
342 }
343
344 int PIdx = MI->findFirstPredOperandIdx();
345 if (PIdx != -1) {
346 MachineOperand &PMO = MI->getOperand(PIdx);
347 PMO.setImm(Pred[0].getImm());
348 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
349 return true;
350 }
351 return false;
352}
353
354bool ARMBaseInstrInfo::
355SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
356 const SmallVectorImpl<MachineOperand> &Pred2) const {
357 if (Pred1.size() > 2 || Pred2.size() > 2)
358 return false;
359
360 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
361 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
362 if (CC1 == CC2)
363 return true;
364
365 switch (CC1) {
366 default:
367 return false;
368 case ARMCC::AL:
369 return true;
370 case ARMCC::HS:
371 return CC2 == ARMCC::HI;
372 case ARMCC::LS:
373 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
374 case ARMCC::GE:
375 return CC2 == ARMCC::GT;
376 case ARMCC::LE:
377 return CC2 == ARMCC::LT;
378 }
379}
380
381bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
382 std::vector<MachineOperand> &Pred) const {
383 // FIXME: This confuses implicit_def with optional CPSR def.
384 const TargetInstrDesc &TID = MI->getDesc();
385 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
386 return false;
387
388 bool Found = false;
389 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
390 const MachineOperand &MO = MI->getOperand(i);
391 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
392 Pred.push_back(MO);
393 Found = true;
394 }
395 }
396
397 return Found;
398}
399
400
401/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
402static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
403 unsigned JTI) DISABLE_INLINE;
404static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
405 unsigned JTI) {
406 return JT[JTI].MBBs.size();
407}
408
409/// GetInstSize - Return the size of the specified MachineInstr.
410///
411unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
412 const MachineBasicBlock &MBB = *MI->getParent();
413 const MachineFunction *MF = MBB.getParent();
414 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
415
416 // Basic size info comes from the TSFlags field.
417 const TargetInstrDesc &TID = MI->getDesc();
418 unsigned TSFlags = TID.TSFlags;
419
420 unsigned Opc = MI->getOpcode();
421 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
422 default: {
423 // If this machine instr is an inline asm, measure it.
424 if (MI->getOpcode() == ARM::INLINEASM)
425 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
426 if (MI->isLabel())
427 return 0;
428 switch (Opc) {
429 default:
430 llvm_unreachable("Unknown or unset size field for instr!");
431 case TargetInstrInfo::IMPLICIT_DEF:
432 case TargetInstrInfo::KILL:
433 case TargetInstrInfo::DBG_LABEL:
434 case TargetInstrInfo::EH_LABEL:
435 return 0;
436 }
437 break;
438 }
439 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
440 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
441 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
442 case ARMII::SizeSpecial: {
443 switch (Opc) {
444 case ARM::CONSTPOOL_ENTRY:
445 // If this machine instr is a constant pool entry, its size is recorded as
446 // operand #2.
447 return MI->getOperand(2).getImm();
448 case ARM::Int_eh_sjlj_setjmp:
449 return 24;
450 case ARM::t2Int_eh_sjlj_setjmp:
447 return 20;
451 return 22;
448 case ARM::BR_JTr:
449 case ARM::BR_JTm:
450 case ARM::BR_JTadd:
451 case ARM::tBR_JTr:
452 case ARM::t2BR_JT:
453 case ARM::t2TBB:
454 case ARM::t2TBH: {
455 // These are jumptable branches, i.e. a branch followed by an inlined
456 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
457 // entry is one byte; TBH two byte each.
458 unsigned EntrySize = (Opc == ARM::t2TBB)
459 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
460 unsigned NumOps = TID.getNumOperands();
461 MachineOperand JTOP =
462 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
463 unsigned JTI = JTOP.getIndex();
464 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
465 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
466 assert(JTI < JT.size());
467 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
468 // 4 aligned. The assembler / linker may add 2 byte padding just before
469 // the JT entries. The size does not include this padding; the
470 // constant islands pass does separate bookkeeping for it.
471 // FIXME: If we know the size of the function is less than (1 << 16) *2
472 // bytes, we can use 16-bit entries instead. Then there won't be an
473 // alignment issue.
474 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
475 unsigned NumEntries = getNumJTEntries(JT, JTI);
476 if (Opc == ARM::t2TBB && (NumEntries & 1))
477 // Make sure the instruction that follows TBB is 2-byte aligned.
478 // FIXME: Constant island pass should insert an "ALIGN" instruction
479 // instead.
480 ++NumEntries;
481 return NumEntries * EntrySize + InstSize;
482 }
483 default:
484 // Otherwise, pseudo-instruction sizes are zero.
485 return 0;
486 }
487 }
488 }
489 return 0; // Not reached
490}
491
492/// Return true if the instruction is a register to register move and
493/// leave the source and dest operands in the passed parameters.
494///
495bool
496ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
497 unsigned &SrcReg, unsigned &DstReg,
498 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
499 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
500
501 switch (MI.getOpcode()) {
502 default: break;
503 case ARM::FCPYS:
504 case ARM::FCPYD:
505 case ARM::VMOVD:
452 case ARM::BR_JTr:
453 case ARM::BR_JTm:
454 case ARM::BR_JTadd:
455 case ARM::tBR_JTr:
456 case ARM::t2BR_JT:
457 case ARM::t2TBB:
458 case ARM::t2TBH: {
459 // These are jumptable branches, i.e. a branch followed by an inlined
460 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
461 // entry is one byte; TBH two byte each.
462 unsigned EntrySize = (Opc == ARM::t2TBB)
463 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
464 unsigned NumOps = TID.getNumOperands();
465 MachineOperand JTOP =
466 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
467 unsigned JTI = JTOP.getIndex();
468 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
469 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
470 assert(JTI < JT.size());
471 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
472 // 4 aligned. The assembler / linker may add 2 byte padding just before
473 // the JT entries. The size does not include this padding; the
474 // constant islands pass does separate bookkeeping for it.
475 // FIXME: If we know the size of the function is less than (1 << 16) *2
476 // bytes, we can use 16-bit entries instead. Then there won't be an
477 // alignment issue.
478 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
479 unsigned NumEntries = getNumJTEntries(JT, JTI);
480 if (Opc == ARM::t2TBB && (NumEntries & 1))
481 // Make sure the instruction that follows TBB is 2-byte aligned.
482 // FIXME: Constant island pass should insert an "ALIGN" instruction
483 // instead.
484 ++NumEntries;
485 return NumEntries * EntrySize + InstSize;
486 }
487 default:
488 // Otherwise, pseudo-instruction sizes are zero.
489 return 0;
490 }
491 }
492 }
493 return 0; // Not reached
494}
495
496/// Return true if the instruction is a register to register move and
497/// leave the source and dest operands in the passed parameters.
498///
499bool
500ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
501 unsigned &SrcReg, unsigned &DstReg,
502 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
503 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
504
505 switch (MI.getOpcode()) {
506 default: break;
507 case ARM::FCPYS:
508 case ARM::FCPYD:
509 case ARM::VMOVD:
506 case ARM::VMOVQ: {
510 case ARM::VMOVQ: {
507 SrcReg = MI.getOperand(1).getReg();
508 DstReg = MI.getOperand(0).getReg();
509 return true;
510 }
511 case ARM::MOVr:
512 case ARM::tMOVr:
513 case ARM::tMOVgpr2tgpr:
514 case ARM::tMOVtgpr2gpr:
515 case ARM::tMOVgpr2gpr:
516 case ARM::t2MOVr: {
517 assert(MI.getDesc().getNumOperands() >= 2 &&
518 MI.getOperand(0).isReg() &&
519 MI.getOperand(1).isReg() &&
520 "Invalid ARM MOV instruction");
521 SrcReg = MI.getOperand(1).getReg();
522 DstReg = MI.getOperand(0).getReg();
523 return true;
524 }
525 }
526
527 return false;
528}
529
530unsigned
531ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
532 int &FrameIndex) const {
533 switch (MI->getOpcode()) {
534 default: break;
535 case ARM::LDR:
536 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
537 if (MI->getOperand(1).isFI() &&
538 MI->getOperand(2).isReg() &&
539 MI->getOperand(3).isImm() &&
540 MI->getOperand(2).getReg() == 0 &&
541 MI->getOperand(3).getImm() == 0) {
542 FrameIndex = MI->getOperand(1).getIndex();
543 return MI->getOperand(0).getReg();
544 }
545 break;
546 case ARM::t2LDRi12:
547 case ARM::tRestore:
548 if (MI->getOperand(1).isFI() &&
549 MI->getOperand(2).isImm() &&
550 MI->getOperand(2).getImm() == 0) {
551 FrameIndex = MI->getOperand(1).getIndex();
552 return MI->getOperand(0).getReg();
553 }
554 break;
555 case ARM::FLDD:
556 case ARM::FLDS:
557 if (MI->getOperand(1).isFI() &&
558 MI->getOperand(2).isImm() &&
559 MI->getOperand(2).getImm() == 0) {
560 FrameIndex = MI->getOperand(1).getIndex();
561 return MI->getOperand(0).getReg();
562 }
563 break;
564 }
565
566 return 0;
567}
568
569unsigned
570ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
571 int &FrameIndex) const {
572 switch (MI->getOpcode()) {
573 default: break;
574 case ARM::STR:
575 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
576 if (MI->getOperand(1).isFI() &&
577 MI->getOperand(2).isReg() &&
578 MI->getOperand(3).isImm() &&
579 MI->getOperand(2).getReg() == 0 &&
580 MI->getOperand(3).getImm() == 0) {
581 FrameIndex = MI->getOperand(1).getIndex();
582 return MI->getOperand(0).getReg();
583 }
584 break;
585 case ARM::t2STRi12:
586 case ARM::tSpill:
587 if (MI->getOperand(1).isFI() &&
588 MI->getOperand(2).isImm() &&
589 MI->getOperand(2).getImm() == 0) {
590 FrameIndex = MI->getOperand(1).getIndex();
591 return MI->getOperand(0).getReg();
592 }
593 break;
594 case ARM::FSTD:
595 case ARM::FSTS:
596 if (MI->getOperand(1).isFI() &&
597 MI->getOperand(2).isImm() &&
598 MI->getOperand(2).getImm() == 0) {
599 FrameIndex = MI->getOperand(1).getIndex();
600 return MI->getOperand(0).getReg();
601 }
602 break;
603 }
604
605 return 0;
606}
607
608bool
609ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
610 MachineBasicBlock::iterator I,
611 unsigned DestReg, unsigned SrcReg,
612 const TargetRegisterClass *DestRC,
613 const TargetRegisterClass *SrcRC) const {
614 DebugLoc DL = DebugLoc::getUnknownLoc();
615 if (I != MBB.end()) DL = I->getDebugLoc();
616
617 if (DestRC != SrcRC) {
511 SrcReg = MI.getOperand(1).getReg();
512 DstReg = MI.getOperand(0).getReg();
513 return true;
514 }
515 case ARM::MOVr:
516 case ARM::tMOVr:
517 case ARM::tMOVgpr2tgpr:
518 case ARM::tMOVtgpr2gpr:
519 case ARM::tMOVgpr2gpr:
520 case ARM::t2MOVr: {
521 assert(MI.getDesc().getNumOperands() >= 2 &&
522 MI.getOperand(0).isReg() &&
523 MI.getOperand(1).isReg() &&
524 "Invalid ARM MOV instruction");
525 SrcReg = MI.getOperand(1).getReg();
526 DstReg = MI.getOperand(0).getReg();
527 return true;
528 }
529 }
530
531 return false;
532}
533
534unsigned
535ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
536 int &FrameIndex) const {
537 switch (MI->getOpcode()) {
538 default: break;
539 case ARM::LDR:
540 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
541 if (MI->getOperand(1).isFI() &&
542 MI->getOperand(2).isReg() &&
543 MI->getOperand(3).isImm() &&
544 MI->getOperand(2).getReg() == 0 &&
545 MI->getOperand(3).getImm() == 0) {
546 FrameIndex = MI->getOperand(1).getIndex();
547 return MI->getOperand(0).getReg();
548 }
549 break;
550 case ARM::t2LDRi12:
551 case ARM::tRestore:
552 if (MI->getOperand(1).isFI() &&
553 MI->getOperand(2).isImm() &&
554 MI->getOperand(2).getImm() == 0) {
555 FrameIndex = MI->getOperand(1).getIndex();
556 return MI->getOperand(0).getReg();
557 }
558 break;
559 case ARM::FLDD:
560 case ARM::FLDS:
561 if (MI->getOperand(1).isFI() &&
562 MI->getOperand(2).isImm() &&
563 MI->getOperand(2).getImm() == 0) {
564 FrameIndex = MI->getOperand(1).getIndex();
565 return MI->getOperand(0).getReg();
566 }
567 break;
568 }
569
570 return 0;
571}
572
573unsigned
574ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
575 int &FrameIndex) const {
576 switch (MI->getOpcode()) {
577 default: break;
578 case ARM::STR:
579 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
580 if (MI->getOperand(1).isFI() &&
581 MI->getOperand(2).isReg() &&
582 MI->getOperand(3).isImm() &&
583 MI->getOperand(2).getReg() == 0 &&
584 MI->getOperand(3).getImm() == 0) {
585 FrameIndex = MI->getOperand(1).getIndex();
586 return MI->getOperand(0).getReg();
587 }
588 break;
589 case ARM::t2STRi12:
590 case ARM::tSpill:
591 if (MI->getOperand(1).isFI() &&
592 MI->getOperand(2).isImm() &&
593 MI->getOperand(2).getImm() == 0) {
594 FrameIndex = MI->getOperand(1).getIndex();
595 return MI->getOperand(0).getReg();
596 }
597 break;
598 case ARM::FSTD:
599 case ARM::FSTS:
600 if (MI->getOperand(1).isFI() &&
601 MI->getOperand(2).isImm() &&
602 MI->getOperand(2).getImm() == 0) {
603 FrameIndex = MI->getOperand(1).getIndex();
604 return MI->getOperand(0).getReg();
605 }
606 break;
607 }
608
609 return 0;
610}
611
612bool
613ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
614 MachineBasicBlock::iterator I,
615 unsigned DestReg, unsigned SrcReg,
616 const TargetRegisterClass *DestRC,
617 const TargetRegisterClass *SrcRC) const {
618 DebugLoc DL = DebugLoc::getUnknownLoc();
619 if (I != MBB.end()) DL = I->getDebugLoc();
620
621 if (DestRC != SrcRC) {
618 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies
619 // Allow QPR / QPR_VFP2 cross-class copies
620 if (DestRC == ARM::DPRRegisterClass) {
621 if (SrcRC == ARM::DPR_VFP2RegisterClass ||
622 SrcRC == ARM::DPR_8RegisterClass) {
623 } else
624 return false;
625 } else if (DestRC == ARM::DPR_VFP2RegisterClass) {
626 if (SrcRC == ARM::DPRRegisterClass ||
627 SrcRC == ARM::DPR_8RegisterClass) {
628 } else
629 return false;
630 } else if (DestRC == ARM::DPR_8RegisterClass) {
631 if (SrcRC == ARM::DPRRegisterClass ||
632 SrcRC == ARM::DPR_VFP2RegisterClass) {
633 } else
634 return false;
635 } else if ((DestRC == ARM::QPRRegisterClass &&
636 SrcRC == ARM::QPR_VFP2RegisterClass) ||
637 (DestRC == ARM::QPR_VFP2RegisterClass &&
638 SrcRC == ARM::QPRRegisterClass)) {
639 } else
622 if (DestRC->getSize() != SrcRC->getSize())
640 return false;
623 return false;
624
625 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
626 // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
627 if (DestRC->getSize() != 8 && DestRC->getSize() != 16)
628 return false;
641 }
642
643 if (DestRC == ARM::GPRRegisterClass) {
644 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
645 DestReg).addReg(SrcReg)));
646 } else if (DestRC == ARM::SPRRegisterClass) {
647 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
648 .addReg(SrcReg));
629 }
630
631 if (DestRC == ARM::GPRRegisterClass) {
632 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
633 DestReg).addReg(SrcReg)));
634 } else if (DestRC == ARM::SPRRegisterClass) {
635 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
636 .addReg(SrcReg));
649 } else if ((DestRC == ARM::DPRRegisterClass) ||
650 (DestRC == ARM::DPR_VFP2RegisterClass) ||
651 (DestRC == ARM::DPR_8RegisterClass)) {
637 } else if (DestRC == ARM::DPRRegisterClass) {
652 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
653 .addReg(SrcReg));
638 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
639 .addReg(SrcReg));
640 } else if (DestRC == ARM::DPR_VFP2RegisterClass ||
641 DestRC == ARM::DPR_8RegisterClass ||
642 SrcRC == ARM::DPR_VFP2RegisterClass ||
643 SrcRC == ARM::DPR_8RegisterClass) {
644 // Always use neon reg-reg move if source or dest is NEON-only regclass.
645 BuildMI(MBB, I, DL, get(ARM::VMOVD), DestReg).addReg(SrcReg);
654 } else if (DestRC == ARM::QPRRegisterClass ||
646 } else if (DestRC == ARM::QPRRegisterClass ||
655 DestRC == ARM::QPR_VFP2RegisterClass) {
647 DestRC == ARM::QPR_VFP2RegisterClass ||
648 DestRC == ARM::QPR_8RegisterClass) {
656 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
657 } else {
658 return false;
659 }
660
661 return true;
662}
663
664void ARMBaseInstrInfo::
665storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
666 unsigned SrcReg, bool isKill, int FI,
667 const TargetRegisterClass *RC) const {
668 DebugLoc DL = DebugLoc::getUnknownLoc();
669 if (I != MBB.end()) DL = I->getDebugLoc();
670 MachineFunction &MF = *MBB.getParent();
671 MachineFrameInfo &MFI = *MF.getFrameInfo();
672
673 MachineMemOperand *MMO =
674 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
675 MachineMemOperand::MOStore, 0,
676 MFI.getObjectSize(FI),
677 MFI.getObjectAlignment(FI));
678
679 if (RC == ARM::GPRRegisterClass) {
680 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
681 .addReg(SrcReg, getKillRegState(isKill))
682 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
683 } else if (RC == ARM::DPRRegisterClass ||
684 RC == ARM::DPR_VFP2RegisterClass ||
685 RC == ARM::DPR_8RegisterClass) {
686 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
687 .addReg(SrcReg, getKillRegState(isKill))
688 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
689 } else if (RC == ARM::SPRRegisterClass) {
690 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
691 .addReg(SrcReg, getKillRegState(isKill))
692 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
693 } else {
694 assert((RC == ARM::QPRRegisterClass ||
695 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
696 // FIXME: Neon instructions should support predicates
697 BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill))
698 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
699 }
700}
701
702void ARMBaseInstrInfo::
703loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
704 unsigned DestReg, int FI,
705 const TargetRegisterClass *RC) const {
706 DebugLoc DL = DebugLoc::getUnknownLoc();
707 if (I != MBB.end()) DL = I->getDebugLoc();
708 MachineFunction &MF = *MBB.getParent();
709 MachineFrameInfo &MFI = *MF.getFrameInfo();
710
711 MachineMemOperand *MMO =
712 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
713 MachineMemOperand::MOLoad, 0,
714 MFI.getObjectSize(FI),
715 MFI.getObjectAlignment(FI));
716
717 if (RC == ARM::GPRRegisterClass) {
718 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
719 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
720 } else if (RC == ARM::DPRRegisterClass ||
721 RC == ARM::DPR_VFP2RegisterClass ||
722 RC == ARM::DPR_8RegisterClass) {
723 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
724 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
725 } else if (RC == ARM::SPRRegisterClass) {
726 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
727 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
728 } else {
729 assert((RC == ARM::QPRRegisterClass ||
649 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
650 } else {
651 return false;
652 }
653
654 return true;
655}
656
657void ARMBaseInstrInfo::
658storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
659 unsigned SrcReg, bool isKill, int FI,
660 const TargetRegisterClass *RC) const {
661 DebugLoc DL = DebugLoc::getUnknownLoc();
662 if (I != MBB.end()) DL = I->getDebugLoc();
663 MachineFunction &MF = *MBB.getParent();
664 MachineFrameInfo &MFI = *MF.getFrameInfo();
665
666 MachineMemOperand *MMO =
667 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
668 MachineMemOperand::MOStore, 0,
669 MFI.getObjectSize(FI),
670 MFI.getObjectAlignment(FI));
671
672 if (RC == ARM::GPRRegisterClass) {
673 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
674 .addReg(SrcReg, getKillRegState(isKill))
675 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
676 } else if (RC == ARM::DPRRegisterClass ||
677 RC == ARM::DPR_VFP2RegisterClass ||
678 RC == ARM::DPR_8RegisterClass) {
679 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
680 .addReg(SrcReg, getKillRegState(isKill))
681 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
682 } else if (RC == ARM::SPRRegisterClass) {
683 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
684 .addReg(SrcReg, getKillRegState(isKill))
685 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
686 } else {
687 assert((RC == ARM::QPRRegisterClass ||
688 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
689 // FIXME: Neon instructions should support predicates
690 BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill))
691 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
692 }
693}
694
695void ARMBaseInstrInfo::
696loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
697 unsigned DestReg, int FI,
698 const TargetRegisterClass *RC) const {
699 DebugLoc DL = DebugLoc::getUnknownLoc();
700 if (I != MBB.end()) DL = I->getDebugLoc();
701 MachineFunction &MF = *MBB.getParent();
702 MachineFrameInfo &MFI = *MF.getFrameInfo();
703
704 MachineMemOperand *MMO =
705 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
706 MachineMemOperand::MOLoad, 0,
707 MFI.getObjectSize(FI),
708 MFI.getObjectAlignment(FI));
709
710 if (RC == ARM::GPRRegisterClass) {
711 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
712 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
713 } else if (RC == ARM::DPRRegisterClass ||
714 RC == ARM::DPR_VFP2RegisterClass ||
715 RC == ARM::DPR_8RegisterClass) {
716 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
717 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
718 } else if (RC == ARM::SPRRegisterClass) {
719 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
720 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
721 } else {
722 assert((RC == ARM::QPRRegisterClass ||
730 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
723 RC == ARM::QPR_VFP2RegisterClass ||
724 RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
731 // FIXME: Neon instructions should support predicates
725 // FIXME: Neon instructions should support predicates
732 BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO);
726 BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0).
727 addMemOperand(MMO);
733 }
734}
735
736MachineInstr *ARMBaseInstrInfo::
737foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
738 const SmallVectorImpl<unsigned> &Ops, int FI) const {
739 if (Ops.size() != 1) return NULL;
740
741 unsigned OpNum = Ops[0];
742 unsigned Opc = MI->getOpcode();
743 MachineInstr *NewMI = NULL;
744 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
745 // If it is updating CPSR, then it cannot be folded.
746 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
747 return NULL;
748 unsigned Pred = MI->getOperand(2).getImm();
749 unsigned PredReg = MI->getOperand(3).getReg();
750 if (OpNum == 0) { // move -> store
751 unsigned SrcReg = MI->getOperand(1).getReg();
728 }
729}
730
731MachineInstr *ARMBaseInstrInfo::
732foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
733 const SmallVectorImpl<unsigned> &Ops, int FI) const {
734 if (Ops.size() != 1) return NULL;
735
736 unsigned OpNum = Ops[0];
737 unsigned Opc = MI->getOpcode();
738 MachineInstr *NewMI = NULL;
739 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
740 // If it is updating CPSR, then it cannot be folded.
741 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
742 return NULL;
743 unsigned Pred = MI->getOperand(2).getImm();
744 unsigned PredReg = MI->getOperand(3).getReg();
745 if (OpNum == 0) { // move -> store
746 unsigned SrcReg = MI->getOperand(1).getReg();
747 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
752 bool isKill = MI->getOperand(1).isKill();
753 bool isUndef = MI->getOperand(1).isUndef();
754 if (Opc == ARM::MOVr)
755 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
748 bool isKill = MI->getOperand(1).isKill();
749 bool isUndef = MI->getOperand(1).isUndef();
750 if (Opc == ARM::MOVr)
751 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
756 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
752 .addReg(SrcReg,
753 getKillRegState(isKill) | getUndefRegState(isUndef),
754 SrcSubReg)
757 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
758 else // ARM::t2MOVr
759 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
755 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
756 else // ARM::t2MOVr
757 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
760 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
758 .addReg(SrcReg,
759 getKillRegState(isKill) | getUndefRegState(isUndef),
760 SrcSubReg)
761 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
762 } else { // move -> load
763 unsigned DstReg = MI->getOperand(0).getReg();
761 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
762 } else { // move -> load
763 unsigned DstReg = MI->getOperand(0).getReg();
764 unsigned DstSubReg = MI->getOperand(0).getSubReg();
764 bool isDead = MI->getOperand(0).isDead();
765 bool isUndef = MI->getOperand(0).isUndef();
766 if (Opc == ARM::MOVr)
767 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
768 .addReg(DstReg,
769 RegState::Define |
770 getDeadRegState(isDead) |
765 bool isDead = MI->getOperand(0).isDead();
766 bool isUndef = MI->getOperand(0).isUndef();
767 if (Opc == ARM::MOVr)
768 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
769 .addReg(DstReg,
770 RegState::Define |
771 getDeadRegState(isDead) |
771 getUndefRegState(isUndef))
772 getUndefRegState(isUndef), DstSubReg)
772 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
773 else // ARM::t2MOVr
774 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
775 .addReg(DstReg,
776 RegState::Define |
777 getDeadRegState(isDead) |
773 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
774 else // ARM::t2MOVr
775 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
776 .addReg(DstReg,
777 RegState::Define |
778 getDeadRegState(isDead) |
778 getUndefRegState(isUndef))
779 getUndefRegState(isUndef), DstSubReg)
779 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
780 }
781 } else if (Opc == ARM::tMOVgpr2gpr ||
782 Opc == ARM::tMOVtgpr2gpr ||
783 Opc == ARM::tMOVgpr2tgpr) {
784 if (OpNum == 0) { // move -> store
785 unsigned SrcReg = MI->getOperand(1).getReg();
780 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
781 }
782 } else if (Opc == ARM::tMOVgpr2gpr ||
783 Opc == ARM::tMOVtgpr2gpr ||
784 Opc == ARM::tMOVgpr2tgpr) {
785 if (OpNum == 0) { // move -> store
786 unsigned SrcReg = MI->getOperand(1).getReg();
787 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
786 bool isKill = MI->getOperand(1).isKill();
787 bool isUndef = MI->getOperand(1).isUndef();
788 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
788 bool isKill = MI->getOperand(1).isKill();
789 bool isUndef = MI->getOperand(1).isUndef();
790 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
789 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
791 .addReg(SrcReg,
792 getKillRegState(isKill) | getUndefRegState(isUndef),
793 SrcSubReg)
790 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
791 } else { // move -> load
792 unsigned DstReg = MI->getOperand(0).getReg();
794 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
795 } else { // move -> load
796 unsigned DstReg = MI->getOperand(0).getReg();
797 unsigned DstSubReg = MI->getOperand(0).getSubReg();
793 bool isDead = MI->getOperand(0).isDead();
794 bool isUndef = MI->getOperand(0).isUndef();
795 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
796 .addReg(DstReg,
797 RegState::Define |
798 getDeadRegState(isDead) |
798 bool isDead = MI->getOperand(0).isDead();
799 bool isUndef = MI->getOperand(0).isUndef();
800 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
801 .addReg(DstReg,
802 RegState::Define |
803 getDeadRegState(isDead) |
799 getUndefRegState(isUndef))
804 getUndefRegState(isUndef),
805 DstSubReg)
800 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
801 }
802 } else if (Opc == ARM::FCPYS) {
803 unsigned Pred = MI->getOperand(2).getImm();
804 unsigned PredReg = MI->getOperand(3).getReg();
805 if (OpNum == 0) { // move -> store
806 unsigned SrcReg = MI->getOperand(1).getReg();
806 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
807 }
808 } else if (Opc == ARM::FCPYS) {
809 unsigned Pred = MI->getOperand(2).getImm();
810 unsigned PredReg = MI->getOperand(3).getReg();
811 if (OpNum == 0) { // move -> store
812 unsigned SrcReg = MI->getOperand(1).getReg();
813 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
807 bool isKill = MI->getOperand(1).isKill();
808 bool isUndef = MI->getOperand(1).isUndef();
809 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
814 bool isKill = MI->getOperand(1).isKill();
815 bool isUndef = MI->getOperand(1).isUndef();
816 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
810 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
817 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
818 SrcSubReg)
811 .addFrameIndex(FI)
812 .addImm(0).addImm(Pred).addReg(PredReg);
813 } else { // move -> load
814 unsigned DstReg = MI->getOperand(0).getReg();
819 .addFrameIndex(FI)
820 .addImm(0).addImm(Pred).addReg(PredReg);
821 } else { // move -> load
822 unsigned DstReg = MI->getOperand(0).getReg();
823 unsigned DstSubReg = MI->getOperand(0).getSubReg();
815 bool isDead = MI->getOperand(0).isDead();
816 bool isUndef = MI->getOperand(0).isUndef();
817 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
818 .addReg(DstReg,
819 RegState::Define |
820 getDeadRegState(isDead) |
824 bool isDead = MI->getOperand(0).isDead();
825 bool isUndef = MI->getOperand(0).isUndef();
826 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
827 .addReg(DstReg,
828 RegState::Define |
829 getDeadRegState(isDead) |
821 getUndefRegState(isUndef))
830 getUndefRegState(isUndef),
831 DstSubReg)
822 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
823 }
824 }
825 else if (Opc == ARM::FCPYD) {
826 unsigned Pred = MI->getOperand(2).getImm();
827 unsigned PredReg = MI->getOperand(3).getReg();
828 if (OpNum == 0) { // move -> store
829 unsigned SrcReg = MI->getOperand(1).getReg();
832 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
833 }
834 }
835 else if (Opc == ARM::FCPYD) {
836 unsigned Pred = MI->getOperand(2).getImm();
837 unsigned PredReg = MI->getOperand(3).getReg();
838 if (OpNum == 0) { // move -> store
839 unsigned SrcReg = MI->getOperand(1).getReg();
840 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
830 bool isKill = MI->getOperand(1).isKill();
831 bool isUndef = MI->getOperand(1).isUndef();
832 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
841 bool isKill = MI->getOperand(1).isKill();
842 bool isUndef = MI->getOperand(1).isUndef();
843 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
833 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
844 .addReg(SrcReg,
845 getKillRegState(isKill) | getUndefRegState(isUndef),
846 SrcSubReg)
834 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
835 } else { // move -> load
836 unsigned DstReg = MI->getOperand(0).getReg();
847 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
848 } else { // move -> load
849 unsigned DstReg = MI->getOperand(0).getReg();
850 unsigned DstSubReg = MI->getOperand(0).getSubReg();
837 bool isDead = MI->getOperand(0).isDead();
838 bool isUndef = MI->getOperand(0).isUndef();
839 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
840 .addReg(DstReg,
841 RegState::Define |
842 getDeadRegState(isDead) |
851 bool isDead = MI->getOperand(0).isDead();
852 bool isUndef = MI->getOperand(0).isUndef();
853 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
854 .addReg(DstReg,
855 RegState::Define |
856 getDeadRegState(isDead) |
843 getUndefRegState(isUndef))
857 getUndefRegState(isUndef),
858 DstSubReg)
844 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
845 }
846 }
847
848 return NewMI;
849}
850
851MachineInstr*
852ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
853 MachineInstr* MI,
854 const SmallVectorImpl<unsigned> &Ops,
855 MachineInstr* LoadMI) const {
856 // FIXME
857 return 0;
858}
859
860bool
861ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
862 const SmallVectorImpl<unsigned> &Ops) const {
863 if (Ops.size() != 1) return false;
864
865 unsigned Opc = MI->getOpcode();
866 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
867 // If it is updating CPSR, then it cannot be folded.
868 return MI->getOperand(4).getReg() != ARM::CPSR ||
869 MI->getOperand(4).isDead();
870 } else if (Opc == ARM::tMOVgpr2gpr ||
871 Opc == ARM::tMOVtgpr2gpr ||
872 Opc == ARM::tMOVgpr2tgpr) {
873 return true;
874 } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) {
875 return true;
876 } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) {
877 return false; // FIXME
878 }
879
880 return false;
881}
882
883/// getInstrPredicate - If instruction is predicated, returns its predicate
884/// condition, otherwise returns AL. It also returns the condition code
885/// register by reference.
886ARMCC::CondCodes
887llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
888 int PIdx = MI->findFirstPredOperandIdx();
889 if (PIdx == -1) {
890 PredReg = 0;
891 return ARMCC::AL;
892 }
893
894 PredReg = MI->getOperand(PIdx+1).getReg();
895 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
896}
897
898
899int llvm::getMatchingCondBranchOpcode(int Opc) {
900 if (Opc == ARM::B)
901 return ARM::Bcc;
902 else if (Opc == ARM::tB)
903 return ARM::tBcc;
904 else if (Opc == ARM::t2B)
905 return ARM::t2Bcc;
906
907 llvm_unreachable("Unknown unconditional branch opcode!");
908 return 0;
909}
910
911
912void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
913 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
914 unsigned DestReg, unsigned BaseReg, int NumBytes,
915 ARMCC::CondCodes Pred, unsigned PredReg,
916 const ARMBaseInstrInfo &TII) {
917 bool isSub = NumBytes < 0;
918 if (isSub) NumBytes = -NumBytes;
919
920 while (NumBytes) {
921 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
922 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
923 assert(ThisVal && "Didn't extract field correctly");
924
925 // We will handle these bits from offset, clear them.
926 NumBytes &= ~ThisVal;
927
928 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
929
930 // Build the new ADD / SUB.
931 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
932 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
933 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
934 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
935 BaseReg = DestReg;
936 }
937}
938
939bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
940 unsigned FrameReg, int &Offset,
941 const ARMBaseInstrInfo &TII) {
942 unsigned Opcode = MI.getOpcode();
943 const TargetInstrDesc &Desc = MI.getDesc();
944 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
945 bool isSub = false;
946
947 // Memory operands in inline assembly always use AddrMode2.
948 if (Opcode == ARM::INLINEASM)
949 AddrMode = ARMII::AddrMode2;
950
951 if (Opcode == ARM::ADDri) {
952 Offset += MI.getOperand(FrameRegIdx+1).getImm();
953 if (Offset == 0) {
954 // Turn it into a move.
955 MI.setDesc(TII.get(ARM::MOVr));
956 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
957 MI.RemoveOperand(FrameRegIdx+1);
958 Offset = 0;
959 return true;
960 } else if (Offset < 0) {
961 Offset = -Offset;
962 isSub = true;
963 MI.setDesc(TII.get(ARM::SUBri));
964 }
965
966 // Common case: small offset, fits into instruction.
967 if (ARM_AM::getSOImmVal(Offset) != -1) {
968 // Replace the FrameIndex with sp / fp
969 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
970 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
971 Offset = 0;
972 return true;
973 }
974
975 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
976 // as possible.
977 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
978 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
979
980 // We will handle these bits from offset, clear them.
981 Offset &= ~ThisImmVal;
982
983 // Get the properly encoded SOImmVal field.
984 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
985 "Bit extraction didn't work?");
986 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
987 } else {
988 unsigned ImmIdx = 0;
989 int InstrOffs = 0;
990 unsigned NumBits = 0;
991 unsigned Scale = 1;
992 switch (AddrMode) {
993 case ARMII::AddrMode2: {
994 ImmIdx = FrameRegIdx+2;
995 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
996 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
997 InstrOffs *= -1;
998 NumBits = 12;
999 break;
1000 }
1001 case ARMII::AddrMode3: {
1002 ImmIdx = FrameRegIdx+2;
1003 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1004 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1005 InstrOffs *= -1;
1006 NumBits = 8;
1007 break;
1008 }
1009 case ARMII::AddrMode4:
1010 // Can't fold any offset even if it's zero.
1011 return false;
1012 case ARMII::AddrMode5: {
1013 ImmIdx = FrameRegIdx+1;
1014 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1015 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1016 InstrOffs *= -1;
1017 NumBits = 8;
1018 Scale = 4;
1019 break;
1020 }
1021 default:
1022 llvm_unreachable("Unsupported addressing mode!");
1023 break;
1024 }
1025
1026 Offset += InstrOffs * Scale;
1027 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1028 if (Offset < 0) {
1029 Offset = -Offset;
1030 isSub = true;
1031 }
1032
1033 // Attempt to fold address comp. if opcode has offset bits
1034 if (NumBits > 0) {
1035 // Common case: small offset, fits into instruction.
1036 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1037 int ImmedOffset = Offset / Scale;
1038 unsigned Mask = (1 << NumBits) - 1;
1039 if ((unsigned)Offset <= Mask * Scale) {
1040 // Replace the FrameIndex with sp
1041 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1042 if (isSub)
1043 ImmedOffset |= 1 << NumBits;
1044 ImmOp.ChangeToImmediate(ImmedOffset);
1045 Offset = 0;
1046 return true;
1047 }
1048
1049 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1050 ImmedOffset = ImmedOffset & Mask;
1051 if (isSub)
1052 ImmedOffset |= 1 << NumBits;
1053 ImmOp.ChangeToImmediate(ImmedOffset);
1054 Offset &= ~(Mask*Scale);
1055 }
1056 }
1057
1058 Offset = (isSub) ? -Offset : Offset;
1059 return Offset == 0;
1060}
859 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
860 }
861 }
862
863 return NewMI;
864}
865
866MachineInstr*
867ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
868 MachineInstr* MI,
869 const SmallVectorImpl<unsigned> &Ops,
870 MachineInstr* LoadMI) const {
871 // FIXME
872 return 0;
873}
874
875bool
876ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
877 const SmallVectorImpl<unsigned> &Ops) const {
878 if (Ops.size() != 1) return false;
879
880 unsigned Opc = MI->getOpcode();
881 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
882 // If it is updating CPSR, then it cannot be folded.
883 return MI->getOperand(4).getReg() != ARM::CPSR ||
884 MI->getOperand(4).isDead();
885 } else if (Opc == ARM::tMOVgpr2gpr ||
886 Opc == ARM::tMOVtgpr2gpr ||
887 Opc == ARM::tMOVgpr2tgpr) {
888 return true;
889 } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) {
890 return true;
891 } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) {
892 return false; // FIXME
893 }
894
895 return false;
896}
897
898/// getInstrPredicate - If instruction is predicated, returns its predicate
899/// condition, otherwise returns AL. It also returns the condition code
900/// register by reference.
901ARMCC::CondCodes
902llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
903 int PIdx = MI->findFirstPredOperandIdx();
904 if (PIdx == -1) {
905 PredReg = 0;
906 return ARMCC::AL;
907 }
908
909 PredReg = MI->getOperand(PIdx+1).getReg();
910 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
911}
912
913
914int llvm::getMatchingCondBranchOpcode(int Opc) {
915 if (Opc == ARM::B)
916 return ARM::Bcc;
917 else if (Opc == ARM::tB)
918 return ARM::tBcc;
919 else if (Opc == ARM::t2B)
920 return ARM::t2Bcc;
921
922 llvm_unreachable("Unknown unconditional branch opcode!");
923 return 0;
924}
925
926
927void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
928 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
929 unsigned DestReg, unsigned BaseReg, int NumBytes,
930 ARMCC::CondCodes Pred, unsigned PredReg,
931 const ARMBaseInstrInfo &TII) {
932 bool isSub = NumBytes < 0;
933 if (isSub) NumBytes = -NumBytes;
934
935 while (NumBytes) {
936 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
937 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
938 assert(ThisVal && "Didn't extract field correctly");
939
940 // We will handle these bits from offset, clear them.
941 NumBytes &= ~ThisVal;
942
943 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
944
945 // Build the new ADD / SUB.
946 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
947 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
948 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
949 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
950 BaseReg = DestReg;
951 }
952}
953
954bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
955 unsigned FrameReg, int &Offset,
956 const ARMBaseInstrInfo &TII) {
957 unsigned Opcode = MI.getOpcode();
958 const TargetInstrDesc &Desc = MI.getDesc();
959 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
960 bool isSub = false;
961
962 // Memory operands in inline assembly always use AddrMode2.
963 if (Opcode == ARM::INLINEASM)
964 AddrMode = ARMII::AddrMode2;
965
966 if (Opcode == ARM::ADDri) {
967 Offset += MI.getOperand(FrameRegIdx+1).getImm();
968 if (Offset == 0) {
969 // Turn it into a move.
970 MI.setDesc(TII.get(ARM::MOVr));
971 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
972 MI.RemoveOperand(FrameRegIdx+1);
973 Offset = 0;
974 return true;
975 } else if (Offset < 0) {
976 Offset = -Offset;
977 isSub = true;
978 MI.setDesc(TII.get(ARM::SUBri));
979 }
980
981 // Common case: small offset, fits into instruction.
982 if (ARM_AM::getSOImmVal(Offset) != -1) {
983 // Replace the FrameIndex with sp / fp
984 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
985 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
986 Offset = 0;
987 return true;
988 }
989
990 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
991 // as possible.
992 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
993 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
994
995 // We will handle these bits from offset, clear them.
996 Offset &= ~ThisImmVal;
997
998 // Get the properly encoded SOImmVal field.
999 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1000 "Bit extraction didn't work?");
1001 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1002 } else {
1003 unsigned ImmIdx = 0;
1004 int InstrOffs = 0;
1005 unsigned NumBits = 0;
1006 unsigned Scale = 1;
1007 switch (AddrMode) {
1008 case ARMII::AddrMode2: {
1009 ImmIdx = FrameRegIdx+2;
1010 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1011 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1012 InstrOffs *= -1;
1013 NumBits = 12;
1014 break;
1015 }
1016 case ARMII::AddrMode3: {
1017 ImmIdx = FrameRegIdx+2;
1018 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1019 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1020 InstrOffs *= -1;
1021 NumBits = 8;
1022 break;
1023 }
1024 case ARMII::AddrMode4:
1025 // Can't fold any offset even if it's zero.
1026 return false;
1027 case ARMII::AddrMode5: {
1028 ImmIdx = FrameRegIdx+1;
1029 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1030 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1031 InstrOffs *= -1;
1032 NumBits = 8;
1033 Scale = 4;
1034 break;
1035 }
1036 default:
1037 llvm_unreachable("Unsupported addressing mode!");
1038 break;
1039 }
1040
1041 Offset += InstrOffs * Scale;
1042 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1043 if (Offset < 0) {
1044 Offset = -Offset;
1045 isSub = true;
1046 }
1047
1048 // Attempt to fold address comp. if opcode has offset bits
1049 if (NumBits > 0) {
1050 // Common case: small offset, fits into instruction.
1051 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1052 int ImmedOffset = Offset / Scale;
1053 unsigned Mask = (1 << NumBits) - 1;
1054 if ((unsigned)Offset <= Mask * Scale) {
1055 // Replace the FrameIndex with sp
1056 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1057 if (isSub)
1058 ImmedOffset |= 1 << NumBits;
1059 ImmOp.ChangeToImmediate(ImmedOffset);
1060 Offset = 0;
1061 return true;
1062 }
1063
1064 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1065 ImmedOffset = ImmedOffset & Mask;
1066 if (isSub)
1067 ImmedOffset |= 1 << NumBits;
1068 ImmOp.ChangeToImmediate(ImmedOffset);
1069 Offset &= ~(Mask*Scale);
1070 }
1071 }
1072
1073 Offset = (isSub) ? -Offset : Offset;
1074 return Offset == 0;
1075}