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sdiff udiff text old ( 199989 ) new ( 200581 )
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LegalizeVectorTypes.cpp (199989) LegalizeVectorTypes.cpp (200581)
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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49 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
50 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
51 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
52 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
53 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
54 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
55 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
56 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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49 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
50 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
51 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
52 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
53 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
54 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
55 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
56 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
57 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_SIGN_EXTEND_INREG(N); break;
57 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
58 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
59 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
60 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
61 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
62 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
63
64 case ISD::CTLZ:

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190 // truncated. Make that explicit here.
191 EVT EltVT = N->getValueType(0).getVectorElementType();
192 SDValue InOp = N->getOperand(0);
193 if (InOp.getValueType() != EltVT)
194 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
195 return InOp;
196}
197
58 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
59 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
60 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
61 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
62 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
63 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
64
65 case ISD::CTLZ:

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191 // truncated. Make that explicit here.
192 EVT EltVT = N->getValueType(0).getVectorElementType();
193 SDValue InOp = N->getOperand(0);
194 if (InOp.getValueType() != EltVT)
195 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
196 return InOp;
197}
198
199SDValue DAGTypeLegalizer::ScalarizeVecRes_SIGN_EXTEND_INREG(SDNode *N) {
200 EVT EltVT = N->getValueType(0).getVectorElementType();
201 SDValue LHS = GetScalarizedVector(N->getOperand(0));
202 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), EltVT,
203 LHS, N->getOperand(1));
204}
205
198SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
199 SDValue LHS = GetScalarizedVector(N->getOperand(1));
200 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
201 LHS.getValueType(), N->getOperand(0), LHS,
202 GetScalarizedVector(N->getOperand(2)));
203}
204
205SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {

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396 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
397 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
398 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
399 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
400 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
401 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
402 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
403 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
206SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
207 SDValue LHS = GetScalarizedVector(N->getOperand(1));
208 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
209 LHS.getValueType(), N->getOperand(0), LHS,
210 GetScalarizedVector(N->getOperand(2)));
211}
212
213SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {

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404 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
405 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
406 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
407 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
408 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
409 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
410 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
411 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
412 case ISD::SIGN_EXTEND_INREG: SplitVecRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
404 case ISD::LOAD:
405 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
406 break;
407 case ISD::SETCC:
408 case ISD::VSETCC:
409 SplitVecRes_SETCC(N, Lo, Hi);
410 break;
411 case ISD::VECTOR_SHUFFLE:

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695 SDValue &Hi) {
696 EVT LoVT, HiVT;
697 DebugLoc dl = N->getDebugLoc();
698 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
699 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
700 Hi = DAG.getUNDEF(HiVT);
701}
702
413 case ISD::LOAD:
414 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
415 break;
416 case ISD::SETCC:
417 case ISD::VSETCC:
418 SplitVecRes_SETCC(N, Lo, Hi);
419 break;
420 case ISD::VECTOR_SHUFFLE:

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704 SDValue &Hi) {
705 EVT LoVT, HiVT;
706 DebugLoc dl = N->getDebugLoc();
707 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
708 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
709 Hi = DAG.getUNDEF(HiVT);
710}
711
712void DAGTypeLegalizer::SplitVecRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo,
713 SDValue &Hi) {
714 SDValue LHSLo, LHSHi;
715 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
716 DebugLoc dl = N->getDebugLoc();
717
718 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
719 N->getOperand(1));
720 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
721 N->getOperand(1));
722}
723
703void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
704 SDValue &Hi) {
705 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
706 EVT LoVT, HiVT;
707 DebugLoc dl = LD->getDebugLoc();
708 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
709
710 ISD::LoadExtType ExtType = LD->getExtensionType();

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1136 case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break;
1137 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1138 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1139 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1140 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1141 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1142 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1143 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
724void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
725 SDValue &Hi) {
726 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
727 EVT LoVT, HiVT;
728 DebugLoc dl = LD->getDebugLoc();
729 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
730
731 ISD::LoadExtType ExtType = LD->getExtensionType();

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1157 case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break;
1158 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1159 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1160 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1161 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1162 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1163 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1164 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1165 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_SIGN_EXTEND_INREG(N); break;
1144 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1145 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1146 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1147 case ISD::VECTOR_SHUFFLE:
1148 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1149 break;
1150 case ISD::VSETCC:
1151 Res = WidenVecRes_VSETCC(N);

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1686}
1687
1688SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1689 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1690 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1691 WidenVT, N->getOperand(0));
1692}
1693
1166 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1167 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1168 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1169 case ISD::VECTOR_SHUFFLE:
1170 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1171 break;
1172 case ISD::VSETCC:
1173 Res = WidenVecRes_VSETCC(N);

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1708}
1709
1710SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1711 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1712 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1713 WidenVT, N->getOperand(0));
1714}
1715
1716SDValue DAGTypeLegalizer::WidenVecRes_SIGN_EXTEND_INREG(SDNode *N) {
1717 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1718 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
1719 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
1720 WidenVT, WidenLHS, N->getOperand(1));
1721}
1722
1694SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1695 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1696 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1697
1698 SDValue Cond1 = N->getOperand(0);
1699 EVT CondVT = Cond1.getValueType();
1700 if (CondVT.isVector()) {
1701 EVT CondEltVT = CondVT.getVectorElementType();

--- 494 unchanged lines hidden --- 		1723SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1724 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1725 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1726
1727 SDValue Cond1 = N->getOperand(0);
1728 EVT CondVT = Cond1.getValueType();
1729 if (CondVT.isVector()) {
1730 EVT CondEltVT = CondVT.getVectorElementType();

--- 494 unchanged lines hidden ---