LegalizeVectorOps.cpp (193323) | LegalizeVectorOps.cpp (193574) |
---|---|
1//===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 115 unchanged lines hidden (view full) --- 124 bool HasVectorValue = false; 125 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end(); 126 J != E; 127 ++J) 128 HasVectorValue |= J->isVector(); 129 if (!HasVectorValue) 130 return TranslateLegalizeResults(Op, Result); 131 | 1//===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 115 unchanged lines hidden (view full) --- 124 bool HasVectorValue = false; 125 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end(); 126 J != E; 127 ++J) 128 HasVectorValue |= J->isVector(); 129 if (!HasVectorValue) 130 return TranslateLegalizeResults(Op, Result); 131 |
132 MVT QueryType; |
|
132 switch (Op.getOpcode()) { 133 default: 134 return TranslateLegalizeResults(Op, Result); 135 case ISD::ADD: 136 case ISD::SUB: 137 case ISD::MUL: 138 case ISD::SDIV: 139 case ISD::UDIV: --- 17 unchanged lines hidden (view full) --- 157 case ISD::CTPOP: 158 case ISD::SELECT: 159 case ISD::SELECT_CC: 160 case ISD::VSETCC: 161 case ISD::ZERO_EXTEND: 162 case ISD::ANY_EXTEND: 163 case ISD::TRUNCATE: 164 case ISD::SIGN_EXTEND: | 133 switch (Op.getOpcode()) { 134 default: 135 return TranslateLegalizeResults(Op, Result); 136 case ISD::ADD: 137 case ISD::SUB: 138 case ISD::MUL: 139 case ISD::SDIV: 140 case ISD::UDIV: --- 17 unchanged lines hidden (view full) --- 158 case ISD::CTPOP: 159 case ISD::SELECT: 160 case ISD::SELECT_CC: 161 case ISD::VSETCC: 162 case ISD::ZERO_EXTEND: 163 case ISD::ANY_EXTEND: 164 case ISD::TRUNCATE: 165 case ISD::SIGN_EXTEND: |
165 case ISD::SINT_TO_FP: 166 case ISD::UINT_TO_FP: | |
167 case ISD::FP_TO_SINT: 168 case ISD::FP_TO_UINT: 169 case ISD::FNEG: 170 case ISD::FABS: 171 case ISD::FSQRT: 172 case ISD::FSIN: 173 case ISD::FCOS: 174 case ISD::FPOWI: 175 case ISD::FPOW: 176 case ISD::FLOG: 177 case ISD::FLOG2: 178 case ISD::FLOG10: 179 case ISD::FEXP: 180 case ISD::FEXP2: 181 case ISD::FCEIL: 182 case ISD::FTRUNC: 183 case ISD::FRINT: 184 case ISD::FNEARBYINT: 185 case ISD::FFLOOR: | 166 case ISD::FP_TO_SINT: 167 case ISD::FP_TO_UINT: 168 case ISD::FNEG: 169 case ISD::FABS: 170 case ISD::FSQRT: 171 case ISD::FSIN: 172 case ISD::FCOS: 173 case ISD::FPOWI: 174 case ISD::FPOW: 175 case ISD::FLOG: 176 case ISD::FLOG2: 177 case ISD::FLOG10: 178 case ISD::FEXP: 179 case ISD::FEXP2: 180 case ISD::FCEIL: 181 case ISD::FTRUNC: 182 case ISD::FRINT: 183 case ISD::FNEARBYINT: 184 case ISD::FFLOOR: |
185 QueryType = Node->getValueType(0); |
|
186 break; | 186 break; |
187 case ISD::SINT_TO_FP: 188 case ISD::UINT_TO_FP: 189 QueryType = Node->getOperand(0).getValueType(); 190 break; |
|
187 } 188 | 191 } 192 |
189 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { | 193 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) { |
190 case TargetLowering::Promote: 191 // "Promote" the operation by bitcasting 192 Result = PromoteVectorOp(Op); 193 Changed = true; 194 break; 195 case TargetLowering::Legal: break; 196 case TargetLowering::Custom: { 197 SDValue Tmp1 = TLI.LowerOperation(Op, DAG); --- 138 unchanged lines hidden --- | 194 case TargetLowering::Promote: 195 // "Promote" the operation by bitcasting 196 Result = PromoteVectorOp(Op); 197 Changed = true; 198 break; 199 case TargetLowering::Legal: break; 200 case TargetLowering::Custom: { 201 SDValue Tmp1 = TLI.LowerOperation(Op, DAG); --- 138 unchanged lines hidden --- |