1//===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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41#include "llvm/Target/TargetRegisterInfo.h"
42#include "llvm/Target/TargetSubtarget.h"
43#include "llvm/Support/CommandLine.h"
44#include "llvm/Support/Debug.h"
45#include "llvm/Support/ErrorHandling.h"
46#include "llvm/Support/raw_ostream.h"
47#include "llvm/ADT/BitVector.h"
48#include "llvm/ADT/Statistic.h"
49#include <set>
50using namespace llvm;
51
52STATISTIC(NumNoops, "Number of noops inserted");
53STATISTIC(NumStalls, "Number of pipeline stalls");
54STATISTIC(NumFixedAnti, "Number of fixed anti-dependencies");
55
56// Post-RA scheduling is enabled with

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260 dbgs() << "*** DEBUG scheduling " << Fn.getFunction()->getNameStr() <<
261 ":BB#" << MBB->getNumber() << " ***\n";
262 }
263#endif
264
265 // Initialize register live-range state for scheduling in this block.
266 Scheduler.StartBlock(MBB);
267
268 // FIXME: Temporary workaround for <rdar://problem/7759363>: The post-RA
269 // scheduler has some sort of problem with DebugValue instructions that
270 // causes an assertion in LeaksContext.h to fail occasionally. Just
271 // remove all those instructions for now.
272 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
273 I != E; ) {
274 MachineInstr *MI = &*I++;
275 if (MI->isDebugValue())
276 MI->eraseFromParent();
277 }
278
279 // Schedule each sequence of instructions not interrupted by a label
280 // or anything else that effectively needs to shut down scheduling.
281 MachineBasicBlock::iterator Current = MBB->end();
282 unsigned Count = MBB->size(), CurrentCount = Count;
283 for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) {
284 MachineInstr *MI = prior(I);
285 if (isSchedulingBoundary(MI, Fn)) {
286 Scheduler.Run(MBB, I, Current, CurrentCount);
287 Scheduler.EmitSchedule();
288 Current = MI;
289 CurrentCount = Count - 1;
290 Scheduler.Observe(MI, CurrentCount);
291 }
292 I = MI;
293 --Count;
294 }
295 assert(Count == 0 && "Instruction count mismatch!");
296 assert((MBB->begin() == Current || CurrentCount != 0) &&
297 "Instruction count mismatch!");
298 Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount);
299 Scheduler.EmitSchedule();
300
301 // Clean up register live-range state.
302 Scheduler.FinishBlock();
303
304 // Update register kills
305 Scheduler.FixupKills(MBB);
306 }
307

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