1//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This pass eliminates machine instruction PHI nodes by inserting copy
11// instructions. This destroys SSA information, but is the desired input for
12// some register allocators.
13//
14//===----------------------------------------------------------------------===//
15
16#define DEBUG_TYPE "phielim"
17#include "PHIElimination.h"
18#include "llvm/CodeGen/LiveVariables.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/CodeGen/MachineDominators.h"
21#include "llvm/CodeGen/MachineInstr.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
| 1//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This pass eliminates machine instruction PHI nodes by inserting copy
11// instructions. This destroys SSA information, but is the desired input for
12// some register allocators.
13//
14//===----------------------------------------------------------------------===//
15
16#define DEBUG_TYPE "phielim"
17#include "PHIElimination.h"
18#include "llvm/CodeGen/LiveVariables.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/CodeGen/MachineDominators.h"
21#include "llvm/CodeGen/MachineInstr.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
|
24#include "llvm/CodeGen/RegAllocRegistry.h"
| |
25#include "llvm/Function.h"
26#include "llvm/Target/TargetMachine.h"
27#include "llvm/ADT/SmallPtrSet.h"
28#include "llvm/ADT/STLExtras.h"
29#include "llvm/ADT/Statistic.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Support/Debug.h"
33#include <algorithm>
34#include <map>
35using namespace llvm;
36
37STATISTIC(NumAtomic, "Number of atomic phis lowered");
38STATISTIC(NumSplits, "Number of critical edges split on demand");
39
| 24#include "llvm/Function.h"
25#include "llvm/Target/TargetMachine.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/STLExtras.h"
28#include "llvm/ADT/Statistic.h"
29#include "llvm/Support/CommandLine.h"
30#include "llvm/Support/Compiler.h"
31#include "llvm/Support/Debug.h"
32#include <algorithm>
33#include <map>
34using namespace llvm;
35
36STATISTIC(NumAtomic, "Number of atomic phis lowered");
37STATISTIC(NumSplits, "Number of critical edges split on demand");
38
|
40static cl::opt<bool>
41SplitEdges("split-phi-edges",
42 cl::desc("Split critical edges during phi elimination"),
43 cl::init(false), cl::Hidden);
44
| |
45char PHIElimination::ID = 0;
46static RegisterPass<PHIElimination>
47X("phi-node-elimination", "Eliminate PHI nodes for register allocation");
48
49const PassInfo *const llvm::PHIEliminationID = &X;
50
| 39char PHIElimination::ID = 0;
40static RegisterPass<PHIElimination>
41X("phi-node-elimination", "Eliminate PHI nodes for register allocation");
42
43const PassInfo *const llvm::PHIEliminationID = &X;
44
|
51namespace llvm { FunctionPass *createLocalRegisterAllocator(); }
52
53// Should we run edge splitting?
54static bool shouldSplitEdges() {
55 // Edge splitting breaks the local register allocator. It cannot tolerate
56 // LiveVariables being run.
57 if (RegisterRegAlloc::getDefault() == createLocalRegisterAllocator)
58 return false;
59 return SplitEdges;
60}
61
| |
62void llvm::PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
63 AU.addPreserved<LiveVariables>();
64 AU.addPreserved<MachineDominatorTree>();
| 45void llvm::PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
46 AU.addPreserved<LiveVariables>();
47 AU.addPreserved<MachineDominatorTree>();
|
65 if (shouldSplitEdges()) {
66 AU.addRequired<LiveVariables>();
67 } else {
68 AU.setPreservesCFG();
69 AU.addPreservedID(MachineLoopInfoID);
70 }
| 48 // rdar://7401784 This would be nice:
49 // AU.addPreservedID(MachineLoopInfoID);
|
71 MachineFunctionPass::getAnalysisUsage(AU);
72}
73
74bool llvm::PHIElimination::runOnMachineFunction(MachineFunction &Fn) {
75 MRI = &Fn.getRegInfo();
76
77 PHIDefs.clear();
78 PHIKills.clear();
79 bool Changed = false;
80
81 // Split critical edges to help the coalescer
| 50 MachineFunctionPass::getAnalysisUsage(AU);
51}
52
53bool llvm::PHIElimination::runOnMachineFunction(MachineFunction &Fn) {
54 MRI = &Fn.getRegInfo();
55
56 PHIDefs.clear();
57 PHIKills.clear();
58 bool Changed = false;
59
60 // Split critical edges to help the coalescer
|
82 if (shouldSplitEdges())
| 61 if (LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>())
|
83 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
| 62 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
|
84 Changed |= SplitPHIEdges(Fn, *I);
| 63 Changed |= SplitPHIEdges(Fn, *I, *LV);
|
85
86 // Populate VRegPHIUseCount
87 analyzePHINodes(Fn);
88
89 // Eliminate PHI instructions by inserting copies into predecessor blocks.
90 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
91 Changed |= EliminatePHINodes(Fn, *I);
92
93 // Remove dead IMPLICIT_DEF instructions.
94 for (SmallPtrSet<MachineInstr*,4>::iterator I = ImpDefs.begin(),
95 E = ImpDefs.end(); I != E; ++I) {
96 MachineInstr *DefMI = *I;
97 unsigned DefReg = DefMI->getOperand(0).getReg();
98 if (MRI->use_empty(DefReg))
99 DefMI->eraseFromParent();
100 }
101
102 ImpDefs.clear();
103 VRegPHIUseCount.clear();
104 return Changed;
105}
106
107/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
108/// predecessor basic blocks.
109///
110bool llvm::PHIElimination::EliminatePHINodes(MachineFunction &MF,
111 MachineBasicBlock &MBB) {
112 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
113 return false; // Quick exit for basic blocks without PHIs.
114
115 // Get an iterator to the first instruction after the last PHI node (this may
116 // also be the end of the basic block).
117 MachineBasicBlock::iterator AfterPHIsIt = SkipPHIsAndLabels(MBB, MBB.begin());
118
119 while (MBB.front().getOpcode() == TargetInstrInfo::PHI)
120 LowerAtomicPHINode(MBB, AfterPHIsIt);
121
122 return true;
123}
124
125/// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
126/// are implicit_def's.
127static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
128 const MachineRegisterInfo *MRI) {
129 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
130 unsigned SrcReg = MPhi->getOperand(i).getReg();
131 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
132 if (!DefMI || DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
133 return false;
134 }
135 return true;
136}
137
138// FindCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg
139// when following the CFG edge to SuccMBB. This needs to be after any def of
140// SrcReg, but before any subsequent point where control flow might jump out of
141// the basic block.
142MachineBasicBlock::iterator
143llvm::PHIElimination::FindCopyInsertPoint(MachineBasicBlock &MBB,
144 MachineBasicBlock &SuccMBB,
145 unsigned SrcReg) {
146 // Handle the trivial case trivially.
147 if (MBB.empty())
148 return MBB.begin();
149
150 // Usually, we just want to insert the copy before the first terminator
151 // instruction. However, for the edge going to a landing pad, we must insert
152 // the copy before the call/invoke instruction.
153 if (!SuccMBB.isLandingPad())
154 return MBB.getFirstTerminator();
155
156 // Discover any defs/uses in this basic block.
157 SmallPtrSet<MachineInstr*, 8> DefUsesInMBB;
158 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
159 RE = MRI->reg_end(); RI != RE; ++RI) {
160 MachineInstr *DefUseMI = &*RI;
161 if (DefUseMI->getParent() == &MBB)
162 DefUsesInMBB.insert(DefUseMI);
163 }
164
165 MachineBasicBlock::iterator InsertPoint;
166 if (DefUsesInMBB.empty()) {
167 // No defs. Insert the copy at the start of the basic block.
168 InsertPoint = MBB.begin();
169 } else if (DefUsesInMBB.size() == 1) {
170 // Insert the copy immediately after the def/use.
171 InsertPoint = *DefUsesInMBB.begin();
172 ++InsertPoint;
173 } else {
174 // Insert the copy immediately after the last def/use.
175 InsertPoint = MBB.end();
176 while (!DefUsesInMBB.count(&*--InsertPoint)) {}
177 ++InsertPoint;
178 }
179
180 // Make sure the copy goes after any phi nodes however.
181 return SkipPHIsAndLabels(MBB, InsertPoint);
182}
183
184/// LowerAtomicPHINode - Lower the PHI node at the top of the specified block,
185/// under the assuption that it needs to be lowered in a way that supports
186/// atomic execution of PHIs. This lowering method is always correct all of the
187/// time.
188///
189void llvm::PHIElimination::LowerAtomicPHINode(
190 MachineBasicBlock &MBB,
191 MachineBasicBlock::iterator AfterPHIsIt) {
192 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
193 MachineInstr *MPhi = MBB.remove(MBB.begin());
194
195 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
196 unsigned DestReg = MPhi->getOperand(0).getReg();
197 bool isDead = MPhi->getOperand(0).isDead();
198
199 // Create a new register for the incoming PHI arguments.
200 MachineFunction &MF = *MBB.getParent();
201 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
202 unsigned IncomingReg = 0;
203
204 // Insert a register to register copy at the top of the current block (but
205 // after any remaining phi nodes) which copies the new incoming register
206 // into the phi node destination.
207 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
208 if (isSourceDefinedByImplicitDef(MPhi, MRI))
209 // If all sources of a PHI node are implicit_def, just emit an
210 // implicit_def instead of a copy.
211 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
212 TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg);
213 else {
214 IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
215 TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
216 }
217
218 // Record PHI def.
219 assert(!hasPHIDef(DestReg) && "Vreg has multiple phi-defs?");
220 PHIDefs[DestReg] = &MBB;
221
222 // Update live variable information if there is any.
223 LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>();
224 if (LV) {
225 MachineInstr *PHICopy = prior(AfterPHIsIt);
226
227 if (IncomingReg) {
228 // Increment use count of the newly created virtual register.
229 LV->getVarInfo(IncomingReg).NumUses++;
230
231 // Add information to LiveVariables to know that the incoming value is
232 // killed. Note that because the value is defined in several places (once
233 // each for each incoming block), the "def" block and instruction fields
234 // for the VarInfo is not filled in.
235 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
236 }
237
238 // Since we are going to be deleting the PHI node, if it is the last use of
239 // any registers, or if the value itself is dead, we need to move this
240 // information over to the new copy we just inserted.
241 LV->removeVirtualRegistersKilled(MPhi);
242
243 // If the result is dead, update LV.
244 if (isDead) {
245 LV->addVirtualRegisterDead(DestReg, PHICopy);
246 LV->removeVirtualRegisterDead(DestReg, MPhi);
247 }
248 }
249
250 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
251 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
252 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i + 1).getMBB(),
253 MPhi->getOperand(i).getReg())];
254
255 // Now loop over all of the incoming arguments, changing them to copy into the
256 // IncomingReg register in the corresponding predecessor basic block.
257 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
258 for (int i = NumSrcs - 1; i >= 0; --i) {
259 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
260 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
261 "Machine PHI Operands must all be virtual registers!");
262
263 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
264 // path the PHI.
265 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
266
267 // Record the kill.
268 PHIKills[SrcReg].insert(&opBlock);
269
270 // If source is defined by an implicit def, there is no need to insert a
271 // copy.
272 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
273 if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
274 ImpDefs.insert(DefMI);
275 continue;
276 }
277
278 // Check to make sure we haven't already emitted the copy for this block.
279 // This can happen because PHI nodes may have multiple entries for the same
280 // basic block.
281 if (!MBBsInsertedInto.insert(&opBlock))
282 continue; // If the copy has already been emitted, we're done.
283
284 // Find a safe location to insert the copy, this may be the first terminator
285 // in the block (or end()).
286 MachineBasicBlock::iterator InsertPos =
287 FindCopyInsertPoint(opBlock, MBB, SrcReg);
288
289 // Insert the copy.
290 TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC);
291
292 // Now update live variable information if we have it. Otherwise we're done
293 if (!LV) continue;
294
295 // We want to be able to insert a kill of the register if this PHI (aka, the
296 // copy we just inserted) is the last use of the source value. Live
297 // variable analysis conservatively handles this by saying that the value is
298 // live until the end of the block the PHI entry lives in. If the value
299 // really is dead at the PHI copy, there will be no successor blocks which
300 // have the value live-in.
301
302 // Also check to see if this register is in use by another PHI node which
303 // has not yet been eliminated. If so, it will be killed at an appropriate
304 // point later.
305
306 // Is it used by any PHI instructions in this block?
307 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(&opBlock, SrcReg)] != 0;
308
309 // Okay, if we now know that the value is not live out of the block, we can
310 // add a kill marker in this block saying that it kills the incoming value!
311 if (!ValueIsUsed && !isLiveOut(SrcReg, opBlock, *LV)) {
312 // In our final twist, we have to decide which instruction kills the
313 // register. In most cases this is the copy, however, the first
314 // terminator instruction at the end of the block may also use the value.
315 // In this case, we should mark *it* as being the killing block, not the
316 // copy.
317 MachineBasicBlock::iterator KillInst = prior(InsertPos);
318 MachineBasicBlock::iterator Term = opBlock.getFirstTerminator();
319 if (Term != opBlock.end()) {
320 if (Term->readsRegister(SrcReg))
321 KillInst = Term;
322
323 // Check that no other terminators use values.
324#ifndef NDEBUG
325 for (MachineBasicBlock::iterator TI = next(Term); TI != opBlock.end();
326 ++TI) {
327 assert(!TI->readsRegister(SrcReg) &&
328 "Terminator instructions cannot use virtual registers unless"
329 "they are the first terminator in a block!");
330 }
331#endif
332 }
333
334 // Finally, mark it killed.
335 LV->addVirtualRegisterKilled(SrcReg, KillInst);
336
337 // This vreg no longer lives all of the way through opBlock.
338 unsigned opBlockNum = opBlock.getNumber();
339 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
340 }
341 }
342
343 // Really delete the PHI instruction now!
344 MF.DeleteMachineInstr(MPhi);
345 ++NumAtomic;
346}
347
348/// analyzePHINodes - Gather information about the PHI nodes in here. In
349/// particular, we want to map the number of uses of a virtual register which is
350/// used in a PHI node. We map that to the BB the vreg is coming from. This is
351/// used later to determine when the vreg is killed in the BB.
352///
353void llvm::PHIElimination::analyzePHINodes(const MachineFunction& Fn) {
354 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
355 I != E; ++I)
356 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
357 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
358 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
359 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i + 1).getMBB(),
360 BBI->getOperand(i).getReg())];
361}
362
363bool llvm::PHIElimination::SplitPHIEdges(MachineFunction &MF,
| 64
65 // Populate VRegPHIUseCount
66 analyzePHINodes(Fn);
67
68 // Eliminate PHI instructions by inserting copies into predecessor blocks.
69 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
70 Changed |= EliminatePHINodes(Fn, *I);
71
72 // Remove dead IMPLICIT_DEF instructions.
73 for (SmallPtrSet<MachineInstr*,4>::iterator I = ImpDefs.begin(),
74 E = ImpDefs.end(); I != E; ++I) {
75 MachineInstr *DefMI = *I;
76 unsigned DefReg = DefMI->getOperand(0).getReg();
77 if (MRI->use_empty(DefReg))
78 DefMI->eraseFromParent();
79 }
80
81 ImpDefs.clear();
82 VRegPHIUseCount.clear();
83 return Changed;
84}
85
86/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
87/// predecessor basic blocks.
88///
89bool llvm::PHIElimination::EliminatePHINodes(MachineFunction &MF,
90 MachineBasicBlock &MBB) {
91 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
92 return false; // Quick exit for basic blocks without PHIs.
93
94 // Get an iterator to the first instruction after the last PHI node (this may
95 // also be the end of the basic block).
96 MachineBasicBlock::iterator AfterPHIsIt = SkipPHIsAndLabels(MBB, MBB.begin());
97
98 while (MBB.front().getOpcode() == TargetInstrInfo::PHI)
99 LowerAtomicPHINode(MBB, AfterPHIsIt);
100
101 return true;
102}
103
104/// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
105/// are implicit_def's.
106static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
107 const MachineRegisterInfo *MRI) {
108 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
109 unsigned SrcReg = MPhi->getOperand(i).getReg();
110 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
111 if (!DefMI || DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
112 return false;
113 }
114 return true;
115}
116
117// FindCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg
118// when following the CFG edge to SuccMBB. This needs to be after any def of
119// SrcReg, but before any subsequent point where control flow might jump out of
120// the basic block.
121MachineBasicBlock::iterator
122llvm::PHIElimination::FindCopyInsertPoint(MachineBasicBlock &MBB,
123 MachineBasicBlock &SuccMBB,
124 unsigned SrcReg) {
125 // Handle the trivial case trivially.
126 if (MBB.empty())
127 return MBB.begin();
128
129 // Usually, we just want to insert the copy before the first terminator
130 // instruction. However, for the edge going to a landing pad, we must insert
131 // the copy before the call/invoke instruction.
132 if (!SuccMBB.isLandingPad())
133 return MBB.getFirstTerminator();
134
135 // Discover any defs/uses in this basic block.
136 SmallPtrSet<MachineInstr*, 8> DefUsesInMBB;
137 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
138 RE = MRI->reg_end(); RI != RE; ++RI) {
139 MachineInstr *DefUseMI = &*RI;
140 if (DefUseMI->getParent() == &MBB)
141 DefUsesInMBB.insert(DefUseMI);
142 }
143
144 MachineBasicBlock::iterator InsertPoint;
145 if (DefUsesInMBB.empty()) {
146 // No defs. Insert the copy at the start of the basic block.
147 InsertPoint = MBB.begin();
148 } else if (DefUsesInMBB.size() == 1) {
149 // Insert the copy immediately after the def/use.
150 InsertPoint = *DefUsesInMBB.begin();
151 ++InsertPoint;
152 } else {
153 // Insert the copy immediately after the last def/use.
154 InsertPoint = MBB.end();
155 while (!DefUsesInMBB.count(&*--InsertPoint)) {}
156 ++InsertPoint;
157 }
158
159 // Make sure the copy goes after any phi nodes however.
160 return SkipPHIsAndLabels(MBB, InsertPoint);
161}
162
163/// LowerAtomicPHINode - Lower the PHI node at the top of the specified block,
164/// under the assuption that it needs to be lowered in a way that supports
165/// atomic execution of PHIs. This lowering method is always correct all of the
166/// time.
167///
168void llvm::PHIElimination::LowerAtomicPHINode(
169 MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator AfterPHIsIt) {
171 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
172 MachineInstr *MPhi = MBB.remove(MBB.begin());
173
174 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
175 unsigned DestReg = MPhi->getOperand(0).getReg();
176 bool isDead = MPhi->getOperand(0).isDead();
177
178 // Create a new register for the incoming PHI arguments.
179 MachineFunction &MF = *MBB.getParent();
180 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
181 unsigned IncomingReg = 0;
182
183 // Insert a register to register copy at the top of the current block (but
184 // after any remaining phi nodes) which copies the new incoming register
185 // into the phi node destination.
186 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
187 if (isSourceDefinedByImplicitDef(MPhi, MRI))
188 // If all sources of a PHI node are implicit_def, just emit an
189 // implicit_def instead of a copy.
190 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
191 TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg);
192 else {
193 IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
194 TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
195 }
196
197 // Record PHI def.
198 assert(!hasPHIDef(DestReg) && "Vreg has multiple phi-defs?");
199 PHIDefs[DestReg] = &MBB;
200
201 // Update live variable information if there is any.
202 LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>();
203 if (LV) {
204 MachineInstr *PHICopy = prior(AfterPHIsIt);
205
206 if (IncomingReg) {
207 // Increment use count of the newly created virtual register.
208 LV->getVarInfo(IncomingReg).NumUses++;
209
210 // Add information to LiveVariables to know that the incoming value is
211 // killed. Note that because the value is defined in several places (once
212 // each for each incoming block), the "def" block and instruction fields
213 // for the VarInfo is not filled in.
214 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
215 }
216
217 // Since we are going to be deleting the PHI node, if it is the last use of
218 // any registers, or if the value itself is dead, we need to move this
219 // information over to the new copy we just inserted.
220 LV->removeVirtualRegistersKilled(MPhi);
221
222 // If the result is dead, update LV.
223 if (isDead) {
224 LV->addVirtualRegisterDead(DestReg, PHICopy);
225 LV->removeVirtualRegisterDead(DestReg, MPhi);
226 }
227 }
228
229 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
230 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
231 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i + 1).getMBB(),
232 MPhi->getOperand(i).getReg())];
233
234 // Now loop over all of the incoming arguments, changing them to copy into the
235 // IncomingReg register in the corresponding predecessor basic block.
236 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
237 for (int i = NumSrcs - 1; i >= 0; --i) {
238 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
239 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
240 "Machine PHI Operands must all be virtual registers!");
241
242 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
243 // path the PHI.
244 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
245
246 // Record the kill.
247 PHIKills[SrcReg].insert(&opBlock);
248
249 // If source is defined by an implicit def, there is no need to insert a
250 // copy.
251 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
252 if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
253 ImpDefs.insert(DefMI);
254 continue;
255 }
256
257 // Check to make sure we haven't already emitted the copy for this block.
258 // This can happen because PHI nodes may have multiple entries for the same
259 // basic block.
260 if (!MBBsInsertedInto.insert(&opBlock))
261 continue; // If the copy has already been emitted, we're done.
262
263 // Find a safe location to insert the copy, this may be the first terminator
264 // in the block (or end()).
265 MachineBasicBlock::iterator InsertPos =
266 FindCopyInsertPoint(opBlock, MBB, SrcReg);
267
268 // Insert the copy.
269 TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC);
270
271 // Now update live variable information if we have it. Otherwise we're done
272 if (!LV) continue;
273
274 // We want to be able to insert a kill of the register if this PHI (aka, the
275 // copy we just inserted) is the last use of the source value. Live
276 // variable analysis conservatively handles this by saying that the value is
277 // live until the end of the block the PHI entry lives in. If the value
278 // really is dead at the PHI copy, there will be no successor blocks which
279 // have the value live-in.
280
281 // Also check to see if this register is in use by another PHI node which
282 // has not yet been eliminated. If so, it will be killed at an appropriate
283 // point later.
284
285 // Is it used by any PHI instructions in this block?
286 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(&opBlock, SrcReg)] != 0;
287
288 // Okay, if we now know that the value is not live out of the block, we can
289 // add a kill marker in this block saying that it kills the incoming value!
290 if (!ValueIsUsed && !isLiveOut(SrcReg, opBlock, *LV)) {
291 // In our final twist, we have to decide which instruction kills the
292 // register. In most cases this is the copy, however, the first
293 // terminator instruction at the end of the block may also use the value.
294 // In this case, we should mark *it* as being the killing block, not the
295 // copy.
296 MachineBasicBlock::iterator KillInst = prior(InsertPos);
297 MachineBasicBlock::iterator Term = opBlock.getFirstTerminator();
298 if (Term != opBlock.end()) {
299 if (Term->readsRegister(SrcReg))
300 KillInst = Term;
301
302 // Check that no other terminators use values.
303#ifndef NDEBUG
304 for (MachineBasicBlock::iterator TI = next(Term); TI != opBlock.end();
305 ++TI) {
306 assert(!TI->readsRegister(SrcReg) &&
307 "Terminator instructions cannot use virtual registers unless"
308 "they are the first terminator in a block!");
309 }
310#endif
311 }
312
313 // Finally, mark it killed.
314 LV->addVirtualRegisterKilled(SrcReg, KillInst);
315
316 // This vreg no longer lives all of the way through opBlock.
317 unsigned opBlockNum = opBlock.getNumber();
318 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
319 }
320 }
321
322 // Really delete the PHI instruction now!
323 MF.DeleteMachineInstr(MPhi);
324 ++NumAtomic;
325}
326
327/// analyzePHINodes - Gather information about the PHI nodes in here. In
328/// particular, we want to map the number of uses of a virtual register which is
329/// used in a PHI node. We map that to the BB the vreg is coming from. This is
330/// used later to determine when the vreg is killed in the BB.
331///
332void llvm::PHIElimination::analyzePHINodes(const MachineFunction& Fn) {
333 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
334 I != E; ++I)
335 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
336 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
337 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
338 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i + 1).getMBB(),
339 BBI->getOperand(i).getReg())];
340}
341
342bool llvm::PHIElimination::SplitPHIEdges(MachineFunction &MF,
|
364 MachineBasicBlock &MBB) {
| 343 MachineBasicBlock &MBB,
344 LiveVariables &LV) {
|
365 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
366 return false; // Quick exit for basic blocks without PHIs.
| 345 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
346 return false; // Quick exit for basic blocks without PHIs.
|
367 LiveVariables &LV = getAnalysis<LiveVariables>();
| 347
|
368 for (MachineBasicBlock::const_iterator BBI = MBB.begin(), BBE = MBB.end();
369 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
370 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
371 unsigned Reg = BBI->getOperand(i).getReg();
372 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
373 // We break edges when registers are live out from the predecessor block
374 // (not considering PHI nodes). If the register is live in to this block
375 // anyway, we would gain nothing from splitting.
376 if (isLiveOut(Reg, *PreMBB, LV) && !isLiveIn(Reg, MBB, LV))
377 SplitCriticalEdge(PreMBB, &MBB);
378 }
379 }
380 return true;
381}
382
383bool llvm::PHIElimination::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB,
384 LiveVariables &LV) {
385 LiveVariables::VarInfo &VI = LV.getVarInfo(Reg);
386
387 // Loop over all of the successors of the basic block, checking to see if
388 // the value is either live in the block, or if it is killed in the block.
389 std::vector<MachineBasicBlock*> OpSuccBlocks;
390 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
391 E = MBB.succ_end(); SI != E; ++SI) {
392 MachineBasicBlock *SuccMBB = *SI;
393
394 // Is it alive in this successor?
395 unsigned SuccIdx = SuccMBB->getNumber();
396 if (VI.AliveBlocks.test(SuccIdx))
397 return true;
398 OpSuccBlocks.push_back(SuccMBB);
399 }
400
401 // Check to see if this value is live because there is a use in a successor
402 // that kills it.
403 switch (OpSuccBlocks.size()) {
404 case 1: {
405 MachineBasicBlock *SuccMBB = OpSuccBlocks[0];
406 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
407 if (VI.Kills[i]->getParent() == SuccMBB)
408 return true;
409 break;
410 }
411 case 2: {
412 MachineBasicBlock *SuccMBB1 = OpSuccBlocks[0], *SuccMBB2 = OpSuccBlocks[1];
413 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
414 if (VI.Kills[i]->getParent() == SuccMBB1 ||
415 VI.Kills[i]->getParent() == SuccMBB2)
416 return true;
417 break;
418 }
419 default:
420 std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end());
421 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
422 if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(),
423 VI.Kills[i]->getParent()))
424 return true;
425 }
426 return false;
427}
428
429bool llvm::PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock &MBB,
430 LiveVariables &LV) {
431 LiveVariables::VarInfo &VI = LV.getVarInfo(Reg);
432
433 if (VI.AliveBlocks.test(MBB.getNumber()))
434 return true;
435
436 // defined in MBB?
437 const MachineInstr *Def = MRI->getVRegDef(Reg);
438 if (Def && Def->getParent() == &MBB)
439 return false;
440
441 // killed in MBB?
442 return VI.findKill(&MBB);
443}
444
445MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A,
446 MachineBasicBlock *B) {
447 assert(A && B && "Missing MBB end point");
448
449 MachineFunction *MF = A->getParent();
450
451 // We may need to update A's terminator, but we can't do that if AnalyzeBranch
452 // fails. If A uses a jump table, we won't touch it.
453 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
454 MachineBasicBlock *TBB = 0, *FBB = 0;
455 SmallVector<MachineOperand, 4> Cond;
456 if (TII->AnalyzeBranch(*A, TBB, FBB, Cond))
457 return NULL;
458
459 ++NumSplits;
460
461 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
462 MF->push_back(NMBB);
463 DEBUG(errs() << "PHIElimination splitting critical edge:"
464 " BB#" << A->getNumber()
465 << " -- BB#" << NMBB->getNumber()
466 << " -- BB#" << B->getNumber() << '\n');
467
468 A->ReplaceUsesOfBlockWith(B, NMBB);
469 // If A may fall through to B, we may have to insert a branch.
470 if (A->isLayoutSuccessor(B))
471 A->updateTerminator();
472
473 // Insert unconditional "jump B" instruction in NMBB.
474 NMBB->addSuccessor(B);
475 Cond.clear();
476 MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond);
477
478 // Fix PHI nodes in B so they refer to NMBB instead of A
479 for (MachineBasicBlock::iterator i = B->begin(), e = B->end();
480 i != e && i->getOpcode() == TargetInstrInfo::PHI; ++i)
481 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
482 if (i->getOperand(ni+1).getMBB() == A)
483 i->getOperand(ni+1).setMBB(NMBB);
484
485 if (LiveVariables *LV=getAnalysisIfAvailable<LiveVariables>())
486 LV->addNewBlock(NMBB, A);
487
488 if (MachineDominatorTree *MDT=getAnalysisIfAvailable<MachineDominatorTree>())
489 MDT->addNewBlock(NMBB, A);
490
491 return NMBB;
492}
| 348 for (MachineBasicBlock::const_iterator BBI = MBB.begin(), BBE = MBB.end();
349 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
350 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
351 unsigned Reg = BBI->getOperand(i).getReg();
352 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
353 // We break edges when registers are live out from the predecessor block
354 // (not considering PHI nodes). If the register is live in to this block
355 // anyway, we would gain nothing from splitting.
356 if (isLiveOut(Reg, *PreMBB, LV) && !isLiveIn(Reg, MBB, LV))
357 SplitCriticalEdge(PreMBB, &MBB);
358 }
359 }
360 return true;
361}
362
363bool llvm::PHIElimination::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB,
364 LiveVariables &LV) {
365 LiveVariables::VarInfo &VI = LV.getVarInfo(Reg);
366
367 // Loop over all of the successors of the basic block, checking to see if
368 // the value is either live in the block, or if it is killed in the block.
369 std::vector<MachineBasicBlock*> OpSuccBlocks;
370 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
371 E = MBB.succ_end(); SI != E; ++SI) {
372 MachineBasicBlock *SuccMBB = *SI;
373
374 // Is it alive in this successor?
375 unsigned SuccIdx = SuccMBB->getNumber();
376 if (VI.AliveBlocks.test(SuccIdx))
377 return true;
378 OpSuccBlocks.push_back(SuccMBB);
379 }
380
381 // Check to see if this value is live because there is a use in a successor
382 // that kills it.
383 switch (OpSuccBlocks.size()) {
384 case 1: {
385 MachineBasicBlock *SuccMBB = OpSuccBlocks[0];
386 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
387 if (VI.Kills[i]->getParent() == SuccMBB)
388 return true;
389 break;
390 }
391 case 2: {
392 MachineBasicBlock *SuccMBB1 = OpSuccBlocks[0], *SuccMBB2 = OpSuccBlocks[1];
393 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
394 if (VI.Kills[i]->getParent() == SuccMBB1 ||
395 VI.Kills[i]->getParent() == SuccMBB2)
396 return true;
397 break;
398 }
399 default:
400 std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end());
401 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
402 if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(),
403 VI.Kills[i]->getParent()))
404 return true;
405 }
406 return false;
407}
408
409bool llvm::PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock &MBB,
410 LiveVariables &LV) {
411 LiveVariables::VarInfo &VI = LV.getVarInfo(Reg);
412
413 if (VI.AliveBlocks.test(MBB.getNumber()))
414 return true;
415
416 // defined in MBB?
417 const MachineInstr *Def = MRI->getVRegDef(Reg);
418 if (Def && Def->getParent() == &MBB)
419 return false;
420
421 // killed in MBB?
422 return VI.findKill(&MBB);
423}
424
425MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A,
426 MachineBasicBlock *B) {
427 assert(A && B && "Missing MBB end point");
428
429 MachineFunction *MF = A->getParent();
430
431 // We may need to update A's terminator, but we can't do that if AnalyzeBranch
432 // fails. If A uses a jump table, we won't touch it.
433 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
434 MachineBasicBlock *TBB = 0, *FBB = 0;
435 SmallVector<MachineOperand, 4> Cond;
436 if (TII->AnalyzeBranch(*A, TBB, FBB, Cond))
437 return NULL;
438
439 ++NumSplits;
440
441 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
442 MF->push_back(NMBB);
443 DEBUG(errs() << "PHIElimination splitting critical edge:"
444 " BB#" << A->getNumber()
445 << " -- BB#" << NMBB->getNumber()
446 << " -- BB#" << B->getNumber() << '\n');
447
448 A->ReplaceUsesOfBlockWith(B, NMBB);
449 // If A may fall through to B, we may have to insert a branch.
450 if (A->isLayoutSuccessor(B))
451 A->updateTerminator();
452
453 // Insert unconditional "jump B" instruction in NMBB.
454 NMBB->addSuccessor(B);
455 Cond.clear();
456 MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond);
457
458 // Fix PHI nodes in B so they refer to NMBB instead of A
459 for (MachineBasicBlock::iterator i = B->begin(), e = B->end();
460 i != e && i->getOpcode() == TargetInstrInfo::PHI; ++i)
461 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
462 if (i->getOperand(ni+1).getMBB() == A)
463 i->getOperand(ni+1).setMBB(NMBB);
464
465 if (LiveVariables *LV=getAnalysisIfAvailable<LiveVariables>())
466 LV->addNewBlock(NMBB, A);
467
468 if (MachineDominatorTree *MDT=getAnalysisIfAvailable<MachineDominatorTree>())
469 MDT->addNewBlock(NMBB, A);
470
471 return NMBB;
472}
|