1@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2@c 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
3@c This is part of the GCC manual.
4@c For copying conditions, see the file gcc.texi.
5
6@ignore
7@c man begin INCLUDE
8@include gcc-vers.texi
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508
509@emph{i386 and x86-64 Options}
510@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol
511-mfpmath=@var{unit} @gol
512-masm=@var{dialect} -mno-fancy-math-387 @gol
513-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
514-mno-wide-multiply -mrtd -malign-double @gol
515-mpreferred-stack-boundary=@var{num} @gol
516-mmmx -msse -msse2 -msse3 -mssse3 -m3dnow @gol
517-mthreads -mno-align-stringops -minline-all-stringops @gol
518-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
519-m96bit-long-double -mregparm=@var{num} -msseregparm @gol
520-mstackrealign @gol
521-momit-leaf-frame-pointer -mno-red-zone -mno-tls-direct-seg-refs @gol
522-mcmodel=@var{code-model} @gol
523-m32 -m64 -mlarge-data-threshold=@var{num}}
524
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9056@item athlon-4, athlon-xp, athlon-mp
9057Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and full SSE
9058instruction set support.
9059@item k8, opteron, athlon64, athlon-fx
9060AMD K8 core based CPUs with x86-64 instruction set support. (This supersets
9061MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
9062@item k8-sse3, opteron-sse3, athlon64-sse3
9063Improved versions of k8, opteron and athlon64 with SSE3 instruction set support.
9064@item winchip-c6
9065IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
9066set support.
9067@item winchip2
9068IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3dNOW!
9069instruction set support.
9070@item c3
9071Via C3 CPU with MMX and 3dNOW! instruction set support. (No scheduling is
--- 278 unchanged lines hidden (view full) ---
9350@item -msse
9351@itemx -mno-sse
9352@item -msse2
9353@itemx -mno-sse2
9354@item -msse3
9355@itemx -mno-sse3
9356@item -mssse3
9357@itemx -mno-ssse3
9358@item -m3dnow
9359@itemx -mno-3dnow
9360@opindex mmmx
9361@opindex mno-mmx
9362@opindex msse
9363@opindex mno-sse
9364@opindex m3dnow
9365@opindex mno-3dnow
9366These switches enable or disable the use of instructions in the MMX,
9367SSE, SSE2, SSE3, SSSE3 or 3DNow! extended instruction sets.
9368These extensions are also available as built-in functions: see
9369@ref{X86 Built-in Functions}, for details of the functions enabled and
9370disabled by these switches.
9371
9372To have SSE/SSE2 instructions generated automatically from floating-point
9373code (as opposed to 387 instructions), see @option{-mfpmath=sse}.
9374
9375These options will enable GCC to use these extended instructions in
--- 4466 unchanged lines hidden ---
2@c 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
3@c This is part of the GCC manual.
4@c For copying conditions, see the file gcc.texi.
5
6@ignore
7@c man begin INCLUDE
8@include gcc-vers.texi
--- 499 unchanged lines hidden (view full) ---
508
509@emph{i386 and x86-64 Options}
510@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol
511-mfpmath=@var{unit} @gol
512-masm=@var{dialect} -mno-fancy-math-387 @gol
513-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
514-mno-wide-multiply -mrtd -malign-double @gol
515-mpreferred-stack-boundary=@var{num} @gol
516-mmmx -msse -msse2 -msse3 -mssse3 -m3dnow @gol
517-mthreads -mno-align-stringops -minline-all-stringops @gol
518-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
519-m96bit-long-double -mregparm=@var{num} -msseregparm @gol
520-mstackrealign @gol
521-momit-leaf-frame-pointer -mno-red-zone -mno-tls-direct-seg-refs @gol
522-mcmodel=@var{code-model} @gol
523-m32 -m64 -mlarge-data-threshold=@var{num}}
524
--- 8531 unchanged lines hidden (view full) ---
9056@item athlon-4, athlon-xp, athlon-mp
9057Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and full SSE
9058instruction set support.
9059@item k8, opteron, athlon64, athlon-fx
9060AMD K8 core based CPUs with x86-64 instruction set support. (This supersets
9061MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
9062@item k8-sse3, opteron-sse3, athlon64-sse3
9063Improved versions of k8, opteron and athlon64 with SSE3 instruction set support.
9064@item winchip-c6
9065IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
9066set support.
9067@item winchip2
9068IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3dNOW!
9069instruction set support.
9070@item c3
9071Via C3 CPU with MMX and 3dNOW! instruction set support. (No scheduling is
--- 278 unchanged lines hidden (view full) ---
9350@item -msse
9351@itemx -mno-sse
9352@item -msse2
9353@itemx -mno-sse2
9354@item -msse3
9355@itemx -mno-sse3
9356@item -mssse3
9357@itemx -mno-ssse3
9358@item -m3dnow
9359@itemx -mno-3dnow
9360@opindex mmmx
9361@opindex mno-mmx
9362@opindex msse
9363@opindex mno-sse
9364@opindex m3dnow
9365@opindex mno-3dnow
9366These switches enable or disable the use of instructions in the MMX,
9367SSE, SSE2, SSE3, SSSE3 or 3DNow! extended instruction sets.
9368These extensions are also available as built-in functions: see
9369@ref{X86 Built-in Functions}, for details of the functions enabled and
9370disabled by these switches.
9371
9372To have SSE/SSE2 instructions generated automatically from floating-point
9373code (as opposed to 387 instructions), see @option{-mfpmath=sse}.
9374
9375These options will enable GCC to use these extended instructions in
--- 4466 unchanged lines hidden ---