1;; GCC machine description for IA-32 and x86-64. 2;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3;; 2001, 2002, 2003, 2004, 2005, 2006 4;; Free Software Foundation, Inc. 5;; Mostly by William Schelter. 6;; x86_64 support added by Jan Hubicka 7;; 8;; This file is part of GCC. --- 139 unchanged lines hidden (view full) --- 148 (UNSPEC_SP_TEST 101) 149 (UNSPEC_SP_TLS_SET 102) 150 (UNSPEC_SP_TLS_TEST 103) 151 152 ; SSSE3 153 (UNSPEC_PSHUFB 120) 154 (UNSPEC_PSIGN 121) 155 (UNSPEC_PALIGNR 122) |
156 157 ; For SSE4A support 158 (UNSPEC_EXTRQI 130) 159 (UNSPEC_EXTRQ 131) 160 (UNSPEC_INSERTQI 132) 161 (UNSPEC_INSERTQ 133) |
162 ]) 163 164(define_constants 165 [(UNSPECV_BLOCKAGE 0) 166 (UNSPECV_STACK_PROBE 1) 167 (UNSPECV_EMMS 2) 168 (UNSPECV_LDMXCSR 3) 169 (UNSPECV_STMXCSR 4) --- 23 unchanged lines hidden (view full) --- 193;; In C guard expressions, put expressions which may be compile-time 194;; constants first. This allows for better optimization. For 195;; example, write "TARGET_64BIT && reload_completed", not 196;; "reload_completed && TARGET_64BIT". 197 198 199;; Processor type. This attribute must exactly match the processor_type 200;; enumeration in i386.h. |
201(define_attr "cpu" "i386,i486,pentium,pentiumpro,geode,k6,athlon,pentium4,k8, 202 nocona,core2,generic32,generic64,amdfam10" |
203 (const (symbol_ref "ix86_tune"))) 204 205;; A basic instruction type. Refinements due to arguments to be 206;; provided in other attributes. 207(define_attr "type" 208 "other,multi, 209 alu,alu1,negnot,imov,imovx,lea, 210 incdec,ishift,ishift1,rotate,rotate1,imul,idiv, 211 icmp,test,ibr,setcc,icmov, 212 push,pop,call,callv,leave, |
213 str,bitmanip,cld, |
214 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint, 215 sselog,sselog1,sseiadd,sseishft,sseimul, |
216 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,sseins, |
217 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft" 218 (const_string "other")) 219 220;; Main data type used by the insn 221(define_attr "mode" 222 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF,V1DF" 223 (const_string "unknown")) 224 225;; The CPU unit operations uses. 226(define_attr "unit" "integer,i387,sse,mmx,unknown" 227 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint") 228 (const_string "i387") 229 (eq_attr "type" "sselog,sselog1,sseiadd,sseishft,sseimul, |
230 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,sseins") |
231 (const_string "sse") 232 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft") 233 (const_string "mmx") 234 (eq_attr "type" "other") 235 (const_string "unknown")] 236 (const_string "integer"))) 237 238;; The (bounding maximum) length of an instruction immediate. 239(define_attr "length_immediate" "" |
240 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave, 241 bitmanip") |
242 (const_int 0) 243 (eq_attr "unit" "i387,sse,mmx") 244 (const_int 0) 245 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1, 246 imul,icmp,push,pop") 247 (symbol_ref "ix86_attr_length_immediate_default(insn,1)") 248 (eq_attr "type" "imov,test") 249 (symbol_ref "ix86_attr_length_immediate_default(insn,0)") --- 37 unchanged lines hidden (view full) --- 287(define_attr "prefix_rep" "" 288 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF")) 289 (const_int 1) 290 (const_int 0))) 291 292;; Set when 0f opcode prefix is used. 293(define_attr "prefix_0f" "" 294 (if_then_else |
295 (ior (eq_attr "type" "imovx,setcc,icmov,bitmanip") |
296 (eq_attr "unit" "sse,mmx")) 297 (const_int 1) 298 (const_int 0))) 299 300;; Set when REX opcode prefix is used. 301(define_attr "prefix_rex" "" 302 (cond [(and (eq_attr "mode" "DI") 303 (eq_attr "type" "!push,pop,call,callv,leave,ibr")) --- 112 unchanged lines hidden (view full) --- 416 (match_operand 1 "memory_operand" "")) 417 (const_string "both") 418 (match_operand 0 "memory_operand" "") 419 (const_string "store") 420 (match_operand 1 "memory_operand" "") 421 (const_string "load") 422 (and (eq_attr "type" 423 "!alu1,negnot,ishift1, |
424 imov,imovx,icmp,test,bitmanip, |
425 fmov,fcmp,fsgn, 426 sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,sselog1, 427 mmx,mmxmov,mmxcmp,mmxcvt") 428 (match_operand 2 "memory_operand" "")) 429 (const_string "load") 430 (and (eq_attr "type" "icmov") 431 (match_operand 3 "memory_operand" "")) 432 (const_string "load") --- 538 unchanged lines hidden (view full) --- 971 972(define_insn "x86_sahf_1" 973 [(set (reg:CC FLAGS_REG) 974 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))] 975 "!TARGET_64BIT" 976 "sahf" 977 [(set_attr "length" "1") 978 (set_attr "athlon_decode" "vector") |
979 (set_attr "amdfam10_decode" "direct") |
980 (set_attr "mode" "SI")]) 981 982;; Pentium Pro can do steps 1 through 3 in one go. |
983;; comi*, ucomi*, fcomi*, ficomi*,fucomi* (i387 instructions set condition codes) |
984(define_insn "*cmpfp_i_mixed" 985 [(set (reg:CCFP FLAGS_REG) 986 (compare:CCFP (match_operand 0 "register_operand" "f,x") 987 (match_operand 1 "nonimmediate_operand" "f,xm")))] 988 "TARGET_MIX_SSE_I387 989 && SSE_FLOAT_MODE_P (GET_MODE (operands[0])) 990 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 991 "* return output_fp_compare (insn, operands, 1, 0);" 992 [(set_attr "type" "fcmp,ssecomi") 993 (set (attr "mode") 994 (if_then_else (match_operand:SF 1 "" "") 995 (const_string "SF") 996 (const_string "DF"))) |
997 (set_attr "athlon_decode" "vector") 998 (set_attr "amdfam10_decode" "direct")]) |
999 1000(define_insn "*cmpfp_i_sse" 1001 [(set (reg:CCFP FLAGS_REG) 1002 (compare:CCFP (match_operand 0 "register_operand" "x") 1003 (match_operand 1 "nonimmediate_operand" "xm")))] 1004 "TARGET_SSE_MATH 1005 && SSE_FLOAT_MODE_P (GET_MODE (operands[0])) 1006 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 1007 "* return output_fp_compare (insn, operands, 1, 0);" 1008 [(set_attr "type" "ssecomi") 1009 (set (attr "mode") 1010 (if_then_else (match_operand:SF 1 "" "") 1011 (const_string "SF") 1012 (const_string "DF"))) |
1013 (set_attr "athlon_decode" "vector") 1014 (set_attr "amdfam10_decode" "direct")]) |
1015 1016(define_insn "*cmpfp_i_i387" 1017 [(set (reg:CCFP FLAGS_REG) 1018 (compare:CCFP (match_operand 0 "register_operand" "f") 1019 (match_operand 1 "register_operand" "f")))] 1020 "TARGET_80387 && TARGET_CMOVE 1021 && (!TARGET_SSE_MATH || !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))) 1022 && FLOAT_MODE_P (GET_MODE (operands[0])) 1023 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 1024 "* return output_fp_compare (insn, operands, 1, 0);" 1025 [(set_attr "type" "fcmp") 1026 (set (attr "mode") 1027 (cond [(match_operand:SF 1 "" "") 1028 (const_string "SF") 1029 (match_operand:DF 1 "" "") 1030 (const_string "DF") 1031 ] 1032 (const_string "XF"))) |
1033 (set_attr "athlon_decode" "vector") 1034 (set_attr "amdfam10_decode" "direct")]) |
1035 1036(define_insn "*cmpfp_iu_mixed" 1037 [(set (reg:CCFPU FLAGS_REG) 1038 (compare:CCFPU (match_operand 0 "register_operand" "f,x") 1039 (match_operand 1 "nonimmediate_operand" "f,xm")))] 1040 "TARGET_MIX_SSE_I387 1041 && SSE_FLOAT_MODE_P (GET_MODE (operands[0])) 1042 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 1043 "* return output_fp_compare (insn, operands, 1, 1);" 1044 [(set_attr "type" "fcmp,ssecomi") 1045 (set (attr "mode") 1046 (if_then_else (match_operand:SF 1 "" "") 1047 (const_string "SF") 1048 (const_string "DF"))) |
1049 (set_attr "athlon_decode" "vector") 1050 (set_attr "amdfam10_decode" "direct")]) |
1051 1052(define_insn "*cmpfp_iu_sse" 1053 [(set (reg:CCFPU FLAGS_REG) 1054 (compare:CCFPU (match_operand 0 "register_operand" "x") 1055 (match_operand 1 "nonimmediate_operand" "xm")))] 1056 "TARGET_SSE_MATH 1057 && SSE_FLOAT_MODE_P (GET_MODE (operands[0])) 1058 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 1059 "* return output_fp_compare (insn, operands, 1, 1);" 1060 [(set_attr "type" "ssecomi") 1061 (set (attr "mode") 1062 (if_then_else (match_operand:SF 1 "" "") 1063 (const_string "SF") 1064 (const_string "DF"))) |
1065 (set_attr "athlon_decode" "vector") 1066 (set_attr "amdfam10_decode" "direct")]) |
1067 1068(define_insn "*cmpfp_iu_387" 1069 [(set (reg:CCFPU FLAGS_REG) 1070 (compare:CCFPU (match_operand 0 "register_operand" "f") 1071 (match_operand 1 "register_operand" "f")))] 1072 "TARGET_80387 && TARGET_CMOVE 1073 && (!TARGET_SSE_MATH || !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))) 1074 && FLOAT_MODE_P (GET_MODE (operands[0])) 1075 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 1076 "* return output_fp_compare (insn, operands, 1, 1);" 1077 [(set_attr "type" "fcmp") 1078 (set (attr "mode") 1079 (cond [(match_operand:SF 1 "" "") 1080 (const_string "SF") 1081 (match_operand:DF 1 "" "") 1082 (const_string "DF") 1083 ] 1084 (const_string "XF"))) |
1085 (set_attr "athlon_decode" "vector") 1086 (set_attr "amdfam10_decode" "direct")]) |
1087 1088;; Move instructions. 1089 1090;; General case of fullword move. 1091 1092(define_expand "movsi" 1093 [(set (match_operand:SI 0 "nonimmediate_operand" "") 1094 (match_operand:SI 1 "general_operand" ""))] --- 189 unchanged lines hidden (view full) --- 1284 (match_operand:SI 1 "register_operand" "+r")) 1285 (set (match_dup 1) 1286 (match_dup 0))] 1287 "" 1288 "xchg{l}\t%1, %0" 1289 [(set_attr "type" "imov") 1290 (set_attr "mode" "SI") 1291 (set_attr "pent_pair" "np") |
1292 (set_attr "athlon_decode" "vector") 1293 (set_attr "amdfam10_decode" "double")]) |
1294 1295(define_expand "movhi" 1296 [(set (match_operand:HI 0 "nonimmediate_operand" "") 1297 (match_operand:HI 1 "general_operand" ""))] 1298 "" 1299 "ix86_expand_move (HImode, operands); DONE;") 1300 1301(define_insn "*pushhi2" --- 100 unchanged lines hidden (view full) --- 1402 (match_operand:HI 1 "register_operand" "+r")) 1403 (set (match_dup 1) 1404 (match_dup 0))] 1405 "!TARGET_PARTIAL_REG_STALL || optimize_size" 1406 "xchg{l}\t%k1, %k0" 1407 [(set_attr "type" "imov") 1408 (set_attr "mode" "SI") 1409 (set_attr "pent_pair" "np") |
1410 (set_attr "athlon_decode" "vector") 1411 (set_attr "amdfam10_decode" "double")]) |
1412 |
1413;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10 |
1414(define_insn "*swaphi_2" 1415 [(set (match_operand:HI 0 "register_operand" "+r") 1416 (match_operand:HI 1 "register_operand" "+r")) 1417 (set (match_dup 1) 1418 (match_dup 0))] 1419 "TARGET_PARTIAL_REG_STALL" 1420 "xchg{w}\t%1, %0" 1421 [(set_attr "type" "imov") --- 156 unchanged lines hidden (view full) --- 1578 (match_operand:QI 1 "register_operand" "+r")) 1579 (set (match_dup 1) 1580 (match_dup 0))] 1581 "!TARGET_PARTIAL_REG_STALL || optimize_size" 1582 "xchg{l}\t%k1, %k0" 1583 [(set_attr "type" "imov") 1584 (set_attr "mode" "SI") 1585 (set_attr "pent_pair" "np") |
1586 (set_attr "athlon_decode" "vector") 1587 (set_attr "amdfam10_decode" "vector")]) |
1588 |
1589;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10 |
1590(define_insn "*swapqi_2" 1591 [(set (match_operand:QI 0 "register_operand" "+q") 1592 (match_operand:QI 1 "register_operand" "+q")) 1593 (set (match_dup 1) 1594 (match_dup 0))] 1595 "TARGET_PARTIAL_REG_STALL" 1596 "xchg{b}\t%1, %0" 1597 [(set_attr "type" "imov") --- 537 unchanged lines hidden (view full) --- 2135 (match_operand:DI 1 "register_operand" "+r")) 2136 (set (match_dup 1) 2137 (match_dup 0))] 2138 "TARGET_64BIT" 2139 "xchg{q}\t%1, %0" 2140 [(set_attr "type" "imov") 2141 (set_attr "mode" "DI") 2142 (set_attr "pent_pair" "np") |
2143 (set_attr "athlon_decode" "vector") 2144 (set_attr "amdfam10_decode" "double")]) |
2145 2146(define_expand "movti" 2147 [(set (match_operand:TI 0 "nonimmediate_operand" "") 2148 (match_operand:TI 1 "nonimmediate_operand" ""))] 2149 "TARGET_SSE || TARGET_64BIT" 2150{ 2151 if (TARGET_64BIT) 2152 ix86_expand_move (TImode, operands); --- 2013 unchanged lines hidden (view full) --- 4166;; When SSE is available, it is always faster to use it! 4167(define_insn "fix_truncsfdi_sse" 4168 [(set (match_operand:DI 0 "register_operand" "=r,r") 4169 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))] 4170 "TARGET_64BIT && TARGET_SSE && (!TARGET_FISTTP || TARGET_SSE_MATH)" 4171 "cvttss2si{q}\t{%1, %0|%0, %1}" 4172 [(set_attr "type" "sseicvt") 4173 (set_attr "mode" "SF") |
4174 (set_attr "athlon_decode" "double,vector") 4175 (set_attr "amdfam10_decode" "double,double")]) |
4176 4177(define_insn "fix_truncdfdi_sse" 4178 [(set (match_operand:DI 0 "register_operand" "=r,r") 4179 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))] 4180 "TARGET_64BIT && TARGET_SSE2 && (!TARGET_FISTTP || TARGET_SSE_MATH)" 4181 "cvttsd2si{q}\t{%1, %0|%0, %1}" 4182 [(set_attr "type" "sseicvt") 4183 (set_attr "mode" "DF") |
4184 (set_attr "athlon_decode" "double,vector") 4185 (set_attr "amdfam10_decode" "double,double")]) |
4186 4187(define_insn "fix_truncsfsi_sse" 4188 [(set (match_operand:SI 0 "register_operand" "=r,r") 4189 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))] 4190 "TARGET_SSE && (!TARGET_FISTTP || TARGET_SSE_MATH)" 4191 "cvttss2si\t{%1, %0|%0, %1}" 4192 [(set_attr "type" "sseicvt") 4193 (set_attr "mode" "DF") |
4194 (set_attr "athlon_decode" "double,vector") 4195 (set_attr "amdfam10_decode" "double,double")]) |
4196 4197(define_insn "fix_truncdfsi_sse" 4198 [(set (match_operand:SI 0 "register_operand" "=r,r") 4199 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))] 4200 "TARGET_SSE2 && (!TARGET_FISTTP || TARGET_SSE_MATH)" 4201 "cvttsd2si\t{%1, %0|%0, %1}" 4202 [(set_attr "type" "sseicvt") 4203 (set_attr "mode" "DF") |
4204 (set_attr "athlon_decode" "double,vector") 4205 (set_attr "amdfam10_decode" "double,double")]) |
4206 4207;; Avoid vector decoded forms of the instruction. 4208(define_peephole2 4209 [(match_scratch:DF 2 "Y") 4210 (set (match_operand:SSEMODEI24 0 "register_operand" "") 4211 (fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))] 4212 "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size" 4213 [(set (match_dup 2) (match_dup 1)) --- 244 unchanged lines hidden (view full) --- 4458(define_insn "x86_fldcw_1" 4459 [(set (reg:HI FPSR_REG) 4460 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))] 4461 "TARGET_80387" 4462 "fldcw\t%0" 4463 [(set_attr "length" "2") 4464 (set_attr "mode" "HI") 4465 (set_attr "unit" "i387") |
4466 (set_attr "athlon_decode" "vector") 4467 (set_attr "amdfam10_decode" "vector")]) |
4468 4469;; Conversion between fixed point and floating point. 4470 4471;; Even though we only accept memory inputs, the backend _really_ 4472;; wants to be able to do this between registers. 4473 4474(define_expand "floathisf2" 4475 [(set (match_operand:SF 0 "register_operand" "") --- 34 unchanged lines hidden (view full) --- 4510 fild%z1\t%1 4511 # 4512 cvtsi2ss\t{%1, %0|%0, %1} 4513 cvtsi2ss\t{%1, %0|%0, %1}" 4514 [(set_attr "type" "fmov,multi,sseicvt,sseicvt") 4515 (set_attr "mode" "SF") 4516 (set_attr "unit" "*,i387,*,*") 4517 (set_attr "athlon_decode" "*,*,vector,double") |
4518 (set_attr "amdfam10_decode" "*,*,vector,double") |
4519 (set_attr "fp_int_src" "true")]) 4520 4521(define_insn "*floatsisf2_sse" 4522 [(set (match_operand:SF 0 "register_operand" "=x,x") 4523 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))] 4524 "TARGET_SSE_MATH" 4525 "cvtsi2ss\t{%1, %0|%0, %1}" 4526 [(set_attr "type" "sseicvt") 4527 (set_attr "mode" "SF") 4528 (set_attr "athlon_decode" "vector,double") |
4529 (set_attr "amdfam10_decode" "vector,double") |
4530 (set_attr "fp_int_src" "true")]) 4531 4532(define_insn "*floatsisf2_i387" 4533 [(set (match_operand:SF 0 "register_operand" "=f,f") 4534 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))] 4535 "TARGET_80387" 4536 "@ 4537 fild%z1\t%1 --- 17 unchanged lines hidden (view full) --- 4555 fild%z1\t%1 4556 # 4557 cvtsi2ss{q}\t{%1, %0|%0, %1} 4558 cvtsi2ss{q}\t{%1, %0|%0, %1}" 4559 [(set_attr "type" "fmov,multi,sseicvt,sseicvt") 4560 (set_attr "mode" "SF") 4561 (set_attr "unit" "*,i387,*,*") 4562 (set_attr "athlon_decode" "*,*,vector,double") |
4563 (set_attr "amdfam10_decode" "*,*,vector,double") |
4564 (set_attr "fp_int_src" "true")]) 4565 4566(define_insn "*floatdisf2_sse" 4567 [(set (match_operand:SF 0 "register_operand" "=x,x") 4568 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))] 4569 "TARGET_64BIT && TARGET_SSE_MATH" 4570 "cvtsi2ss{q}\t{%1, %0|%0, %1}" 4571 [(set_attr "type" "sseicvt") 4572 (set_attr "mode" "SF") 4573 (set_attr "athlon_decode" "vector,double") |
4574 (set_attr "amdfam10_decode" "vector,double") |
4575 (set_attr "fp_int_src" "true")]) 4576 4577(define_insn "*floatdisf2_i387" 4578 [(set (match_operand:SF 0 "register_operand" "=f,f") 4579 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))] 4580 "TARGET_80387" 4581 "@ 4582 fild%z1\t%1 --- 42 unchanged lines hidden (view full) --- 4625 fild%z1\t%1 4626 # 4627 cvtsi2sd\t{%1, %0|%0, %1} 4628 cvtsi2sd\t{%1, %0|%0, %1}" 4629 [(set_attr "type" "fmov,multi,sseicvt,sseicvt") 4630 (set_attr "mode" "DF") 4631 (set_attr "unit" "*,i387,*,*") 4632 (set_attr "athlon_decode" "*,*,double,direct") |
4633 (set_attr "amdfam10_decode" "*,*,vector,double") |
4634 (set_attr "fp_int_src" "true")]) 4635 4636(define_insn "*floatsidf2_sse" 4637 [(set (match_operand:DF 0 "register_operand" "=Y,Y") 4638 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))] 4639 "TARGET_SSE2 && TARGET_SSE_MATH" 4640 "cvtsi2sd\t{%1, %0|%0, %1}" 4641 [(set_attr "type" "sseicvt") 4642 (set_attr "mode" "DF") 4643 (set_attr "athlon_decode" "double,direct") |
4644 (set_attr "amdfam10_decode" "vector,double") |
4645 (set_attr "fp_int_src" "true")]) 4646 4647(define_insn "*floatsidf2_i387" 4648 [(set (match_operand:DF 0 "register_operand" "=f,f") 4649 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))] 4650 "TARGET_80387" 4651 "@ 4652 fild%z1\t%1 --- 17 unchanged lines hidden (view full) --- 4670 fild%z1\t%1 4671 # 4672 cvtsi2sd{q}\t{%1, %0|%0, %1} 4673 cvtsi2sd{q}\t{%1, %0|%0, %1}" 4674 [(set_attr "type" "fmov,multi,sseicvt,sseicvt") 4675 (set_attr "mode" "DF") 4676 (set_attr "unit" "*,i387,*,*") 4677 (set_attr "athlon_decode" "*,*,double,direct") |
4678 (set_attr "amdfam10_decode" "*,*,vector,double") |
4679 (set_attr "fp_int_src" "true")]) 4680 4681(define_insn "*floatdidf2_sse" 4682 [(set (match_operand:DF 0 "register_operand" "=Y,Y") 4683 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))] 4684 "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH" 4685 "cvtsi2sd{q}\t{%1, %0|%0, %1}" 4686 [(set_attr "type" "sseicvt") 4687 (set_attr "mode" "DF") 4688 (set_attr "athlon_decode" "double,direct") |
4689 (set_attr "amdfam10_decode" "vector,double") |
4690 (set_attr "fp_int_src" "true")]) 4691 4692(define_insn "*floatdidf2_i387" 4693 [(set (match_operand:DF 0 "register_operand" "=f,f") 4694 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))] 4695 "TARGET_80387" 4696 "@ 4697 fild%z1\t%1 --- 2191 unchanged lines hidden (view full) --- 6889(define_expand "muldi3" 6890 [(parallel [(set (match_operand:DI 0 "register_operand" "") 6891 (mult:DI (match_operand:DI 1 "register_operand" "") 6892 (match_operand:DI 2 "x86_64_general_operand" ""))) 6893 (clobber (reg:CC FLAGS_REG))])] 6894 "TARGET_64BIT" 6895 "") 6896 |
6897;; On AMDFAM10 6898;; IMUL reg64, reg64, imm8 Direct 6899;; IMUL reg64, mem64, imm8 VectorPath 6900;; IMUL reg64, reg64, imm32 Direct 6901;; IMUL reg64, mem64, imm32 VectorPath 6902;; IMUL reg64, reg64 Direct 6903;; IMUL reg64, mem64 Direct 6904 |
6905(define_insn "*muldi3_1_rex64" 6906 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 6907 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0") 6908 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr"))) 6909 (clobber (reg:CC FLAGS_REG))] 6910 "TARGET_64BIT 6911 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 6912 "@ --- 6 unchanged lines hidden (view full) --- 6919 (cond [(eq_attr "cpu" "athlon") 6920 (const_string "vector") 6921 (eq_attr "alternative" "1") 6922 (const_string "vector") 6923 (and (eq_attr "alternative" "2") 6924 (match_operand 1 "memory_operand" "")) 6925 (const_string "vector")] 6926 (const_string "direct"))) |
6927 (set (attr "amdfam10_decode") 6928 (cond [(and (eq_attr "alternative" "0,1") 6929 (match_operand 1 "memory_operand" "")) 6930 (const_string "vector")] 6931 (const_string "direct"))) |
6932 (set_attr "mode" "DI")]) 6933 6934(define_expand "mulsi3" 6935 [(parallel [(set (match_operand:SI 0 "register_operand" "") 6936 (mult:SI (match_operand:SI 1 "register_operand" "") 6937 (match_operand:SI 2 "general_operand" ""))) 6938 (clobber (reg:CC FLAGS_REG))])] 6939 "" 6940 "") 6941 |
6942;; On AMDFAM10 6943;; IMUL reg32, reg32, imm8 Direct 6944;; IMUL reg32, mem32, imm8 VectorPath 6945;; IMUL reg32, reg32, imm32 Direct 6946;; IMUL reg32, mem32, imm32 VectorPath 6947;; IMUL reg32, reg32 Direct 6948;; IMUL reg32, mem32 Direct 6949 |
6950(define_insn "*mulsi3_1" 6951 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 6952 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0") 6953 (match_operand:SI 2 "general_operand" "K,i,mr"))) 6954 (clobber (reg:CC FLAGS_REG))] 6955 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" 6956 "@ 6957 imul{l}\t{%2, %1, %0|%0, %1, %2} --- 5 unchanged lines hidden (view full) --- 6963 (cond [(eq_attr "cpu" "athlon") 6964 (const_string "vector") 6965 (eq_attr "alternative" "1") 6966 (const_string "vector") 6967 (and (eq_attr "alternative" "2") 6968 (match_operand 1 "memory_operand" "")) 6969 (const_string "vector")] 6970 (const_string "direct"))) |
6971 (set (attr "amdfam10_decode") 6972 (cond [(and (eq_attr "alternative" "0,1") 6973 (match_operand 1 "memory_operand" "")) 6974 (const_string "vector")] 6975 (const_string "direct"))) |
6976 (set_attr "mode" "SI")]) 6977 6978(define_insn "*mulsi3_1_zext" 6979 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 6980 (zero_extend:DI 6981 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0") 6982 (match_operand:SI 2 "general_operand" "K,i,mr")))) 6983 (clobber (reg:CC FLAGS_REG))] --- 9 unchanged lines hidden (view full) --- 6993 (cond [(eq_attr "cpu" "athlon") 6994 (const_string "vector") 6995 (eq_attr "alternative" "1") 6996 (const_string "vector") 6997 (and (eq_attr "alternative" "2") 6998 (match_operand 1 "memory_operand" "")) 6999 (const_string "vector")] 7000 (const_string "direct"))) |
7001 (set (attr "amdfam10_decode") 7002 (cond [(and (eq_attr "alternative" "0,1") 7003 (match_operand 1 "memory_operand" "")) 7004 (const_string "vector")] 7005 (const_string "direct"))) |
7006 (set_attr "mode" "SI")]) 7007 7008(define_expand "mulhi3" 7009 [(parallel [(set (match_operand:HI 0 "register_operand" "") 7010 (mult:HI (match_operand:HI 1 "register_operand" "") 7011 (match_operand:HI 2 "general_operand" ""))) 7012 (clobber (reg:CC FLAGS_REG))])] 7013 "TARGET_HIMODE_MATH" 7014 "") 7015 |
7016;; On AMDFAM10 7017;; IMUL reg16, reg16, imm8 VectorPath 7018;; IMUL reg16, mem16, imm8 VectorPath 7019;; IMUL reg16, reg16, imm16 VectorPath 7020;; IMUL reg16, mem16, imm16 VectorPath 7021;; IMUL reg16, reg16 Direct 7022;; IMUL reg16, mem16 Direct |
7023(define_insn "*mulhi3_1" 7024 [(set (match_operand:HI 0 "register_operand" "=r,r,r") 7025 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0") 7026 (match_operand:HI 2 "general_operand" "K,i,mr"))) 7027 (clobber (reg:CC FLAGS_REG))] 7028 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" 7029 "@ 7030 imul{w}\t{%2, %1, %0|%0, %1, %2} 7031 imul{w}\t{%2, %1, %0|%0, %1, %2} 7032 imul{w}\t{%2, %0|%0, %2}" 7033 [(set_attr "type" "imul") 7034 (set_attr "prefix_0f" "0,0,1") 7035 (set (attr "athlon_decode") 7036 (cond [(eq_attr "cpu" "athlon") 7037 (const_string "vector") 7038 (eq_attr "alternative" "1,2") 7039 (const_string "vector")] 7040 (const_string "direct"))) |
7041 (set (attr "amdfam10_decode") 7042 (cond [(eq_attr "alternative" "0,1") 7043 (const_string "vector")] 7044 (const_string "direct"))) |
7045 (set_attr "mode" "HI")]) 7046 7047(define_expand "mulqi3" 7048 [(parallel [(set (match_operand:QI 0 "register_operand" "") 7049 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "") 7050 (match_operand:QI 2 "register_operand" ""))) 7051 (clobber (reg:CC FLAGS_REG))])] 7052 "TARGET_QIMODE_MATH" 7053 "") 7054 |
7055;;On AMDFAM10 7056;; MUL reg8 Direct 7057;; MUL mem8 Direct 7058 |
7059(define_insn "*mulqi3_1" 7060 [(set (match_operand:QI 0 "register_operand" "=a") 7061 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0") 7062 (match_operand:QI 2 "nonimmediate_operand" "qm"))) 7063 (clobber (reg:CC FLAGS_REG))] 7064 "TARGET_QIMODE_MATH 7065 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 7066 "mul{b}\t%2" 7067 [(set_attr "type" "imul") 7068 (set_attr "length_immediate" "0") 7069 (set (attr "athlon_decode") 7070 (if_then_else (eq_attr "cpu" "athlon") 7071 (const_string "vector") 7072 (const_string "direct"))) |
7073 (set_attr "amdfam10_decode" "direct") |
7074 (set_attr "mode" "QI")]) 7075 7076(define_expand "umulqihi3" 7077 [(parallel [(set (match_operand:HI 0 "register_operand" "") 7078 (mult:HI (zero_extend:HI 7079 (match_operand:QI 1 "nonimmediate_operand" "")) 7080 (zero_extend:HI 7081 (match_operand:QI 2 "register_operand" "")))) --- 10 unchanged lines hidden (view full) --- 7092 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 7093 "mul{b}\t%2" 7094 [(set_attr "type" "imul") 7095 (set_attr "length_immediate" "0") 7096 (set (attr "athlon_decode") 7097 (if_then_else (eq_attr "cpu" "athlon") 7098 (const_string "vector") 7099 (const_string "direct"))) |
7100 (set_attr "amdfam10_decode" "direct") |
7101 (set_attr "mode" "QI")]) 7102 7103(define_expand "mulqihi3" 7104 [(parallel [(set (match_operand:HI 0 "register_operand" "") 7105 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")) 7106 (sign_extend:HI (match_operand:QI 2 "register_operand" "")))) 7107 (clobber (reg:CC FLAGS_REG))])] 7108 "TARGET_QIMODE_MATH" --- 8 unchanged lines hidden (view full) --- 7117 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 7118 "imul{b}\t%2" 7119 [(set_attr "type" "imul") 7120 (set_attr "length_immediate" "0") 7121 (set (attr "athlon_decode") 7122 (if_then_else (eq_attr "cpu" "athlon") 7123 (const_string "vector") 7124 (const_string "direct"))) |
7125 (set_attr "amdfam10_decode" "direct") |
7126 (set_attr "mode" "QI")]) 7127 7128(define_expand "umulditi3" 7129 [(parallel [(set (match_operand:TI 0 "register_operand" "") 7130 (mult:TI (zero_extend:TI 7131 (match_operand:DI 1 "nonimmediate_operand" "")) 7132 (zero_extend:TI 7133 (match_operand:DI 2 "register_operand" "")))) --- 10 unchanged lines hidden (view full) --- 7144 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 7145 "mul{q}\t%2" 7146 [(set_attr "type" "imul") 7147 (set_attr "length_immediate" "0") 7148 (set (attr "athlon_decode") 7149 (if_then_else (eq_attr "cpu" "athlon") 7150 (const_string "vector") 7151 (const_string "double"))) |
7152 (set_attr "amdfam10_decode" "double") |
7153 (set_attr "mode" "DI")]) 7154 7155;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers 7156(define_expand "umulsidi3" 7157 [(parallel [(set (match_operand:DI 0 "register_operand" "") 7158 (mult:DI (zero_extend:DI 7159 (match_operand:SI 1 "nonimmediate_operand" "")) 7160 (zero_extend:DI --- 11 unchanged lines hidden (view full) --- 7172 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 7173 "mul{l}\t%2" 7174 [(set_attr "type" "imul") 7175 (set_attr "length_immediate" "0") 7176 (set (attr "athlon_decode") 7177 (if_then_else (eq_attr "cpu" "athlon") 7178 (const_string "vector") 7179 (const_string "double"))) |
7180 (set_attr "amdfam10_decode" "double") |
7181 (set_attr "mode" "SI")]) 7182 7183(define_expand "mulditi3" 7184 [(parallel [(set (match_operand:TI 0 "register_operand" "") 7185 (mult:TI (sign_extend:TI 7186 (match_operand:DI 1 "nonimmediate_operand" "")) 7187 (sign_extend:TI 7188 (match_operand:DI 2 "register_operand" "")))) --- 10 unchanged lines hidden (view full) --- 7199 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 7200 "imul{q}\t%2" 7201 [(set_attr "type" "imul") 7202 (set_attr "length_immediate" "0") 7203 (set (attr "athlon_decode") 7204 (if_then_else (eq_attr "cpu" "athlon") 7205 (const_string "vector") 7206 (const_string "double"))) |
7207 (set_attr "amdfam10_decode" "double") |
7208 (set_attr "mode" "DI")]) 7209 7210(define_expand "mulsidi3" 7211 [(parallel [(set (match_operand:DI 0 "register_operand" "") 7212 (mult:DI (sign_extend:DI 7213 (match_operand:SI 1 "nonimmediate_operand" "")) 7214 (sign_extend:DI 7215 (match_operand:SI 2 "register_operand" "")))) --- 10 unchanged lines hidden (view full) --- 7226 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 7227 "imul{l}\t%2" 7228 [(set_attr "type" "imul") 7229 (set_attr "length_immediate" "0") 7230 (set (attr "athlon_decode") 7231 (if_then_else (eq_attr "cpu" "athlon") 7232 (const_string "vector") 7233 (const_string "double"))) |
7234 (set_attr "amdfam10_decode" "double") |
7235 (set_attr "mode" "SI")]) 7236 7237(define_expand "umuldi3_highpart" 7238 [(parallel [(set (match_operand:DI 0 "register_operand" "") 7239 (truncate:DI 7240 (lshiftrt:TI 7241 (mult:TI (zero_extend:TI 7242 (match_operand:DI 1 "nonimmediate_operand" "")) --- 20 unchanged lines hidden (view full) --- 7263 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 7264 "mul{q}\t%2" 7265 [(set_attr "type" "imul") 7266 (set_attr "length_immediate" "0") 7267 (set (attr "athlon_decode") 7268 (if_then_else (eq_attr "cpu" "athlon") 7269 (const_string "vector") 7270 (const_string "double"))) |
7271 (set_attr "amdfam10_decode" "double") |
7272 (set_attr "mode" "DI")]) 7273 7274(define_expand "umulsi3_highpart" 7275 [(parallel [(set (match_operand:SI 0 "register_operand" "") 7276 (truncate:SI 7277 (lshiftrt:DI 7278 (mult:DI (zero_extend:DI 7279 (match_operand:SI 1 "nonimmediate_operand" "")) --- 19 unchanged lines hidden (view full) --- 7299 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" 7300 "mul{l}\t%2" 7301 [(set_attr "type" "imul") 7302 (set_attr "length_immediate" "0") 7303 (set (attr "athlon_decode") 7304 (if_then_else (eq_attr "cpu" "athlon") 7305 (const_string "vector") 7306 (const_string "double"))) |
7307 (set_attr "amdfam10_decode" "double") |
7308 (set_attr "mode" "SI")]) 7309 7310(define_insn "*umulsi3_highpart_zext" 7311 [(set (match_operand:DI 0 "register_operand" "=d") 7312 (zero_extend:DI (truncate:SI 7313 (lshiftrt:DI 7314 (mult:DI (zero_extend:DI 7315 (match_operand:SI 1 "nonimmediate_operand" "%a")) --- 6 unchanged lines hidden (view full) --- 7322 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 7323 "mul{l}\t%2" 7324 [(set_attr "type" "imul") 7325 (set_attr "length_immediate" "0") 7326 (set (attr "athlon_decode") 7327 (if_then_else (eq_attr "cpu" "athlon") 7328 (const_string "vector") 7329 (const_string "double"))) |
7330 (set_attr "amdfam10_decode" "double") |
7331 (set_attr "mode" "SI")]) 7332 7333(define_expand "smuldi3_highpart" 7334 [(parallel [(set (match_operand:DI 0 "register_operand" "=d") 7335 (truncate:DI 7336 (lshiftrt:TI 7337 (mult:TI (sign_extend:TI 7338 (match_operand:DI 1 "nonimmediate_operand" "")) --- 19 unchanged lines hidden (view full) --- 7358 "TARGET_64BIT 7359 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 7360 "imul{q}\t%2" 7361 [(set_attr "type" "imul") 7362 (set (attr "athlon_decode") 7363 (if_then_else (eq_attr "cpu" "athlon") 7364 (const_string "vector") 7365 (const_string "double"))) |
7366 (set_attr "amdfam10_decode" "double") |
7367 (set_attr "mode" "DI")]) 7368 7369(define_expand "smulsi3_highpart" 7370 [(parallel [(set (match_operand:SI 0 "register_operand" "") 7371 (truncate:SI 7372 (lshiftrt:DI 7373 (mult:DI (sign_extend:DI 7374 (match_operand:SI 1 "nonimmediate_operand" "")) --- 18 unchanged lines hidden (view full) --- 7393 (clobber (reg:CC FLAGS_REG))] 7394 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" 7395 "imul{l}\t%2" 7396 [(set_attr "type" "imul") 7397 (set (attr "athlon_decode") 7398 (if_then_else (eq_attr "cpu" "athlon") 7399 (const_string "vector") 7400 (const_string "double"))) |
7401 (set_attr "amdfam10_decode" "double") |
7402 (set_attr "mode" "SI")]) 7403 7404(define_insn "*smulsi3_highpart_zext" 7405 [(set (match_operand:DI 0 "register_operand" "=d") 7406 (zero_extend:DI (truncate:SI 7407 (lshiftrt:DI 7408 (mult:DI (sign_extend:DI 7409 (match_operand:SI 1 "nonimmediate_operand" "%a")) --- 5 unchanged lines hidden (view full) --- 7415 "TARGET_64BIT 7416 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 7417 "imul{l}\t%2" 7418 [(set_attr "type" "imul") 7419 (set (attr "athlon_decode") 7420 (if_then_else (eq_attr "cpu" "athlon") 7421 (const_string "vector") 7422 (const_string "double"))) |
7423 (set_attr "amdfam10_decode" "double") |
7424 (set_attr "mode" "SI")]) 7425 7426;; The patterns that match these are at the end of this file. 7427 7428(define_expand "mulxf3" 7429 [(set (match_operand:XF 0 "register_operand" "") 7430 (mult:XF (match_operand:XF 1 "register_operand" "") 7431 (match_operand:XF 2 "register_operand" "")))] --- 2965 unchanged lines hidden (view full) --- 10397 (clobber (reg:CC FLAGS_REG))] 10398 "TARGET_64BIT" 10399 "@ 10400 shld{q}\t{%2, %1, %0|%0, %1, %2} 10401 shld{q}\t{%s2%1, %0|%0, %1, %2}" 10402 [(set_attr "type" "ishift") 10403 (set_attr "prefix_0f" "1") 10404 (set_attr "mode" "DI") |
10405 (set_attr "athlon_decode" "vector") 10406 (set_attr "amdfam10_decode" "vector")]) |
10407 10408(define_expand "x86_64_shift_adj" 10409 [(set (reg:CCZ FLAGS_REG) 10410 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "") 10411 (const_int 64)) 10412 (const_int 0))) 10413 (set (match_operand:DI 0 "register_operand" "") 10414 (if_then_else:DI (ne (reg:CCZ FLAGS_REG) (const_int 0)) --- 198 unchanged lines hidden (view full) --- 10613 "" 10614 "@ 10615 shld{l}\t{%2, %1, %0|%0, %1, %2} 10616 shld{l}\t{%s2%1, %0|%0, %1, %2}" 10617 [(set_attr "type" "ishift") 10618 (set_attr "prefix_0f" "1") 10619 (set_attr "mode" "SI") 10620 (set_attr "pent_pair" "np") |
10621 (set_attr "athlon_decode" "vector") 10622 (set_attr "amdfam10_decode" "vector")]) |
10623 10624(define_expand "x86_shift_adj_1" 10625 [(set (reg:CCZ FLAGS_REG) 10626 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "") 10627 (const_int 32)) 10628 (const_int 0))) 10629 (set (match_operand:SI 0 "register_operand" "") 10630 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0)) --- 743 unchanged lines hidden (view full) --- 11374 (clobber (reg:CC FLAGS_REG))] 11375 "TARGET_64BIT" 11376 "@ 11377 shrd{q}\t{%2, %1, %0|%0, %1, %2} 11378 shrd{q}\t{%s2%1, %0|%0, %1, %2}" 11379 [(set_attr "type" "ishift") 11380 (set_attr "prefix_0f" "1") 11381 (set_attr "mode" "DI") |
11382 (set_attr "athlon_decode" "vector") 11383 (set_attr "amdfam10_decode" "vector")]) |
11384 11385(define_expand "ashrdi3" 11386 [(set (match_operand:DI 0 "shiftdi_operand" "") 11387 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "") 11388 (match_operand:QI 2 "nonmemory_operand" "")))] 11389 "" 11390 "ix86_expand_binary_operator (ASHIFTRT, DImode, operands); DONE;") 11391 --- 3257 unchanged lines hidden (view full) --- 14649 [(set (match_operand:SI 0 "register_operand" "") 14650 (minus:SI (const_int 31) 14651 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "")))) 14652 (clobber (reg:CC FLAGS_REG))]) 14653 (parallel 14654 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31))) 14655 (clobber (reg:CC FLAGS_REG))])] 14656 "" |
14657{ 14658 if (TARGET_ABM) 14659 { 14660 emit_insn (gen_clzsi2_abm (operands[0], operands[1])); 14661 DONE; 14662 } 14663}) |
14664 |
14665(define_insn "clzsi2_abm" 14666 [(set (match_operand:SI 0 "register_operand" "=r") 14667 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))) 14668 (clobber (reg:CC FLAGS_REG))] 14669 "TARGET_ABM" 14670 "lzcnt{l}\t{%1, %0|%0, %1}" 14671 [(set_attr "prefix_rep" "1") 14672 (set_attr "type" "bitmanip") 14673 (set_attr "mode" "SI")]) 14674 |
14675(define_insn "*bsr" 14676 [(set (match_operand:SI 0 "register_operand" "=r") 14677 (minus:SI (const_int 31) 14678 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))) 14679 (clobber (reg:CC FLAGS_REG))] 14680 "" 14681 "bsr{l}\t{%1, %0|%0, %1}" |
14682 [(set_attr "prefix_0f" "1") 14683 (set_attr "mode" "SI")]) |
14684 |
14685(define_insn "popcountsi2" 14686 [(set (match_operand:SI 0 "register_operand" "=r") 14687 (popcount:SI (match_operand:SI 1 "nonimmediate_operand" ""))) 14688 (clobber (reg:CC FLAGS_REG))] 14689 "TARGET_POPCNT" 14690 "popcnt{l}\t{%1, %0|%0, %1}" 14691 [(set_attr "prefix_rep" "1") 14692 (set_attr "type" "bitmanip") 14693 (set_attr "mode" "SI")]) 14694 14695(define_insn "*popcountsi2_cmp" 14696 [(set (reg FLAGS_REG) 14697 (compare 14698 (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm")) 14699 (const_int 0))) 14700 (set (match_operand:SI 0 "register_operand" "=r") 14701 (popcount:SI (match_dup 1)))] 14702 "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)" 14703 "popcnt{l}\t{%1, %0|%0, %1}" 14704 [(set_attr "prefix_rep" "1") 14705 (set_attr "type" "bitmanip") 14706 (set_attr "mode" "SI")]) 14707 14708(define_insn "*popcountsi2_cmp_zext" 14709 [(set (reg FLAGS_REG) 14710 (compare 14711 (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm")) 14712 (const_int 0))) 14713 (set (match_operand:DI 0 "register_operand" "=r") 14714 (zero_extend:DI(popcount:SI (match_dup 1))))] 14715 "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)" 14716 "popcnt{l}\t{%1, %0|%0, %1}" 14717 [(set_attr "prefix_rep" "1") 14718 (set_attr "type" "bitmanip") 14719 (set_attr "mode" "SI")]) 14720 |
14721(define_expand "clzdi2" 14722 [(parallel 14723 [(set (match_operand:DI 0 "register_operand" "") 14724 (minus:DI (const_int 63) 14725 (clz:DI (match_operand:DI 1 "nonimmediate_operand" "")))) 14726 (clobber (reg:CC FLAGS_REG))]) 14727 (parallel 14728 [(set (match_dup 0) (xor:DI (match_dup 0) (const_int 63))) 14729 (clobber (reg:CC FLAGS_REG))])] 14730 "TARGET_64BIT" |
14731{ 14732 if (TARGET_ABM) 14733 { 14734 emit_insn (gen_clzdi2_abm (operands[0], operands[1])); 14735 DONE; 14736 } 14737}) |
14738 |
14739(define_insn "clzdi2_abm" 14740 [(set (match_operand:DI 0 "register_operand" "=r") 14741 (clz:DI (match_operand:DI 1 "nonimmediate_operand" ""))) 14742 (clobber (reg:CC FLAGS_REG))] 14743 "TARGET_64BIT && TARGET_ABM" 14744 "lzcnt{q}\t{%1, %0|%0, %1}" 14745 [(set_attr "prefix_rep" "1") 14746 (set_attr "type" "bitmanip") 14747 (set_attr "mode" "DI")]) 14748 |
14749(define_insn "*bsr_rex64" 14750 [(set (match_operand:DI 0 "register_operand" "=r") 14751 (minus:DI (const_int 63) 14752 (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))) 14753 (clobber (reg:CC FLAGS_REG))] 14754 "TARGET_64BIT" 14755 "bsr{q}\t{%1, %0|%0, %1}" |
14756 [(set_attr "prefix_0f" "1") 14757 (set_attr "mode" "DI")]) 14758 14759(define_insn "popcountdi2" 14760 [(set (match_operand:DI 0 "register_operand" "=r") 14761 (popcount:DI (match_operand:DI 1 "nonimmediate_operand" ""))) 14762 (clobber (reg:CC FLAGS_REG))] 14763 "TARGET_64BIT && TARGET_POPCNT" 14764 "popcnt{q}\t{%1, %0|%0, %1}" 14765 [(set_attr "prefix_rep" "1") 14766 (set_attr "type" "bitmanip") 14767 (set_attr "mode" "DI")]) 14768 14769(define_insn "*popcountdi2_cmp" 14770 [(set (reg FLAGS_REG) 14771 (compare 14772 (popcount:DI (match_operand:DI 1 "nonimmediate_operand" "rm")) 14773 (const_int 0))) 14774 (set (match_operand:DI 0 "register_operand" "=r") 14775 (popcount:DI (match_dup 1)))] 14776 "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)" 14777 "popcnt{q}\t{%1, %0|%0, %1}" 14778 [(set_attr "prefix_rep" "1") 14779 (set_attr "type" "bitmanip") 14780 (set_attr "mode" "DI")]) 14781 14782(define_expand "clzhi2" 14783 [(parallel 14784 [(set (match_operand:HI 0 "register_operand" "") 14785 (minus:HI (const_int 15) 14786 (clz:HI (match_operand:HI 1 "nonimmediate_operand" "")))) 14787 (clobber (reg:CC FLAGS_REG))]) 14788 (parallel 14789 [(set (match_dup 0) (xor:HI (match_dup 0) (const_int 15))) 14790 (clobber (reg:CC FLAGS_REG))])] 14791 "" 14792{ 14793 if (TARGET_ABM) 14794 { 14795 emit_insn (gen_clzhi2_abm (operands[0], operands[1])); 14796 DONE; 14797 } 14798}) 14799 14800(define_insn "clzhi2_abm" 14801 [(set (match_operand:HI 0 "register_operand" "=r") 14802 (clz:HI (match_operand:HI 1 "nonimmediate_operand" ""))) 14803 (clobber (reg:CC FLAGS_REG))] 14804 "TARGET_ABM" 14805 "lzcnt{w}\t{%1, %0|%0, %1}" 14806 [(set_attr "prefix_rep" "1") 14807 (set_attr "type" "bitmanip") 14808 (set_attr "mode" "HI")]) 14809 14810(define_insn "*bsrhi" 14811 [(set (match_operand:HI 0 "register_operand" "=r") 14812 (minus:HI (const_int 15) 14813 (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm")))) 14814 (clobber (reg:CC FLAGS_REG))] 14815 "" 14816 "bsr{w}\t{%1, %0|%0, %1}" 14817 [(set_attr "prefix_0f" "1") 14818 (set_attr "mode" "HI")]) 14819 14820(define_insn "popcounthi2" 14821 [(set (match_operand:HI 0 "register_operand" "=r") 14822 (popcount:HI (match_operand:HI 1 "nonimmediate_operand" ""))) 14823 (clobber (reg:CC FLAGS_REG))] 14824 "TARGET_POPCNT" 14825 "popcnt{w}\t{%1, %0|%0, %1}" 14826 [(set_attr "prefix_rep" "1") 14827 (set_attr "type" "bitmanip") 14828 (set_attr "mode" "HI")]) 14829 14830(define_insn "*popcounthi2_cmp" 14831 [(set (reg FLAGS_REG) 14832 (compare 14833 (popcount:HI (match_operand:HI 1 "nonimmediate_operand" "rm")) 14834 (const_int 0))) 14835 (set (match_operand:HI 0 "register_operand" "=r") 14836 (popcount:HI (match_dup 1)))] 14837 "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)" 14838 "popcnt{w}\t{%1, %0|%0, %1}" 14839 [(set_attr "prefix_rep" "1") 14840 (set_attr "type" "bitmanip") 14841 (set_attr "mode" "HI")]) |
14842 14843;; Thread-local storage patterns for ELF. 14844;; 14845;; Note that these code sequences must appear exactly as shown 14846;; in order to allow linker relaxation. 14847 14848(define_insn "*tls_global_dynamic_32_gnu" 14849 [(set (match_operand:SI 0 "register_operand" "=a") --- 889 unchanged lines hidden (view full) --- 15739 [(set (match_operand:SF 0 "register_operand" "=f,x") 15740 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0,xm")))] 15741 "TARGET_USE_FANCY_MATH_387 && TARGET_MIX_SSE_I387" 15742 "@ 15743 fsqrt 15744 sqrtss\t{%1, %0|%0, %1}" 15745 [(set_attr "type" "fpspc,sse") 15746 (set_attr "mode" "SF,SF") |
15747 (set_attr "athlon_decode" "direct,*") 15748 (set_attr "amdfam10_decode" "direct,*")]) |
15749 15750(define_insn "*sqrtsf2_sse" 15751 [(set (match_operand:SF 0 "register_operand" "=x") 15752 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))] 15753 "TARGET_SSE_MATH" 15754 "sqrtss\t{%1, %0|%0, %1}" 15755 [(set_attr "type" "sse") 15756 (set_attr "mode" "SF") |
15757 (set_attr "athlon_decode" "*") 15758 (set_attr "amdfam10_decode" "*")]) |
15759 15760(define_insn "*sqrtsf2_i387" 15761 [(set (match_operand:SF 0 "register_operand" "=f") 15762 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))] 15763 "TARGET_USE_FANCY_MATH_387" 15764 "fsqrt" 15765 [(set_attr "type" "fpspc") 15766 (set_attr "mode" "SF") |
15767 (set_attr "athlon_decode" "direct") 15768 (set_attr "amdfam10_decode" "direct")]) |
15769 15770(define_expand "sqrtdf2" 15771 [(set (match_operand:DF 0 "register_operand" "") 15772 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))] 15773 "TARGET_USE_FANCY_MATH_387 || (TARGET_SSE2 && TARGET_SSE_MATH)" 15774{ 15775 if (!(TARGET_SSE2 && TARGET_SSE_MATH)) 15776 operands[1] = force_reg (DFmode, operands[1]); 15777}) 15778 15779(define_insn "*sqrtdf2_mixed" 15780 [(set (match_operand:DF 0 "register_operand" "=f,Y") 15781 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0,Ym")))] 15782 "TARGET_USE_FANCY_MATH_387 && TARGET_SSE2 && TARGET_MIX_SSE_I387" 15783 "@ 15784 fsqrt 15785 sqrtsd\t{%1, %0|%0, %1}" 15786 [(set_attr "type" "fpspc,sse") 15787 (set_attr "mode" "DF,DF") |
15788 (set_attr "athlon_decode" "direct,*") 15789 (set_attr "amdfam10_decode" "direct,*")]) |
15790 15791(define_insn "*sqrtdf2_sse" 15792 [(set (match_operand:DF 0 "register_operand" "=Y") 15793 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))] 15794 "TARGET_SSE2 && TARGET_SSE_MATH" 15795 "sqrtsd\t{%1, %0|%0, %1}" 15796 [(set_attr "type" "sse") 15797 (set_attr "mode" "DF") |
15798 (set_attr "athlon_decode" "*") 15799 (set_attr "amdfam10_decode" "*")]) |
15800 15801(define_insn "*sqrtdf2_i387" 15802 [(set (match_operand:DF 0 "register_operand" "=f") 15803 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))] 15804 "TARGET_USE_FANCY_MATH_387" 15805 "fsqrt" 15806 [(set_attr "type" "fpspc") 15807 (set_attr "mode" "DF") |
15808 (set_attr "athlon_decode" "direct") 15809 (set_attr "amdfam10_decode" "direct")]) |
15810 15811(define_insn "*sqrtextendsfdf2_i387" 15812 [(set (match_operand:DF 0 "register_operand" "=f") 15813 (sqrt:DF (float_extend:DF 15814 (match_operand:SF 1 "register_operand" "0"))))] 15815 "TARGET_USE_FANCY_MATH_387 15816 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)" 15817 "fsqrt" 15818 [(set_attr "type" "fpspc") 15819 (set_attr "mode" "DF") |
15820 (set_attr "athlon_decode" "direct") 15821 (set_attr "amdfam10_decode" "direct")]) |
15822 15823(define_insn "sqrtxf2" 15824 [(set (match_operand:XF 0 "register_operand" "=f") 15825 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))] 15826 "TARGET_USE_FANCY_MATH_387" 15827 "fsqrt" 15828 [(set_attr "type" "fpspc") 15829 (set_attr "mode" "XF") |
15830 (set_attr "athlon_decode" "direct") 15831 (set_attr "amdfam10_decode" "direct")]) |
15832 15833(define_insn "*sqrtextendsfxf2_i387" 15834 [(set (match_operand:XF 0 "register_operand" "=f") 15835 (sqrt:XF (float_extend:XF 15836 (match_operand:SF 1 "register_operand" "0"))))] 15837 "TARGET_USE_FANCY_MATH_387" 15838 "fsqrt" 15839 [(set_attr "type" "fpspc") 15840 (set_attr "mode" "XF") |
15841 (set_attr "athlon_decode" "direct") 15842 (set_attr "amdfam10_decode" "direct")]) |
15843 15844(define_insn "*sqrtextenddfxf2_i387" 15845 [(set (match_operand:XF 0 "register_operand" "=f") 15846 (sqrt:XF (float_extend:XF 15847 (match_operand:DF 1 "register_operand" "0"))))] 15848 "TARGET_USE_FANCY_MATH_387" 15849 "fsqrt" 15850 [(set_attr "type" "fpspc") 15851 (set_attr "mode" "XF") |
15852 (set_attr "athlon_decode" "direct") 15853 (set_attr "amdfam10_decode" "direct")]) |
15854 15855(define_insn "fpremxf4" 15856 [(set (match_operand:XF 0 "register_operand" "=f") 15857 (unspec:XF [(match_operand:XF 2 "register_operand" "0") 15858 (match_operand:XF 3 "register_operand" "1")] 15859 UNSPEC_FPREM_F)) 15860 (set (match_operand:XF 1 "register_operand" "=u") 15861 (unspec:XF [(match_dup 2) (match_dup 3)] --- 4784 unchanged lines hidden (view full) --- 20646;; Imul $32bit_imm, mem, reg is vector decoded, while 20647;; imul $32bit_imm, reg, reg is direct decoded. 20648(define_peephole2 20649 [(match_scratch:DI 3 "r") 20650 (parallel [(set (match_operand:DI 0 "register_operand" "") 20651 (mult:DI (match_operand:DI 1 "memory_operand" "") 20652 (match_operand:DI 2 "immediate_operand" ""))) 20653 (clobber (reg:CC FLAGS_REG))])] |
20654 "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size |
20655 && !satisfies_constraint_K (operands[2])" 20656 [(set (match_dup 3) (match_dup 1)) 20657 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2))) 20658 (clobber (reg:CC FLAGS_REG))])] 20659"") 20660 20661(define_peephole2 20662 [(match_scratch:SI 3 "r") 20663 (parallel [(set (match_operand:SI 0 "register_operand" "") 20664 (mult:SI (match_operand:SI 1 "memory_operand" "") 20665 (match_operand:SI 2 "immediate_operand" ""))) 20666 (clobber (reg:CC FLAGS_REG))])] |
20667 "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size |
20668 && !satisfies_constraint_K (operands[2])" 20669 [(set (match_dup 3) (match_dup 1)) 20670 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2))) 20671 (clobber (reg:CC FLAGS_REG))])] 20672"") 20673 20674(define_peephole2 20675 [(match_scratch:SI 3 "r") 20676 (parallel [(set (match_operand:DI 0 "register_operand" "") 20677 (zero_extend:DI 20678 (mult:SI (match_operand:SI 1 "memory_operand" "") 20679 (match_operand:SI 2 "immediate_operand" "")))) 20680 (clobber (reg:CC FLAGS_REG))])] |
20681 "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size |
20682 && !satisfies_constraint_K (operands[2])" 20683 [(set (match_dup 3) (match_dup 1)) 20684 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2)))) 20685 (clobber (reg:CC FLAGS_REG))])] 20686"") 20687 20688;; imul $8/16bit_imm, regmem, reg is vector decoded. 20689;; Convert it into imul reg, reg 20690;; It would be better to force assembler to encode instruction using long 20691;; immediate, but there is apparently no way to do so. 20692(define_peephole2 20693 [(parallel [(set (match_operand:DI 0 "register_operand" "") 20694 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "") 20695 (match_operand:DI 2 "const_int_operand" ""))) 20696 (clobber (reg:CC FLAGS_REG))]) 20697 (match_scratch:DI 3 "r")] |
20698 "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size |
20699 && satisfies_constraint_K (operands[2])" 20700 [(set (match_dup 3) (match_dup 2)) 20701 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3))) 20702 (clobber (reg:CC FLAGS_REG))])] 20703{ 20704 if (!rtx_equal_p (operands[0], operands[1])) 20705 emit_move_insn (operands[0], operands[1]); 20706}) 20707 20708(define_peephole2 20709 [(parallel [(set (match_operand:SI 0 "register_operand" "") 20710 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "") 20711 (match_operand:SI 2 "const_int_operand" ""))) 20712 (clobber (reg:CC FLAGS_REG))]) 20713 (match_scratch:SI 3 "r")] |
20714 "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size |
20715 && satisfies_constraint_K (operands[2])" 20716 [(set (match_dup 3) (match_dup 2)) 20717 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3))) 20718 (clobber (reg:CC FLAGS_REG))])] 20719{ 20720 if (!rtx_equal_p (operands[0], operands[1])) 20721 emit_move_insn (operands[0], operands[1]); 20722}) 20723 20724(define_peephole2 20725 [(parallel [(set (match_operand:HI 0 "register_operand" "") 20726 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "") 20727 (match_operand:HI 2 "immediate_operand" ""))) 20728 (clobber (reg:CC FLAGS_REG))]) 20729 (match_scratch:HI 3 "r")] |
20730 "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size" |
20731 [(set (match_dup 3) (match_dup 2)) 20732 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3))) 20733 (clobber (reg:CC FLAGS_REG))])] 20734{ 20735 if (!rtx_equal_p (operands[0], operands[1])) 20736 emit_move_insn (operands[0], operands[1]); 20737}) 20738 --- 480 unchanged lines hidden --- |