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1;; GCC machine description for IA-32 and x86-64.
2;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
2;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3;; 2001, 2002, 2003
4;; Free Software Foundation, Inc.
5;; Mostly by William Schelter.
6;; x86_64 support added by Jan Hubicka
7;;
8;; This file is part of GNU CC.
9;;
10;; GNU CC is free software; you can redistribute it and/or modify
11;; it under the terms of the GNU General Public License as published by

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45;; 'J' Print the appropriate jump operand.
46;;
47;; 'b' Print the QImode name of the register for the indicated operand.
48;; %b0 would print %al if operands[0] is reg 0.
49;; 'w' Likewise, print the HImode name of the register.
50;; 'k' Likewise, print the SImode name of the register.
51;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
52;; 'y' Print "st(0)" instead of "st" as a register.
52;;
53
54;; UNSPEC usage:
54;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode.
55;; operand 0 is the memory address to scan.
56;; operand 1 is a register containing the value to scan for. The mode
57;; of the scas opcode will be the same as the mode of this operand.
58;; operand 2 is the known alignment of operand 0.
59;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
60;; operand 0 is the argument for `sin'.
61;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
62;; operand 0 is the argument for `cos'.
63;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is
64;; always SImode. operand 0 is the size of the stack allocation.
65;; 4 This is the source of a fake SET of the frame pointer which is used to
66;; prevent insns referencing it being scheduled across the initial
67;; decrement of the stack pointer.
68;; 5 This is a `bsf' operation.
69;; 6 This is the @GOT offset of a PIC address.
70;; 7 This is the @GOTOFF offset of a PIC address.
71;; 8 This is a reference to a symbol's @PLT address.
72;; 9 This is an `fnstsw' operation.
73;; 10 This is a `sahf' operation.
74;; 11 This is a `fstcw' operation
75;; 12 This is behaviour of add when setting carry flag.
76;; 13 This is a `eh_return' placeholder.
55
78;; For SSE/MMX support:
79;; 30 This is `fix', guaranteed to be truncating.
80;; 31 This is a `emms' operation.
81;; 32 This is a `maskmov' operation.
82;; 33 This is a `movmsk' operation.
83;; 34 This is a `non-temporal' move.
84;; 36 This is used to distinguish COMISS from UCOMISS.
85;; 37 This is a `ldmxcsr' operation.
86;; 38 This is a forced `movaps' instruction (rather than whatever movti does)
87;; 39 This is a forced `movups' instruction (rather than whatever movti does)
88;; 40 This is a `stmxcsr' operation.
89;; 41 This is a `shuffle' operation.
90;; 42 This is a `rcp' operation.
91;; 43 This is a `rsqsrt' operation.
92;; 44 This is a `sfence' operation.
93;; 45 This is a noop to prevent excessive combiner cleverness.
94;; 46 This is a `femms' operation.
95;; 49 This is a 'pavgusb' operation.
96;; 50 This is a `pfrcp' operation.
97;; 51 This is a `pfrcpit1' operation.
98;; 52 This is a `pfrcpit2' operation.
99;; 53 This is a `pfrsqrt' operation.
100;; 54 This is a `pfrsqrit1' operation.
56(define_constants
57 [; Relocation specifiers
58 (UNSPEC_GOT 0)
59 (UNSPEC_GOTOFF 1)
60 (UNSPEC_GOTPCREL 2)
61 (UNSPEC_GOTTPOFF 3)
62 (UNSPEC_TPOFF 4)
63 (UNSPEC_NTPOFF 5)
64 (UNSPEC_DTPOFF 6)
65 (UNSPEC_GOTNTPOFF 7)
66 (UNSPEC_INDNTPOFF 8)
67
68 ; Prologue support
69 (UNSPEC_STACK_PROBE 10)
70 (UNSPEC_STACK_ALLOC 11)
71 (UNSPEC_SET_GOT 12)
72 (UNSPEC_SSE_PROLOGUE_SAVE 13)
73
74 ; TLS support
75 (UNSPEC_TP 15)
76 (UNSPEC_TLS_GD 16)
77 (UNSPEC_TLS_LD_BASE 17)
78
79 ; Other random patterns
80 (UNSPEC_SCAS 20)
81 (UNSPEC_SIN 21)
82 (UNSPEC_COS 22)
83 (UNSPEC_BSF 23)
84 (UNSPEC_FNSTSW 24)
85 (UNSPEC_SAHF 25)
86 (UNSPEC_FSTCW 26)
87 (UNSPEC_ADD_CARRY 27)
88 (UNSPEC_FLDCW 28)
89
90 ; For SSE/MMX support:
91 (UNSPEC_FIX 30)
92 (UNSPEC_MASKMOV 32)
93 (UNSPEC_MOVMSK 33)
94 (UNSPEC_MOVNT 34)
95 (UNSPEC_MOVA 38)
96 (UNSPEC_MOVU 39)
97 (UNSPEC_SHUFFLE 41)
98 (UNSPEC_RCP 42)
99 (UNSPEC_RSQRT 43)
100 (UNSPEC_SFENCE 44)
101 (UNSPEC_NOP 45) ; prevents combiner cleverness
102 (UNSPEC_PAVGUSB 49)
103 (UNSPEC_PFRCP 50)
104 (UNSPEC_PFRCPIT1 51)
105 (UNSPEC_PFRCPIT2 52)
106 (UNSPEC_PFRSQRT 53)
107 (UNSPEC_PFRSQIT1 54)
108 (UNSPEC_PSHUFLW 55)
109 (UNSPEC_PSHUFHW 56)
110 (UNSPEC_MFENCE 59)
111 (UNSPEC_LFENCE 60)
112 (UNSPEC_PSADBW 61)
113 ])
114
115(define_constants
116 [(UNSPECV_BLOCKAGE 0)
117 (UNSPECV_EH_RETURN 13)
118 (UNSPECV_EMMS 31)
119 (UNSPECV_LDMXCSR 37)
120 (UNSPECV_STMXCSR 40)
121 (UNSPECV_FEMMS 46)
122 (UNSPECV_CLFLUSH 57)
123 ])
124
125;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
126;; from i386.c.
127
128;; In C guard expressions, put expressions which may be compile-time
129;; constants first. This allows for better optimization. For
130;; example, write "TARGET_64BIT && reload_completed", not
131;; "reload_completed && TARGET_64BIT".
132
133
134;; Processor type. This attribute must exactly match the processor_type
135;; enumeration in i386.h.
136(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
137 (const (symbol_ref "ix86_cpu")))
138
139;; A basic instruction type. Refinements due to arguments to be
140;; provided in other attributes.
141(define_attr "type"
119 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx,fistp"
142 "other,multi,
143 alu,alu1,negnot,imov,imovx,lea,
144 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
145 icmp,test,ibr,setcc,icmov,
146 push,pop,call,callv,
147 str,cld,
148 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,
149 sselog,sseiadd,sseishft,sseimul,
150 sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv,
151 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
152 (const_string "other"))
153
154;; Main data type used by the insn
123(define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI"
155(define_attr "mode"
156 "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI,V4SF,V2DF,V2SF"
157 (const_string "unknown"))
158
126;; Set for i387 operations.
127(define_attr "i387" ""
128 (if_then_else (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
129 (const_int 1)
130 (const_int 0)))
159;; The CPU unit operations uses.
160(define_attr "unit" "integer,i387,sse,mmx,unknown"
161 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
162 (const_string "i387")
163 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
164 sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv")
165 (const_string "sse")
166 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
167 (const_string "mmx")
168 (eq_attr "type" "other")
169 (const_string "unknown")]
170 (const_string "integer")))
171
172;; The (bounding maximum) length of an instruction immediate.
173(define_attr "length_immediate" ""
134 (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv,sse,mmx")
174 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv")
175 (const_int 0)
136 (eq_attr "i387" "1")
176 (eq_attr "unit" "i387,sse,mmx")
177 (const_int 0)
138 (eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop")
178 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
179 imul,icmp,push,pop")
180 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
181 (eq_attr "type" "imov,test")
182 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
183 (eq_attr "type" "call")
184 (if_then_else (match_operand 0 "constant_call_address_operand" "")
185 (const_int 4)
186 (const_int 0))
187 (eq_attr "type" "callv")
188 (if_then_else (match_operand 1 "constant_call_address_operand" "")
189 (const_int 4)
190 (const_int 0))
191 ;; We don't know the size before shorten_branches. Expect
192 ;; the instruction to fit for better scheduling.
193 (eq_attr "type" "ibr")
151 (if_then_else (and (ge (minus (match_dup 0) (pc))
152 (const_int -128))
153 (lt (minus (match_dup 0) (pc))
154 (const_int 124)))
155 (const_int 1)
156 (const_int 4))
194 (const_int 1)
195 ]
158 (symbol_ref "/* Update immediate_length and other attributes! */ abort(),1")))
196 (symbol_ref "/* Update immediate_length and other attributes! */
197 abort(),1")))
198
199;; The (bounding maximum) length of an instruction address.
200(define_attr "length_address" ""
201 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
202 (const_int 0)
203 (and (eq_attr "type" "call")
165 (match_operand 1 "constant_call_address_operand" ""))
204 (match_operand 0 "constant_call_address_operand" ""))
205 (const_int 0)
206 (and (eq_attr "type" "callv")
207 (match_operand 1 "constant_call_address_operand" ""))
208 (const_int 0)
209 ]
210 (symbol_ref "ix86_attr_length_address_default (insn)")))
211
212;; Set when length prefix is used.
213(define_attr "prefix_data16" ""
175 (if_then_else (eq_attr "mode" "HI")
214 (if_then_else (ior (eq_attr "mode" "HI")
215 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
216 (const_int 1)
217 (const_int 0)))
218
219;; Set when string REP prefix is used.
180(define_attr "prefix_rep" "" (const_int 0))
220(define_attr "prefix_rep" ""
221 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
222 (const_int 1)
223 (const_int 0)))
224
225;; Set when 0f opcode prefix is used.
226(define_attr "prefix_0f" ""
184 (if_then_else (eq_attr "type" "imovx,setcc,icmov,sse,mmx")
227 (if_then_else
228 (eq_attr "type"
229 "imovx,setcc,icmov,
230 sselog,sseiadd,sseishft,sseimul,
231 sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv,
232 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
233 (const_int 1)
234 (const_int 0)))
235
236;; Set when modrm byte is used.
237(define_attr "modrm" ""
238 (cond [(eq_attr "type" "str,cld")
239 (const_int 0)
192 (eq_attr "i387" "1")
240 (eq_attr "unit" "i387")
241 (const_int 0)
242 (and (eq_attr "type" "incdec")
243 (ior (match_operand:SI 1 "register_operand" "")
244 (match_operand:HI 1 "register_operand" "")))
245 (const_int 0)
246 (and (eq_attr "type" "push")
247 (not (match_operand 1 "memory_operand" "")))
248 (const_int 0)
249 (and (eq_attr "type" "pop")
250 (not (match_operand 0 "memory_operand" "")))
251 (const_int 0)
252 (and (eq_attr "type" "imov")
253 (and (match_operand 0 "register_operand" "")
254 (match_operand 1 "immediate_operand" "")))
255 (const_int 0)
256 (and (eq_attr "type" "call")
257 (match_operand 0 "constant_call_address_operand" ""))
258 (const_int 0)
259 (and (eq_attr "type" "callv")
260 (match_operand 1 "constant_call_address_operand" ""))
261 (const_int 0)
262 ]
263 (const_int 1)))
264
265;; The (bounding maximum) length of an instruction in bytes.
266;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want
267;; to split it and compute proper length as for other insns.
268(define_attr "length" ""
269 (cond [(eq_attr "type" "other,multi,fistp")
270 (const_int 16)
217 ]
271 (eq_attr "type" "fcmp")
272 (const_int 4)
273 (eq_attr "unit" "i387")
274 (plus (const_int 2)
275 (plus (attr "prefix_data16")
276 (attr "length_address")))]
277 (plus (plus (attr "modrm")
278 (plus (attr "prefix_0f")
220 (plus (attr "i387")
221 (const_int 1))))
279 (const_int 1)))
280 (plus (attr "prefix_rep")
281 (plus (attr "prefix_data16")
282 (plus (attr "length_immediate")
283 (attr "length_address")))))))
284
285;; The `memory' attribute is `none' if no memory is referenced, `load' or
286;; `store' if there is a simple memory reference therein, or `unknown'
287;; if the instruction is complex.

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296 (eq_attr "type" "push")
297 (if_then_else (match_operand 1 "memory_operand" "")
298 (const_string "both")
299 (const_string "store"))
300 (eq_attr "type" "pop,setcc")
301 (if_then_else (match_operand 0 "memory_operand" "")
302 (const_string "both")
303 (const_string "load"))
246 (eq_attr "type" "icmp,test")
304 (eq_attr "type" "icmp,test,ssecmp,mmxcmp,fcmp")
305 (if_then_else (ior (match_operand 0 "memory_operand" "")
306 (match_operand 1 "memory_operand" ""))
307 (const_string "load")
308 (const_string "none"))
309 (eq_attr "type" "ibr")
310 (if_then_else (match_operand 0 "memory_operand" "")
311 (const_string "load")
312 (const_string "none"))

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323 (const_string "both")
324 (and (match_operand 0 "memory_operand" "")
325 (match_operand 1 "memory_operand" ""))
326 (const_string "both")
327 (match_operand 0 "memory_operand" "")
328 (const_string "store")
329 (match_operand 1 "memory_operand" "")
330 (const_string "load")
273 (and (eq_attr "type" "!icmp,test,alu1,negnot,fop1,fsgn,imov,imovx,fmov,fcmp,sse,mmx")
331 (and (eq_attr "type"
332 "!alu1,negnot,
333 imov,imovx,icmp,test,
334 fmov,fcmp,fsgn,
335 sse,ssemov,ssecmp,ssecvt,
336 mmx,mmxmov,mmxcmp,mmxcvt")
337 (match_operand 2 "memory_operand" ""))
338 (const_string "load")
339 (and (eq_attr "type" "icmov")
340 (match_operand 3 "memory_operand" ""))
341 (const_string "load")
342 ]
343 (const_string "none")))
344
345;; Indicates if an instruction has both an immediate and a displacement.
346
347(define_attr "imm_disp" "false,true,unknown"
348 (cond [(eq_attr "type" "other,multi")
349 (const_string "unknown")
287 (and (eq_attr "type" "icmp,test,imov")
350 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
351 (and (match_operand 0 "memory_displacement_operand" "")
352 (match_operand 1 "immediate_operand" "")))
353 (const_string "true")
291 (and (eq_attr "type" "alu,ishift,imul,idiv")
354 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
355 (and (match_operand 0 "memory_displacement_operand" "")
356 (match_operand 2 "immediate_operand" "")))
357 (const_string "true")
358 ]
359 (const_string "false")))
360
361;; Indicates if an FP operation has an integer source.
362
363(define_attr "fp_int_src" "false,true"
364 (const_string "false"))
365
366;; Describe a user's asm statement.
367(define_asm_attributes
368 [(set_attr "length" "128")
369 (set_attr "type" "multi")])
370
308;; Pentium Scheduling
309;;
310;; The Pentium is an in-order core with two integer pipelines.
311
312;; True for insns that behave like prefixed insns on the Pentium.
313(define_attr "pent_prefix" "false,true"
314 (if_then_else (ior (eq_attr "prefix_0f" "1")
315 (ior (eq_attr "prefix_data16" "1")
316 (eq_attr "prefix_rep" "1")))
317 (const_string "true")
318 (const_string "false")))
319
320;; Categorize how an instruction slots.
321
322;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
323;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
324;; rules, because it results in noticeably better code on non-MMX Pentium
325;; and doesn't hurt much on MMX. (Prefixed instructions are not very
326;; common, so the scheduler usualy has a non-prefixed insn to pair).
327
328(define_attr "pent_pair" "uv,pu,pv,np"
329 (cond [(eq_attr "imm_disp" "true")
330 (const_string "np")
331 (ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec")
332 (and (eq_attr "type" "pop,push")
333 (eq_attr "memory" "!both")))
334 (if_then_else (eq_attr "pent_prefix" "true")
335 (const_string "pu")
336 (const_string "uv"))
337 (eq_attr "type" "ibr")
338 (const_string "pv")
339 (and (eq_attr "type" "ishift")
340 (match_operand 2 "const_int_operand" ""))
341 (const_string "pu")
342 (and (eq_attr "type" "call")
343 (match_operand 0 "constant_call_address_operand" ""))
344 (const_string "pv")
345 (and (eq_attr "type" "callv")
346 (match_operand 1 "constant_call_address_operand" ""))
347 (const_string "pv")
348 ]
349 (const_string "np")))
350
351;; Rough readiness numbers. Fine tuning happens in i386.c.
352;;
353;; u describes pipe U
354;; v describes pipe V
355;; uv describes either pipe U or V for those that can issue to either
356;; np describes not paring
357;; fpu describes fpu
358;; fpm describes fp insns of different types are not pipelined.
359;;
360;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
361
362(define_function_unit "pent_np" 1 0
363 (and (eq_attr "cpu" "pentium")
364 (eq_attr "type" "imul"))
365 11 11)
366
367(define_function_unit "pent_mul" 1 1
368 (and (eq_attr "cpu" "pentium")
369 (eq_attr "type" "imul"))
370 11 11)
371
372;; Rep movs takes minimally 12 cycles.
373(define_function_unit "pent_np" 1 0
374 (and (eq_attr "cpu" "pentium")
375 (eq_attr "type" "str"))
376 12 12)
377
378; ??? IDIV for SI takes 46 cycles, for HI 30, for QI 22
379(define_function_unit "pent_np" 1 0
380 (and (eq_attr "cpu" "pentium")
381 (eq_attr "type" "idiv"))
382 46 46)
383
384; Fp reg-reg moves takes 1 cycle. Loads takes 1 cycle for SF/DF mode,
385; 3 cycles for XFmode. Stores takes 2 cycles for SF/DF and 3 for XF.
386; fldz and fld1 takes 2 cycles. Only reg-reg moves are pairable.
387; The integer <-> fp conversion is not modeled correctly. Fild behaves
388; like normal fp operation and fist takes 6 cycles.
389
390(define_function_unit "fpu" 1 0
391 (and (eq_attr "cpu" "pentium")
392 (and (eq_attr "type" "fmov")
393 (and (eq_attr "memory" "load,store")
394 (eq_attr "mode" "XF"))))
395 3 3)
396
397(define_function_unit "pent_np" 1 0
398 (and (eq_attr "cpu" "pentium")
399 (and (eq_attr "type" "fmov")
400 (and (eq_attr "memory" "load,store")
401 (eq_attr "mode" "XF"))))
402 3 3)
403
404(define_function_unit "fpu" 1 0
405 (and (eq_attr "cpu" "pentium")
406 (and (eq_attr "type" "fmov")
407 (ior (match_operand 1 "immediate_operand" "")
408 (eq_attr "memory" "store"))))
409 2 2)
410
411(define_function_unit "pent_np" 1 0
412 (and (eq_attr "cpu" "pentium")
413 (and (eq_attr "type" "fmov")
414 (ior (match_operand 1 "immediate_operand" "")
415 (eq_attr "memory" "store"))))
416 2 2)
417
418(define_function_unit "pent_np" 1 0
419 (and (eq_attr "cpu" "pentium")
420 (eq_attr "type" "cld"))
421 2 2)
422
423(define_function_unit "fpu" 1 0
424 (and (eq_attr "cpu" "pentium")
425 (and (eq_attr "type" "fmov")
426 (eq_attr "memory" "none,load")))
427 1 1)
428
429; Read/Modify/Write instructions usually take 3 cycles.
430(define_function_unit "pent_u" 1 0
431 (and (eq_attr "cpu" "pentium")
432 (and (eq_attr "type" "alu,alu1,ishift")
433 (and (eq_attr "pent_pair" "pu")
434 (eq_attr "memory" "both"))))
435 3 3)
436
437(define_function_unit "pent_uv" 2 0
438 (and (eq_attr "cpu" "pentium")
439 (and (eq_attr "type" "alu,alu1,ishift")
440 (and (eq_attr "pent_pair" "!np")
441 (eq_attr "memory" "both"))))
442 3 3)
443
444(define_function_unit "pent_np" 1 0
445 (and (eq_attr "cpu" "pentium")
446 (and (eq_attr "type" "alu,alu1,negnot,ishift")
447 (and (eq_attr "pent_pair" "np")
448 (eq_attr "memory" "both"))))
449 3 3)
450
451; Read/Modify or Modify/Write instructions usually take 2 cycles.
452(define_function_unit "pent_u" 1 0
453 (and (eq_attr "cpu" "pentium")
454 (and (eq_attr "type" "alu,ishift")
455 (and (eq_attr "pent_pair" "pu")
456 (eq_attr "memory" "load,store"))))
457 2 2)
458
459(define_function_unit "pent_uv" 2 0
460 (and (eq_attr "cpu" "pentium")
461 (and (eq_attr "type" "alu,ishift")
462 (and (eq_attr "pent_pair" "!np")
463 (eq_attr "memory" "load,store"))))
464 2 2)
465
466(define_function_unit "pent_np" 1 0
467 (and (eq_attr "cpu" "pentium")
468 (and (eq_attr "type" "alu,ishift")
469 (and (eq_attr "pent_pair" "np")
470 (eq_attr "memory" "load,store"))))
471 2 2)
472
473; Insns w/o memory operands and move instructions usually take one cycle.
474(define_function_unit "pent_u" 1 0
475 (and (eq_attr "cpu" "pentium")
476 (eq_attr "pent_pair" "pu"))
477 1 1)
478
479(define_function_unit "pent_v" 1 0
480 (and (eq_attr "cpu" "pentium")
481 (eq_attr "pent_pair" "pv"))
482 1 1)
483
484(define_function_unit "pent_uv" 2 0
485 (and (eq_attr "cpu" "pentium")
486 (eq_attr "pent_pair" "!np"))
487 1 1)
488
489(define_function_unit "pent_np" 1 0
490 (and (eq_attr "cpu" "pentium")
491 (eq_attr "pent_pair" "np"))
492 1 1)
493
494; Pairable insns only conflict with other non-pairable insns.
495(define_function_unit "pent_np" 1 0
496 (and (eq_attr "cpu" "pentium")
497 (and (eq_attr "type" "alu,alu1,ishift")
498 (and (eq_attr "pent_pair" "!np")
499 (eq_attr "memory" "both"))))
500 3 3
501 [(eq_attr "pent_pair" "np")])
502
503(define_function_unit "pent_np" 1 0
504 (and (eq_attr "cpu" "pentium")
505 (and (eq_attr "type" "alu,alu1,ishift")
506 (and (eq_attr "pent_pair" "!np")
507 (eq_attr "memory" "load,store"))))
508 2 2
509 [(eq_attr "pent_pair" "np")])
510
511(define_function_unit "pent_np" 1 0
512 (and (eq_attr "cpu" "pentium")
513 (eq_attr "pent_pair" "!np"))
514 1 1
515 [(eq_attr "pent_pair" "np")])
516
517; Floating point instructions usually blocks cycle longer when combined with
518; integer instructions, because of the inpaired fxch instruction.
519(define_function_unit "pent_np" 1 0
520 (and (eq_attr "cpu" "pentium")
521 (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp,fistp"))
522 2 2
523 [(eq_attr "type" "!fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp,fistp")])
524
525(define_function_unit "fpu" 1 0
526 (and (eq_attr "cpu" "pentium")
527 (eq_attr "type" "fcmp,fxch,fsgn"))
528 1 1)
529
530; Addition takes 3 cycles; assume other random cruft does as well.
531; ??? Trivial fp operations such as fabs or fchs takes only one cycle.
532(define_function_unit "fpu" 1 0
533 (and (eq_attr "cpu" "pentium")
534 (eq_attr "type" "fop,fop1,fistp"))
535 3 1)
536
537; Multiplication takes 3 cycles and is only half pipelined.
538(define_function_unit "fpu" 1 0
539 (and (eq_attr "cpu" "pentium")
540 (eq_attr "type" "fmul"))
541 3 1)
542
543(define_function_unit "pent_mul" 1 1
544 (and (eq_attr "cpu" "pentium")
545 (eq_attr "type" "fmul"))
546 2 2)
547
548; ??? This is correct only for fdiv and sqrt -- sin/cos take 65-100 cycles.
549; They can overlap with integer insns. Only the last two cycles can overlap
550; with other fp insns. Only fsin/fcos can overlap with multiplies.
551; Only last two cycles of fsin/fcos can overlap with other instructions.
552(define_function_unit "fpu" 1 0
553 (and (eq_attr "cpu" "pentium")
554 (eq_attr "type" "fdiv"))
555 39 37)
556
557(define_function_unit "pent_mul" 1 1
558 (and (eq_attr "cpu" "pentium")
559 (eq_attr "type" "fdiv"))
560 39 39)
561
562(define_function_unit "fpu" 1 0
563 (and (eq_attr "cpu" "pentium")
564 (eq_attr "type" "fpspc"))
565 70 68)
566
567(define_function_unit "pent_mul" 1 1
568 (and (eq_attr "cpu" "pentium")
569 (eq_attr "type" "fpspc"))
570 70 70)
371(include "pentium.md")
372(include "ppro.md")
373(include "k6.md")
374(include "athlon.md")
375
572;; Pentium Pro/PII Scheduling
573;;
574;; The PPro has an out-of-order core, but the instruction decoders are
575;; naturally in-order and asymmetric. We get best performance by scheduling
576;; for the decoders, for in doing so we give the oo execution unit the
577;; most choices.
578
579;; Categorize how many uops an ia32 instruction evaluates to:
580;; one -- an instruction with 1 uop can be decoded by any of the
581;; three decoders.
582;; few -- an instruction with 1 to 4 uops can be decoded only by
583;; decoder 0.
584;; many -- a complex instruction may take an unspecified number of
585;; cycles to decode in decoder 0.
586
587(define_attr "ppro_uops" "one,few,many"
588 (cond [(eq_attr "type" "other,multi,call,callv,fpspc,str")
589 (const_string "many")
590 (eq_attr "type" "icmov,fcmov,str,cld")
591 (const_string "few")
592 (eq_attr "type" "imov")
593 (if_then_else (eq_attr "memory" "store,both")
594 (const_string "few")
595 (const_string "one"))
596 (eq_attr "memory" "!none")
597 (const_string "few")
598 ]
599 (const_string "one")))
600
601;; Rough readiness numbers. Fine tuning happens in i386.c.
602;;
603;; p0 describes port 0.
604;; p01 describes ports 0 and 1 as a pair; alu insns can issue to either.
605;; p2 describes port 2 for loads.
606;; p34 describes ports 3 and 4 for stores.
607;; fpu describes the fpu accessed via port 0.
608;; ??? It is less than clear if there are separate fadd and fmul units
609;; that could operate in parallel.
610;;
611;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
612
613(define_function_unit "ppro_p0" 1 0
614 (and (eq_attr "cpu" "pentiumpro")
615 (eq_attr "type" "ishift,lea,ibr,cld"))
616 1 1)
617
618(define_function_unit "ppro_p0" 1 0
619 (and (eq_attr "cpu" "pentiumpro")
620 (eq_attr "type" "imul"))
621 4 1)
622
623;; ??? Does the divider lock out the pipe while it works,
624;; or is there a disconnected unit?
625(define_function_unit "ppro_p0" 1 0
626 (and (eq_attr "cpu" "pentiumpro")
627 (eq_attr "type" "idiv"))
628 17 17)
629
630(define_function_unit "ppro_p0" 1 0
631 (and (eq_attr "cpu" "pentiumpro")
632 (eq_attr "type" "fop,fop1,fsgn,fistp"))
633 3 1)
634
635(define_function_unit "ppro_p0" 1 0
636 (and (eq_attr "cpu" "pentiumpro")
637 (eq_attr "type" "fcmov"))
638 2 1)
639
640(define_function_unit "ppro_p0" 1 0
641 (and (eq_attr "cpu" "pentiumpro")
642 (eq_attr "type" "fcmp"))
643 1 1)
644
645(define_function_unit "ppro_p0" 1 0
646 (and (eq_attr "cpu" "pentiumpro")
647 (eq_attr "type" "fmov"))
648 1 1)
649
650(define_function_unit "ppro_p0" 1 0
651 (and (eq_attr "cpu" "pentiumpro")
652 (eq_attr "type" "fmul"))
653 5 1)
654
655(define_function_unit "ppro_p0" 1 0
656 (and (eq_attr "cpu" "pentiumpro")
657 (eq_attr "type" "fdiv,fpspc"))
658 56 1)
659
660(define_function_unit "ppro_p01" 2 0
661 (and (eq_attr "cpu" "pentiumpro")
662 (eq_attr "type" "!imov,fmov"))
663 1 1)
664
665(define_function_unit "ppro_p01" 2 0
666 (and (and (eq_attr "cpu" "pentiumpro")
667 (eq_attr "type" "imov,fmov"))
668 (eq_attr "memory" "none"))
669 1 1)
670
671(define_function_unit "ppro_p2" 1 0
672 (and (eq_attr "cpu" "pentiumpro")
673 (ior (eq_attr "type" "pop")
674 (eq_attr "memory" "load,both")))
675 3 1)
676
677(define_function_unit "ppro_p34" 1 0
678 (and (eq_attr "cpu" "pentiumpro")
679 (ior (eq_attr "type" "push")
680 (eq_attr "memory" "store,both")))
681 1 1)
682
683(define_function_unit "fpu" 1 0
684 (and (eq_attr "cpu" "pentiumpro")
685 (eq_attr "type" "fop,fop1,fsgn,fmov,fcmp,fcmov,fistp"))
686 1 1)
687
688(define_function_unit "fpu" 1 0
689 (and (eq_attr "cpu" "pentiumpro")
690 (eq_attr "type" "fmul"))
691 5 2)
692
693(define_function_unit "fpu" 1 0
694 (and (eq_attr "cpu" "pentiumpro")
695 (eq_attr "type" "fdiv,fpspc"))
696 56 56)
697
698;; imul uses the fpu. ??? does it have the same throughput as fmul?
699(define_function_unit "fpu" 1 0
700 (and (eq_attr "cpu" "pentiumpro")
701 (eq_attr "type" "imul"))
702 4 1)
703
704;; AMD K6/K6-2 Scheduling
705;;
706;; The K6 has similar architecture to PPro. Important difference is, that
707;; there are only two decoders and they seems to be much slower than execution
708;; units. So we have to pay much more attention to proper decoding for
709;; schedulers. We share most of scheduler code for PPro in i386.c
710;;
711;; The fp unit is not pipelined and do one operation per two cycles including
712;; the FXCH.
713;;
714;; alu describes both ALU units (ALU-X and ALU-Y).
715;; alux describes X alu unit
716;; fpu describes FPU unit
717;; load describes load unit.
718;; branch describes branch unit.
719;; store decsribes store unit. This unit is not modelled completely and only
720;; used to model lea operation. Otherwise it lie outside of the critical
721;; path.
722;;
723;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
724
725;; The decoder specification is in the PPro section above!
726
727;; Shift instructions and certain arithmetic are issued only to X pipe.
728(define_function_unit "k6_alux" 1 0
729 (and (eq_attr "cpu" "k6")
730 (eq_attr "type" "ishift,alu1,negnot,cld"))
731 1 1)
732
733;; The QI mode arithmetic is issued to X pipe only.
734(define_function_unit "k6_alux" 1 0
735 (and (eq_attr "cpu" "k6")
736 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec")
737 (match_operand:QI 0 "general_operand" "")))
738 1 1)
739
740(define_function_unit "k6_alu" 2 0
741 (and (eq_attr "cpu" "k6")
742 (eq_attr "type" "ishift,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
743 1 1)
744
745(define_function_unit "k6_alu" 2 0
746 (and (eq_attr "cpu" "k6")
747 (and (eq_attr "type" "imov")
748 (eq_attr "memory" "none")))
749 1 1)
750
751(define_function_unit "k6_branch" 1 0
752 (and (eq_attr "cpu" "k6")
753 (eq_attr "type" "call,callv,ibr"))
754 1 1)
755
756;; Load unit have two cycle latency, but we take care for it in adjust_cost
757(define_function_unit "k6_load" 1 0
758 (and (eq_attr "cpu" "k6")
759 (ior (eq_attr "type" "pop")
760 (eq_attr "memory" "load,both")))
761 1 1)
762
763(define_function_unit "k6_load" 1 0
764 (and (eq_attr "cpu" "k6")
765 (and (eq_attr "type" "str")
766 (eq_attr "memory" "load,both")))
767 10 10)
768
769;; Lea have two instructions, so latency is probably 2
770(define_function_unit "k6_store" 1 0
771 (and (eq_attr "cpu" "k6")
772 (eq_attr "type" "lea"))
773 2 1)
774
775(define_function_unit "k6_store" 1 0
776 (and (eq_attr "cpu" "k6")
777 (eq_attr "type" "str"))
778 10 10)
779
780(define_function_unit "k6_store" 1 0
781 (and (eq_attr "cpu" "k6")
782 (ior (eq_attr "type" "push")
783 (eq_attr "memory" "store,both")))
784 1 1)
785
786(define_function_unit "k6_fpu" 1 1
787 (and (eq_attr "cpu" "k6")
788 (eq_attr "type" "fop,fop1,fmov,fcmp,fistp"))
789 2 2)
790
791(define_function_unit "k6_fpu" 1 1
792 (and (eq_attr "cpu" "k6")
793 (eq_attr "type" "fmul"))
794 2 2)
795
796;; ??? Guess
797(define_function_unit "k6_fpu" 1 1
798 (and (eq_attr "cpu" "k6")
799 (eq_attr "type" "fdiv,fpspc"))
800 56 56)
801
802(define_function_unit "k6_alu" 2 0
803 (and (eq_attr "cpu" "k6")
804 (eq_attr "type" "imul"))
805 2 2)
806
807(define_function_unit "k6_alux" 1 0
808 (and (eq_attr "cpu" "k6")
809 (eq_attr "type" "imul"))
810 2 2)
811
812;; ??? Guess
813(define_function_unit "k6_alu" 2 0
814 (and (eq_attr "cpu" "k6")
815 (eq_attr "type" "idiv"))
816 17 17)
817
818(define_function_unit "k6_alux" 1 0
819 (and (eq_attr "cpu" "k6")
820 (eq_attr "type" "idiv"))
821 17 17)
822
823;; AMD Athlon Scheduling
824;;
825;; The Athlon does contain three pipelined FP units, three integer units and
826;; three address generation units.
827;;
828;; The predecode logic is determining boundaries of instructions in the 64
829;; byte cache line. So the cache line straddling problem of K6 might be issue
830;; here as well, but it is not noted in the documentation.
831;;
832;; Three DirectPath instructions decoders and only one VectorPath decoder
833;; is available. They can decode three DirectPath instructions or one VectorPath
834;; instruction per cycle.
835;; Decoded macro instructions are then passed to 72 entry instruction control
836;; unit, that passes
837;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
838;;
839;; The load/store queue unit is not attached to the schedulers but
840;; communicates with all the execution units separately instead.
841
842(define_attr "athlon_decode" "direct,vector"
843 (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,fcmov")
844 (const_string "vector")
845 (and (eq_attr "type" "push")
846 (match_operand 1 "memory_operand" ""))
847 (const_string "vector")
848 (and (eq_attr "type" "fmov")
849 (and (eq_attr "memory" "load,store")
850 (eq_attr "mode" "XF")))
851 (const_string "vector")]
852 (const_string "direct")))
853
854(define_function_unit "athlon_vectordec" 1 0
855 (and (eq_attr "cpu" "athlon")
856 (eq_attr "athlon_decode" "vector"))
857 1 1)
858
859(define_function_unit "athlon_directdec" 3 0
860 (and (eq_attr "cpu" "athlon")
861 (eq_attr "athlon_decode" "direct"))
862 1 1)
863
864(define_function_unit "athlon_vectordec" 1 0
865 (and (eq_attr "cpu" "athlon")
866 (eq_attr "athlon_decode" "direct"))
867 1 1 [(eq_attr "athlon_decode" "vector")])
868
869(define_function_unit "athlon_ieu" 3 0
870 (and (eq_attr "cpu" "athlon")
871 (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
872 1 1)
873
874(define_function_unit "athlon_ieu" 3 0
875 (and (eq_attr "cpu" "athlon")
876 (eq_attr "type" "str"))
877 15 15)
878
879(define_function_unit "athlon_ieu" 3 0
880 (and (eq_attr "cpu" "athlon")
881 (eq_attr "type" "imul"))
882 5 0)
883
884(define_function_unit "athlon_ieu" 3 0
885 (and (eq_attr "cpu" "athlon")
886 (eq_attr "type" "idiv"))
887 42 0)
888
889(define_function_unit "athlon_muldiv" 1 0
890 (and (eq_attr "cpu" "athlon")
891 (eq_attr "type" "imul"))
892 5 0)
893
894(define_function_unit "athlon_muldiv" 1 0
895 (and (eq_attr "cpu" "athlon")
896 (eq_attr "type" "idiv"))
897 42 42)
898
899(define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
900 (cond [(eq_attr "type" "fop,fop1,fcmp,fistp")
901 (const_string "add")
902 (eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
903 (const_string "mul")
904 (and (eq_attr "type" "fmov") (eq_attr "memory" "store,both"))
905 (const_string "store")
906 (and (eq_attr "type" "fmov") (eq_attr "memory" "load"))
907 (const_string "any")
908 (and (eq_attr "type" "fmov")
909 (ior (match_operand:SI 1 "register_operand" "")
910 (match_operand 1 "immediate_operand" "")))
911 (const_string "store")
912 (eq_attr "type" "fmov")
913 (const_string "muladd")]
914 (const_string "none")))
915
916;; We use latencies 1 for definitions. This is OK to model colisions
917;; in execution units. The real latencies are modeled in the "fp" pipeline.
918
919;; fsin, fcos: 96-192
920;; fsincos: 107-211
921;; fsqrt: 19 for SFmode, 27 for DFmode, 35 for XFmode.
922(define_function_unit "athlon_fp" 3 0
923 (and (eq_attr "cpu" "athlon")
924 (eq_attr "type" "fpspc"))
925 100 1)
926
927;; 16 cycles for SFmode, 20 for DFmode and 24 for XFmode.
928(define_function_unit "athlon_fp" 3 0
929 (and (eq_attr "cpu" "athlon")
930 (eq_attr "type" "fdiv"))
931 24 1)
932
933(define_function_unit "athlon_fp" 3 0
934 (and (eq_attr "cpu" "athlon")
935 (eq_attr "type" "fop,fop1,fmul,fistp"))
936 4 1)
937
938;; XFmode loads are slow.
939;; XFmode store is slow too (8 cycles), but we don't need to model it, because
940;; there are no dependent instructions.
941
942(define_function_unit "athlon_fp" 3 0
943 (and (eq_attr "cpu" "athlon")
944 (and (eq_attr "type" "fmov")
945 (and (eq_attr "memory" "load")
946 (eq_attr "mode" "XF"))))
947 10 1)
948
949(define_function_unit "athlon_fp" 3 0
950 (and (eq_attr "cpu" "athlon")
951 (eq_attr "type" "fmov,fsgn"))
952 2 1)
953
954;; fcmp and ftst instructions
955(define_function_unit "athlon_fp" 3 0
956 (and (eq_attr "cpu" "athlon")
957 (and (eq_attr "type" "fcmp")
958 (eq_attr "athlon_decode" "direct")))
959 3 1)
960
961;; fcmpi instructions.
962(define_function_unit "athlon_fp" 3 0
963 (and (eq_attr "cpu" "athlon")
964 (and (eq_attr "type" "fcmp")
965 (eq_attr "athlon_decode" "vector")))
966 3 1)
967
968(define_function_unit "athlon_fp" 3 0
969 (and (eq_attr "cpu" "athlon")
970 (eq_attr "type" "fcmov"))
971 7 1)
972
973(define_function_unit "athlon_fp_mul" 1 0
974 (and (eq_attr "cpu" "athlon")
975 (eq_attr "athlon_fpunits" "mul"))
976 1 1)
977
978(define_function_unit "athlon_fp_add" 1 0
979 (and (eq_attr "cpu" "athlon")
980 (eq_attr "athlon_fpunits" "add"))
981 1 1)
982
983(define_function_unit "athlon_fp_muladd" 2 0
984 (and (eq_attr "cpu" "athlon")
985 (eq_attr "athlon_fpunits" "muladd,mul,add"))
986 1 1)
987
988(define_function_unit "athlon_fp_store" 1 0
989 (and (eq_attr "cpu" "athlon")
990 (eq_attr "athlon_fpunits" "store"))
991 1 1)
992
993;; We don't need to model the Address Generation Unit, since we don't model
994;; the re-order buffer yet and thus we never schedule more than three operations
995;; at time. Later we may want to experiment with MD_SCHED macros modeling the
996;; decoders independently on the functional units.
997
998;(define_function_unit "athlon_agu" 3 0
999; (and (eq_attr "cpu" "athlon")
1000; (and (eq_attr "memory" "!none")
1001; (eq_attr "athlon_fpunits" "none")))
1002; 1 1)
1003
1004;; Model load unit to avoid too long sequences of loads. We don't need to
1005;; model store queue, since it is hardly going to be bottleneck.
1006
1007(define_function_unit "athlon_load" 2 0
1008 (and (eq_attr "cpu" "athlon")
1009 (eq_attr "memory" "load,both"))
1010 1 1)
1011
1012
376;; Compare instructions.
377
378;; All compare insns have expanders that save the operands away without
379;; actually generating RTL. The bCOND or sCOND (emitted immediately
380;; after the cmp) will actually emit the cmpM.
381
382(define_expand "cmpdi"
383 [(set (reg:CC 17)

--- 356 unchanged lines hidden (view full) ---

740;;
741;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
742;; things aren't as bad as they sound...
743
744(define_insn "*cmpfp_0"
745 [(set (match_operand:HI 0 "register_operand" "=a")
746 (unspec:HI
747 [(compare:CCFP (match_operand 1 "register_operand" "f")
1385 (match_operand 2 "const0_operand" "X"))] 9))]
748 (match_operand 2 "const0_operand" "X"))]
749 UNSPEC_FNSTSW))]
750 "TARGET_80387
751 && FLOAT_MODE_P (GET_MODE (operands[1]))
752 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
753{
754 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
755 return "ftst\;fnstsw\t%0\;fstp\t%y0";
756 else
757 return "ftst\;fnstsw\t%0";

--- 14 unchanged lines hidden (view full) ---

772 [(set_attr "type" "fcmp")
773 (set_attr "mode" "SF")])
774
775(define_insn "*cmpfp_2_sf_1"
776 [(set (match_operand:HI 0 "register_operand" "=a")
777 (unspec:HI
778 [(compare:CCFP
779 (match_operand:SF 1 "register_operand" "f")
1416 (match_operand:SF 2 "nonimmediate_operand" "fm"))] 9))]
780 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
781 UNSPEC_FNSTSW))]
782 "TARGET_80387"
783 "* return output_fp_compare (insn, operands, 2, 0);"
784 [(set_attr "type" "fcmp")
785 (set_attr "mode" "SF")])
786
787(define_insn "*cmpfp_2_df"
788 [(set (reg:CCFP 18)
789 (compare:CCFP

--- 4 unchanged lines hidden (view full) ---

794 [(set_attr "type" "fcmp")
795 (set_attr "mode" "DF")])
796
797(define_insn "*cmpfp_2_df_1"
798 [(set (match_operand:HI 0 "register_operand" "=a")
799 (unspec:HI
800 [(compare:CCFP
801 (match_operand:DF 1 "register_operand" "f")
1437 (match_operand:DF 2 "nonimmediate_operand" "fm"))] 9))]
802 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
803 UNSPEC_FNSTSW))]
804 "TARGET_80387"
805 "* return output_fp_compare (insn, operands, 2, 0);"
806 [(set_attr "type" "multi")
807 (set_attr "mode" "DF")])
808
809(define_insn "*cmpfp_2_xf"
810 [(set (reg:CCFP 18)
811 (compare:CCFP

--- 14 unchanged lines hidden (view full) ---

826 [(set_attr "type" "fcmp")
827 (set_attr "mode" "XF")])
828
829(define_insn "*cmpfp_2_xf_1"
830 [(set (match_operand:HI 0 "register_operand" "=a")
831 (unspec:HI
832 [(compare:CCFP
833 (match_operand:XF 1 "register_operand" "f")
1468 (match_operand:XF 2 "register_operand" "f"))] 9))]
834 (match_operand:XF 2 "register_operand" "f"))]
835 UNSPEC_FNSTSW))]
836 "!TARGET_64BIT && TARGET_80387"
837 "* return output_fp_compare (insn, operands, 2, 0);"
838 [(set_attr "type" "multi")
839 (set_attr "mode" "XF")])
840
841(define_insn "*cmpfp_2_tf_1"
842 [(set (match_operand:HI 0 "register_operand" "=a")
843 (unspec:HI
844 [(compare:CCFP
845 (match_operand:TF 1 "register_operand" "f")
1479 (match_operand:TF 2 "register_operand" "f"))] 9))]
846 (match_operand:TF 2 "register_operand" "f"))]
847 UNSPEC_FNSTSW))]
848 "TARGET_80387"
849 "* return output_fp_compare (insn, operands, 2, 0);"
850 [(set_attr "type" "multi")
851 (set_attr "mode" "XF")])
852
853(define_insn "*cmpfp_2u"
854 [(set (reg:CCFPU 18)
855 (compare:CCFPU

--- 6 unchanged lines hidden (view full) ---

862 [(set_attr "type" "fcmp")
863 (set_attr "mode" "unknownfp")])
864
865(define_insn "*cmpfp_2u_1"
866 [(set (match_operand:HI 0 "register_operand" "=a")
867 (unspec:HI
868 [(compare:CCFPU
869 (match_operand 1 "register_operand" "f")
1502 (match_operand 2 "register_operand" "f"))] 9))]
870 (match_operand 2 "register_operand" "f"))]
871 UNSPEC_FNSTSW))]
872 "TARGET_80387
873 && FLOAT_MODE_P (GET_MODE (operands[1]))
874 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
875 "* return output_fp_compare (insn, operands, 2, 1);"
876 [(set_attr "type" "multi")
877 (set_attr "mode" "unknownfp")])
878
879;; Patterns to match the SImode-in-memory ficom instructions.

--- 31 unchanged lines hidden (view full) ---

911 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
912 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
913
914;; FP compares, step 2
915;; Move the fpsw to ax.
916
917(define_insn "x86_fnstsw_1"
918 [(set (match_operand:HI 0 "register_operand" "=a")
1550 (unspec:HI [(reg 18)] 9))]
919 (unspec:HI [(reg 18)] UNSPEC_FNSTSW))]
920 "TARGET_80387"
921 "fnstsw\t%0"
922 [(set_attr "length" "2")
923 (set_attr "mode" "SI")
1555 (set_attr "i387" "1")
924 (set_attr "unit" "i387")
925 (set_attr "ppro_uops" "few")])
926
927;; FP compares, step 3
928;; Get ax into flags, general case.
929
930(define_insn "x86_sahf_1"
931 [(set (reg:CC 17)
1563 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] 10))]
932 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
933 "!TARGET_64BIT"
934 "sahf"
935 [(set_attr "length" "1")
936 (set_attr "athlon_decode" "vector")
937 (set_attr "mode" "SI")
938 (set_attr "ppro_uops" "one")])
939
940;; Pentium Pro can do steps 1 through 3 in one go.

--- 14 unchanged lines hidden (view full) ---

955(define_insn "*cmpfp_i_sse"
956 [(set (reg:CCFP 17)
957 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
958 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
959 "TARGET_80387
960 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
961 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
962 "* return output_fp_compare (insn, operands, 1, 0);"
1594 [(set_attr "type" "fcmp,sse")
963 [(set_attr "type" "fcmp,ssecmp")
964 (set_attr "mode" "unknownfp")
965 (set_attr "athlon_decode" "vector")])
966
967(define_insn "*cmpfp_i_sse_only"
968 [(set (reg:CCFP 17)
969 (compare:CCFP (match_operand 0 "register_operand" "x")
970 (match_operand 1 "nonimmediate_operand" "xm")))]
971 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
972 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
973 "* return output_fp_compare (insn, operands, 1, 0);"
1605 [(set_attr "type" "sse")
974 [(set_attr "type" "ssecmp")
975 (set_attr "mode" "unknownfp")
976 (set_attr "athlon_decode" "vector")])
977
978(define_insn "*cmpfp_iu"
979 [(set (reg:CCFPU 17)
980 (compare:CCFPU (match_operand 0 "register_operand" "f")
981 (match_operand 1 "register_operand" "f")))]
982 "TARGET_80387 && TARGET_CMOVE

--- 8 unchanged lines hidden (view full) ---

991(define_insn "*cmpfp_iu_sse"
992 [(set (reg:CCFPU 17)
993 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
994 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
995 "TARGET_80387
996 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
997 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
998 "* return output_fp_compare (insn, operands, 1, 1);"
1630 [(set_attr "type" "fcmp,sse")
999 [(set_attr "type" "fcmp,ssecmp")
1000 (set_attr "mode" "unknownfp")
1001 (set_attr "athlon_decode" "vector")])
1002
1003(define_insn "*cmpfp_iu_sse_only"
1004 [(set (reg:CCFPU 17)
1005 (compare:CCFPU (match_operand 0 "register_operand" "x")
1006 (match_operand 1 "nonimmediate_operand" "xm")))]
1007 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1008 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1009 "* return output_fp_compare (insn, operands, 1, 1);"
1641 [(set_attr "type" "sse")
1010 [(set_attr "type" "ssecmp")
1011 (set_attr "mode" "unknownfp")
1012 (set_attr "athlon_decode" "vector")])
1013
1014;; Move instructions.
1015
1016;; General case of fullword move.
1017
1018(define_expand "movsi"

--- 78 unchanged lines hidden (view full) ---

1097{
1098 operands[1] = constm1_rtx;
1099 return "or{l}\t{%1, %0|%0, %1}";
1100}
1101 [(set_attr "type" "alu1")
1102 (set_attr "mode" "SI")
1103 (set_attr "length_immediate" "1")])
1104
1736; The first alternative is used only to compute proper length of instruction.
1737; Reload's algorithm does not take into account the cost of spill instructions
1738; needed to free register in given class, so avoid it from choosing the first
1739; alternative when eax is not available.
1740
1105(define_insn "*movsi_1"
1742 [(set (match_operand:SI 0 "nonimmediate_operand" "=*?a,r,*?a,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1743 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,*y,rm,*Y,*Y"))]
1106 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!rm,!*y,!*Y,!*Y,!rm")
1107 (match_operand:SI 1 "general_operand" "rinm,rin,rm,*y,*y,*Y,rm,*Y"))]
1108 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1109{
1110 switch (get_attr_type (insn))
1111 {
1748 case TYPE_SSE:
1749 if (get_attr_mode (insn) == TImode)
1112 case TYPE_SSEMOV:
1113 if (get_attr_mode (insn) == MODE_TI)
1114 return "movdqa\t{%1, %0|%0, %1}";
1115 return "movd\t{%1, %0|%0, %1}";
1116
1753 case TYPE_MMX:
1754 if (get_attr_mode (insn) == DImode)
1117 case TYPE_MMXMOV:
1118 if (get_attr_mode (insn) == MODE_DI)
1119 return "movq\t{%1, %0|%0, %1}";
1120 return "movd\t{%1, %0|%0, %1}";
1121
1122 case TYPE_LEA:
1123 return "lea{l}\t{%1, %0|%0, %1}";
1124
1125 default:
1762 if (flag_pic && SYMBOLIC_CONST (operands[1]))
1126 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1127 abort();
1128 return "mov{l}\t{%1, %0|%0, %1}";
1129 }
1130}
1131 [(set (attr "type")
1768 (cond [(eq_attr "alternative" "4,5,6")
1769 (const_string "mmx")
1770 (eq_attr "alternative" "7,8,9")
1771 (const_string "sse")
1132 (cond [(eq_attr "alternative" "2,3,4")
1133 (const_string "mmxmov")
1134 (eq_attr "alternative" "5,6,7")
1135 (const_string "ssemov")
1136 (and (ne (symbol_ref "flag_pic") (const_int 0))
1137 (match_operand:SI 1 "symbolic_operand" ""))
1138 (const_string "lea")
1139 ]
1140 (const_string "imov")))
1777 (set_attr "modrm" "0,*,0,*,*,*,*,*,*,*")
1778 (set_attr "mode" "SI,SI,SI,SI,SI,SI,DI,TI,SI,SI")])
1141 (set_attr "mode" "SI,SI,SI,SI,DI,TI,SI,SI")])
1142
1143;; Stores and loads of ax to arbitary constant address.
1144;; We fake an second form of instruction to force reload to load address
1145;; into register when rax is not available
1146(define_insn "*movabssi_1_rex64"
1784 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1785 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1786 "TARGET_64BIT"
1147 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1148 (match_operand:SI 1 "nonmemory_operand" "a,er"))]
1149 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1150 "@
1151 movabs{l}\t{%1, %P0|%P0, %1}
1789 mov{l}\t{%1, %a0|%a0, %1}
1790 movabs{l}\t{%1, %a0|%a0, %1}"
1152 mov{l}\t{%1, %a0|%a0, %1}"
1153 [(set_attr "type" "imov")
1792 (set_attr "modrm" "0,*,*")
1793 (set_attr "length_address" "8,0,0")
1794 (set_attr "length_immediate" "0,*,*")
1154 (set_attr "modrm" "0,*")
1155 (set_attr "length_address" "8,0")
1156 (set_attr "length_immediate" "0,*")
1157 (set_attr "memory" "store")
1158 (set_attr "mode" "SI")])
1159
1160(define_insn "*movabssi_2_rex64"
1161 [(set (match_operand:SI 0 "register_operand" "=a,r")
1162 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1801 "TARGET_64BIT"
1163 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1164 "@
1165 movabs{l}\t{%P1, %0|%0, %P1}
1166 mov{l}\t{%a1, %0|%0, %a1}"
1167 [(set_attr "type" "imov")
1168 (set_attr "modrm" "0,*")
1169 (set_attr "length_address" "8,0")
1170 (set_attr "length_immediate" "0")
1171 (set_attr "memory" "load")

--- 33 unchanged lines hidden (view full) ---

1205(define_insn "*pushhi2_rex64"
1206 [(set (match_operand:HI 0 "push_operand" "=X")
1207 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1208 "TARGET_64BIT"
1209 "push{q}\t%q1"
1210 [(set_attr "type" "push")
1211 (set_attr "mode" "QI")])
1212
1851; The first alternative is used only to compute proper length of instruction.
1852; Reload's algorithm does not take into account the cost of spill instructions
1853; needed to free register in given class, so avoid it from choosing the first
1854; alternative when eax is not available.
1855
1213(define_insn "*movhi_1"
1857 [(set (match_operand:HI 0 "nonimmediate_operand" "=*?a,r,r,*?a,r,m")
1858 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1214 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1215 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
1216 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1217{
1218 switch (get_attr_type (insn))
1219 {
1220 case TYPE_IMOVX:
1221 /* movzwl is faster than movw on p2 due to partial word stalls,
1222 though not as fast as an aligned movl. */
1223 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1224 default:
1225 if (get_attr_mode (insn) == MODE_SI)
1226 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1227 else
1228 return "mov{w}\t{%1, %0|%0, %1}";
1229 }
1230}
1231 [(set (attr "type")
1875 (cond [(and (eq_attr "alternative" "0,1")
1232 (cond [(and (eq_attr "alternative" "0")
1233 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1234 (const_int 0))
1235 (eq (symbol_ref "TARGET_HIMODE_MATH")
1236 (const_int 0))))
1237 (const_string "imov")
1881 (and (eq_attr "alternative" "2,3,4")
1238 (and (eq_attr "alternative" "1,2")
1239 (match_operand:HI 1 "aligned_operand" ""))
1240 (const_string "imov")
1241 (and (ne (symbol_ref "TARGET_MOVX")
1242 (const_int 0))
1886 (eq_attr "alternative" "0,1,3,4"))
1243 (eq_attr "alternative" "0,2"))
1244 (const_string "imovx")
1245 ]
1246 (const_string "imov")))
1247 (set (attr "mode")
1248 (cond [(eq_attr "type" "imovx")
1249 (const_string "SI")
1893 (and (eq_attr "alternative" "2,3,4")
1250 (and (eq_attr "alternative" "1,2")
1251 (match_operand:HI 1 "aligned_operand" ""))
1252 (const_string "SI")
1896 (and (eq_attr "alternative" "0,1")
1253 (and (eq_attr "alternative" "0")
1254 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1255 (const_int 0))
1256 (eq (symbol_ref "TARGET_HIMODE_MATH")
1257 (const_int 0))))
1258 (const_string "SI")
1259 ]
1903 (const_string "HI")))
1904 (set_attr "modrm" "0,*,*,0,*,*")])
1260 (const_string "HI")))])
1261
1262;; Stores and loads of ax to arbitary constant address.
1263;; We fake an second form of instruction to force reload to load address
1264;; into register when rax is not available
1265(define_insn "*movabshi_1_rex64"
1910 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1911 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1912 "TARGET_64BIT"
1266 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1267 (match_operand:HI 1 "nonmemory_operand" "a,er"))]
1268 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1269 "@
1270 movabs{w}\t{%1, %P0|%P0, %1}
1915 mov{w}\t{%1, %a0|%a0, %1}
1916 movabs{w}\t{%1, %a0|%a0, %1}"
1271 mov{w}\t{%1, %a0|%a0, %1}"
1272 [(set_attr "type" "imov")
1918 (set_attr "modrm" "0,*,*")
1919 (set_attr "length_address" "8,0,0")
1920 (set_attr "length_immediate" "0,*,*")
1273 (set_attr "modrm" "0,*")
1274 (set_attr "length_address" "8,0")
1275 (set_attr "length_immediate" "0,*")
1276 (set_attr "memory" "store")
1277 (set_attr "mode" "HI")])
1278
1279(define_insn "*movabshi_2_rex64"
1280 [(set (match_operand:HI 0 "register_operand" "=a,r")
1281 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1927 "TARGET_64BIT"
1282 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1283 "@
1284 movabs{w}\t{%P1, %0|%0, %P1}
1285 mov{w}\t{%a1, %0|%0, %a1}"
1286 [(set_attr "type" "imov")
1287 (set_attr "modrm" "0,*")
1288 (set_attr "length_address" "8,0")
1289 (set_attr "length_immediate" "0")
1290 (set_attr "memory" "load")

--- 181 unchanged lines hidden (view full) ---

1472 (set_attr "pent_pair" "np")
1473 (set_attr "mode" "QI")
1474 (set_attr "modrm" "0")
1475 (set_attr "ppro_uops" "few")])
1476
1477(define_expand "movstrictqi"
1478 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1479 (match_operand:QI 1 "general_operand" ""))]
2125 "! TARGET_PARTIAL_REG_STALL"
1480 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1481{
1482 /* Don't generate memory->memory moves, go through a register. */
1483 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1484 operands[1] = force_reg (QImode, operands[1]);
1485})
1486
1487(define_insn "*movstrictqi_1"
1488 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1489 (match_operand:QI 1 "general_operand" "*qn,m"))]
2135 "! TARGET_PARTIAL_REG_STALL
1490 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1491 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1492 "mov{b}\t{%1, %0|%0, %1}"
1493 [(set_attr "type" "imov")
1494 (set_attr "mode" "QI")])
1495
1496(define_insn "*movstrictqi_xor"
1497 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1498 (match_operand:QI 1 "const0_operand" "i"))

--- 77 unchanged lines hidden (view full) ---

1576 (if_then_else (eq_attr "type" "imovx")
1577 (const_string "SI")
1578 (const_string "QI")))])
1579
1580;; Stores and loads of ax to arbitary constant address.
1581;; We fake an second form of instruction to force reload to load address
1582;; into register when rax is not available
1583(define_insn "*movabsqi_1_rex64"
2229 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2230 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
2231 "TARGET_64BIT"
1584 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1585 (match_operand:QI 1 "nonmemory_operand" "a,er"))]
1586 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1587 "@
1588 movabs{b}\t{%1, %P0|%P0, %1}
2234 mov{b}\t{%1, %a0|%a0, %1}
2235 movabs{b}\t{%1, %a0|%a0, %1}"
1589 mov{b}\t{%1, %a0|%a0, %1}"
1590 [(set_attr "type" "imov")
2237 (set_attr "modrm" "0,*,*")
2238 (set_attr "length_address" "8,0,0")
2239 (set_attr "length_immediate" "0,*,*")
1591 (set_attr "modrm" "0,*")
1592 (set_attr "length_address" "8,0")
1593 (set_attr "length_immediate" "0,*")
1594 (set_attr "memory" "store")
1595 (set_attr "mode" "QI")])
1596
1597(define_insn "*movabsqi_2_rex64"
1598 [(set (match_operand:QI 0 "register_operand" "=a,r")
1599 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2246 "TARGET_64BIT"
1600 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1601 "@
1602 movabs{b}\t{%P1, %0|%0, %P1}
1603 mov{b}\t{%a1, %0|%0, %a1}"
1604 [(set_attr "type" "imov")
1605 (set_attr "modrm" "0,*")
1606 (set_attr "length_address" "8,0")
1607 (set_attr "length_immediate" "0")
1608 (set_attr "memory" "load")

--- 224 unchanged lines hidden (view full) ---

1833 "@
1834 #
1835 #
1836 movq\t{%1, %0|%0, %1}
1837 movq\t{%1, %0|%0, %1}
1838 movq\t{%1, %0|%0, %1}
1839 movdqa\t{%1, %0|%0, %1}
1840 movq\t{%1, %0|%0, %1}"
2487 [(set_attr "type" "*,*,mmx,mmx,sse,sse,sse")
1841 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1842 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1843
1844(define_split
1845 [(set (match_operand:DI 0 "push_operand" "")
1846 (match_operand:DI 1 "general_operand" ""))]
1847 "!TARGET_64BIT && reload_completed
1848 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1849 [(const_int 0)]

--- 12 unchanged lines hidden (view full) ---

1862(define_insn "*movdi_1_rex64"
1863 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,!*Y,!m,!*Y")
1864 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))]
1865 "TARGET_64BIT
1866 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1867{
1868 switch (get_attr_type (insn))
1869 {
2516 case TYPE_SSE:
1870 case TYPE_SSEMOV:
1871 if (register_operand (operands[0], DImode)
1872 && register_operand (operands[1], DImode))
1873 return "movdqa\t{%1, %0|%0, %1}";
1874 /* FALLTHRU */
2521 case TYPE_MMX:
1875 case TYPE_MMXMOV:
1876 return "movq\t{%1, %0|%0, %1}";
1877 case TYPE_MULTI:
1878 return "#";
1879 case TYPE_LEA:
1880 return "lea{q}\t{%a1, %0|%0, %a1}";
1881 default:
2528 if (flag_pic && SYMBOLIC_CONST (operands[1]))
1882 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1883 abort ();
1884 if (get_attr_mode (insn) == MODE_SI)
1885 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1886 else if (which_alternative == 2)
1887 return "movabs{q}\t{%1, %0|%0, %1}";
1888 else
1889 return "mov{q}\t{%1, %0|%0, %1}";
1890 }
1891}
1892 [(set (attr "type")
1893 (cond [(eq_attr "alternative" "5,6")
2540 (const_string "mmx")
2541 (eq_attr "alternative" "7,8")
2542 (const_string "sse")
1894 (const_string "mmxmov")
1895 (eq_attr "alternative" "7,8,9")
1896 (const_string "ssemov")
1897 (eq_attr "alternative" "4")
1898 (const_string "multi")
1899 (and (ne (symbol_ref "flag_pic") (const_int 0))
1900 (match_operand:DI 1 "symbolic_operand" ""))
1901 (const_string "lea")
1902 ]
1903 (const_string "imov")))
1904 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*")
1905 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*")
1906 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")])
1907
1908;; Stores and loads of ax to arbitary constant address.
1909;; We fake an second form of instruction to force reload to load address
1910;; into register when rax is not available
1911(define_insn "*movabsdi_1_rex64"
1912 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1913 (match_operand:DI 1 "nonmemory_operand" "a,er"))]
2560 "TARGET_64BIT"
1914 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1915 "@
1916 movabs{q}\t{%1, %P0|%P0, %1}
1917 mov{q}\t{%1, %a0|%a0, %1}"
1918 [(set_attr "type" "imov")
1919 (set_attr "modrm" "0,*")
1920 (set_attr "length_address" "8,0")
1921 (set_attr "length_immediate" "0,*")
1922 (set_attr "memory" "store")
1923 (set_attr "mode" "DI")])
1924
1925(define_insn "*movabsdi_2_rex64"
1926 [(set (match_operand:DI 0 "register_operand" "=a,r")
1927 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2574 "TARGET_64BIT"
1928 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1929 "@
1930 movabs{q}\t{%P1, %0|%0, %P1}
1931 mov{q}\t{%a1, %0|%0, %a1}"
1932 [(set_attr "type" "imov")
1933 (set_attr "modrm" "0,*")
1934 (set_attr "length_address" "8,0")
1935 (set_attr "length_immediate" "0")
1936 (set_attr "memory" "load")

--- 123 unchanged lines hidden (view full) ---

2060 [(set (match_dup 0)
2061 (match_dup 1))]
2062 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2063
2064
2065;; %%% Kill this when call knows how to work this out.
2066(define_split
2067 [(set (match_operand:SF 0 "push_operand" "")
2714 (match_operand:SF 1 "register_operand" ""))]
2715 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2068 (match_operand:SF 1 "any_fp_register_operand" ""))]
2069 "!TARGET_64BIT"
2070 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2071 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2072
2073(define_split
2074 [(set (match_operand:SF 0 "push_operand" "")
2721 (match_operand:SF 1 "register_operand" ""))]
2722 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2075 (match_operand:SF 1 "any_fp_register_operand" ""))]
2076 "TARGET_64BIT"
2077 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2078 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2079
2080(define_insn "*movsf_1"
2081 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2728 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf,rm,*y,*y"))]
2082 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,rm,*y,*y"))]
2083 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2084 && (reload_in_progress || reload_completed
2085 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2086 || GET_CODE (operands[1]) != CONST_DOUBLE
2087 || memory_operand (operands[0], SFmode))"
2088{
2089 switch (which_alternative)
2090 {

--- 21 unchanged lines hidden (view full) ---

2112 return "fld1";
2113 }
2114 abort();
2115
2116 case 3:
2117 case 4:
2118 return "mov{l}\t{%1, %0|%0, %1}";
2119 case 5:
2766 if (TARGET_SSE2)
2120 if (TARGET_SSE2 && !TARGET_ATHLON)
2121 return "pxor\t%0, %0";
2122 else
2123 return "xorps\t%0, %0";
2124 case 6:
2125 if (TARGET_PARTIAL_REG_DEPENDENCY)
2126 return "movaps\t{%1, %0|%0, %1}";
2127 else
2128 return "movss\t{%1, %0|%0, %1}";

--- 7 unchanged lines hidden (view full) ---

2136
2137 case 11:
2138 return "movq\t{%1, %0|%0, %1}";
2139
2140 default:
2141 abort();
2142 }
2143}
2790 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse,mmx,mmx,mmx")
2144 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2145 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI,DI")])
2146
2147(define_insn "*swapsf"
2148 [(set (match_operand:SF 0 "register_operand" "+f")
2149 (match_operand:SF 1 "register_operand" "+f"))
2150 (set (match_dup 1)
2151 (match_dup 0))]
2152 "reload_completed || !TARGET_SSE"

--- 79 unchanged lines hidden (view full) ---

2232 }
2233}
2234 [(set_attr "type" "multi")
2235 (set_attr "mode" "DF,SI,DF")])
2236
2237;; %%% Kill this when call knows how to work this out.
2238(define_split
2239 [(set (match_operand:DF 0 "push_operand" "")
2886 (match_operand:DF 1 "register_operand" ""))]
2887 "!TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2240 (match_operand:DF 1 "any_fp_register_operand" ""))]
2241 "!TARGET_64BIT && reload_completed"
2242 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2243 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2244 "")
2245
2246(define_split
2247 [(set (match_operand:DF 0 "push_operand" "")
2894 (match_operand:DF 1 "register_operand" ""))]
2895 "TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2248 (match_operand:DF 1 "any_fp_register_operand" ""))]
2249 "TARGET_64BIT && reload_completed"
2250 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2251 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2252 "")
2253
2254(define_split
2255 [(set (match_operand:DF 0 "push_operand" "")
2256 (match_operand:DF 1 "general_operand" ""))]
2257 "reload_completed"
2258 [(const_int 0)]
2259 "ix86_split_long_move (operands); DONE;")
2260
2261;; Moving is usually shorter when only FP registers are used. This separate
2262;; movdf pattern avoids the use of integer registers for FP operations
2263;; when optimizing for size.
2264
2265(define_insn "*movdf_nointeger"
2266 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2913 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,H,Y#f,YHm#f,Y#f"))]
2267 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,C,Y#f,YHm#f,Y#f"))]
2268 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2269 && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES)
2270 && (reload_in_progress || reload_completed
2271 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2272 || GET_CODE (operands[1]) != CONST_DOUBLE
2273 || memory_operand (operands[0], DFmode))"
2274{
2275 switch (which_alternative)

--- 22 unchanged lines hidden (view full) ---

2298 return "fld1";
2299 }
2300 abort();
2301
2302 case 3:
2303 case 4:
2304 return "#";
2305 case 5:
2952 return "pxor\t%0, %0";
2306 if (TARGET_ATHLON)
2307 return "xorpd\t%0, %0";
2308 else
2309 return "pxor\t%0, %0";
2310 case 6:
2311 if (TARGET_PARTIAL_REG_DEPENDENCY)
2312 return "movapd\t{%1, %0|%0, %1}";
2313 else
2314 return "movsd\t{%1, %0|%0, %1}";
2315 case 7:
2316 case 8:
2317 return "movsd\t{%1, %0|%0, %1}";
2318
2319 default:
2320 abort();
2321 }
2322}
2966 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
2323 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2324 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2325
2326(define_insn "*movdf_integer"
2327 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2971 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,H,Y#rf,Ym#rf,Y#rf"))]
2328 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,C,Y#rf,Ym#rf,Y#rf"))]
2329 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2330 && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
2331 && (reload_in_progress || reload_completed
2332 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2333 || GET_CODE (operands[1]) != CONST_DOUBLE
2334 || memory_operand (operands[0], DFmode))"
2335{
2336 switch (which_alternative)

--- 23 unchanged lines hidden (view full) ---

2360 }
2361 abort();
2362
2363 case 3:
2364 case 4:
2365 return "#";
2366
2367 case 5:
3011 return "pxor\t%0, %0";
2368 if (TARGET_ATHLON)
2369 return "xorpd\t%0, %0";
2370 else
2371 return "pxor\t%0, %0";
2372 case 6:
2373 if (TARGET_PARTIAL_REG_DEPENDENCY)
2374 return "movapd\t{%1, %0|%0, %1}";
2375 else
2376 return "movsd\t{%1, %0|%0, %1}";
2377 case 7:
2378 case 8:
2379 return "movsd\t{%1, %0|%0, %1}";
2380
2381 default:
2382 abort();
2383 }
2384}
3025 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
2385 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2386 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2387
2388(define_split
2389 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2390 (match_operand:DF 1 "general_operand" ""))]
2391 "reload_completed
2392 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2393 && ! (ANY_FP_REG_P (operands[0]) ||

--- 157 unchanged lines hidden (view full) ---

2551
2552(define_split
2553 [(set (match_operand 0 "push_operand" "")
2554 (match_operand 1 "general_operand" ""))]
2555 "reload_completed
2556 && (GET_MODE (operands[0]) == XFmode
2557 || GET_MODE (operands[0]) == TFmode
2558 || GET_MODE (operands[0]) == DFmode)
3199 && (!REG_P (operands[1]) || !ANY_FP_REGNO_P (REGNO (operands[1])))"
2559 && !ANY_FP_REG_P (operands[1])"
2560 [(const_int 0)]
2561 "ix86_split_long_move (operands); DONE;")
2562
2563(define_split
2564 [(set (match_operand:XF 0 "push_operand" "")
3205 (match_operand:XF 1 "register_operand" ""))]
3206 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2565 (match_operand:XF 1 "any_fp_register_operand" ""))]
2566 "!TARGET_64BIT"
2567 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
2568 (set (mem:XF (reg:SI 7)) (match_dup 1))])
2569
2570(define_split
2571 [(set (match_operand:TF 0 "push_operand" "")
3212 (match_operand:TF 1 "register_operand" ""))]
3213 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2572 (match_operand:TF 1 "any_fp_register_operand" ""))]
2573 "!TARGET_64BIT"
2574 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
2575 (set (mem:TF (reg:SI 7)) (match_dup 1))])
2576
2577(define_split
2578 [(set (match_operand:TF 0 "push_operand" "")
3219 (match_operand:TF 1 "register_operand" ""))]
3220 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2579 (match_operand:TF 1 "any_fp_register_operand" ""))]
2580 "TARGET_64BIT"
2581 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
2582 (set (mem:TF (reg:DI 7)) (match_dup 1))])
2583
2584;; Do not use integer registers when optimizing for size
2585(define_insn "*movxf_nointeger"
2586 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2587 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2588 "!TARGET_64BIT

--- 735 unchanged lines hidden (view full) ---

3324(define_insn "*dummy_extendsfdf2"
3325 [(set (match_operand:DF 0 "push_operand" "=<")
3326 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3327 "0"
3328 "#")
3329
3330(define_split
3331 [(set (match_operand:DF 0 "push_operand" "")
3972 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3973 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3332 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3333 "!TARGET_64BIT"
3334 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3335 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3336
3337(define_split
3338 [(set (match_operand:DF 0 "push_operand" "")
3979 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3980 "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3339 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3340 "TARGET_64BIT"
3341 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3342 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3343
3344(define_insn "*dummy_extendsfxf2"
3345 [(set (match_operand:XF 0 "push_operand" "=<")
3346 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3347 "0"
3348 "#")
3349
3350(define_split
3351 [(set (match_operand:XF 0 "push_operand" "")
3992 (float_extend:XF (match_operand:SF 1 "register_operand" "")))]
3993 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3352 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3353 "!TARGET_64BIT"
3354 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3355 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3356
3357(define_insn "*dummy_extendsftf2"
3358 [(set (match_operand:TF 0 "push_operand" "=<")
3359 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3360 "0"
3361 "#")
3362
3363(define_split
3364 [(set (match_operand:TF 0 "push_operand" "")
4005 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
4006 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3365 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
3366 "!TARGET_64BIT"
3367 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3368 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
3369
3370(define_split
3371 [(set (match_operand:TF 0 "push_operand" "")
4012 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
4013 "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3372 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
3373 "TARGET_64BIT"
3374 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3375 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3376
3377(define_insn "*dummy_extenddfxf2"
3378 [(set (match_operand:XF 0 "push_operand" "=<")
3379 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3380 "0"
3381 "#")
3382
3383(define_split
3384 [(set (match_operand:XF 0 "push_operand" "")
4025 (float_extend:XF (match_operand:DF 1 "register_operand" "")))]
4026 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3385 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3386 "!TARGET_64BIT"
3387 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3388 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3389
3390(define_insn "*dummy_extenddftf2"
3391 [(set (match_operand:TF 0 "push_operand" "=<")
3392 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3393 "0"
3394 "#")
3395
3396(define_split
3397 [(set (match_operand:TF 0 "push_operand" "")
4038 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
4039 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3398 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
3399 "!TARGET_64BIT"
3400 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3401 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3402
3403(define_split
3404 [(set (match_operand:TF 0 "push_operand" "")
4045 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
4046 "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3405 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
3406 "TARGET_64BIT"
3407 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3408 (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3409
3410(define_expand "extendsfdf2"
3411 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4052 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3412 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3413 "TARGET_80387 || TARGET_SSE2"
3414{
3415 /* ??? Needed for compress_float_constant since all fp constants
3416 are LEGITIMATE_CONSTANT_P. */
3417 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3418 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3419 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3420 operands[1] = force_reg (SFmode, operands[1]);
3421})
3422
3423(define_insn "*extendsfdf2_1"
3424 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3425 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3426 "(TARGET_80387 || TARGET_SSE2)

--- 18 unchanged lines hidden (view full) ---

3445 return "fst%z0\t%y0";
3446 case 2:
3447 return "cvtss2sd\t{%1, %0|%0, %1}";
3448
3449 default:
3450 abort ();
3451 }
3452}
4089 [(set_attr "type" "fmov,fmov,sse")
3453 [(set_attr "type" "fmov,fmov,ssecvt")
3454 (set_attr "mode" "SF,XF,DF")])
3455
3456(define_insn "*extendsfdf2_1_sse_only"
3457 [(set (match_operand:DF 0 "register_operand" "=Y")
3458 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3459 "!TARGET_80387 && TARGET_SSE2
3460 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3461 "cvtss2sd\t{%1, %0|%0, %1}"
4098 [(set_attr "type" "sse")
3462 [(set_attr "type" "ssecvt")
3463 (set_attr "mode" "DF")])
3464
3465(define_expand "extendsfxf2"
3466 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4103 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "")))]
3467 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3468 "!TARGET_64BIT && TARGET_80387"
3469{
3470 /* ??? Needed for compress_float_constant since all fp constants
3471 are LEGITIMATE_CONSTANT_P. */
3472 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3473 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3474 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3475 operands[1] = force_reg (SFmode, operands[1]);
3476})
3477
3478(define_insn "*extendsfxf2_1"
3479 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3480 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3481 "!TARGET_64BIT && TARGET_80387

--- 22 unchanged lines hidden (view full) ---

3504 abort ();
3505 }
3506}
3507 [(set_attr "type" "fmov")
3508 (set_attr "mode" "SF,XF")])
3509
3510(define_expand "extendsftf2"
3511 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4144 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
3512 (float_extend:TF (match_operand:SF 1 "general_operand" "")))]
3513 "TARGET_80387"
3514{
3515 /* ??? Needed for compress_float_constant since all fp constants
3516 are LEGITIMATE_CONSTANT_P. */
3517 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3518 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3519 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3520 operands[1] = force_reg (SFmode, operands[1]);
3521})
3522
3523(define_insn "*extendsftf2_1"
3524 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3525 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3526 "TARGET_80387

--- 22 unchanged lines hidden (view full) ---

3549 abort ();
3550 }
3551}
3552 [(set_attr "type" "fmov")
3553 (set_attr "mode" "SF,XF")])
3554
3555(define_expand "extenddfxf2"
3556 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4185 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "")))]
3557 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3558 "!TARGET_64BIT && TARGET_80387"
3559{
3560 /* ??? Needed for compress_float_constant since all fp constants
3561 are LEGITIMATE_CONSTANT_P. */
3562 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3563 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3564 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3565 operands[1] = force_reg (DFmode, operands[1]);
3566})
3567
3568(define_insn "*extenddfxf2_1"
3569 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3570 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3571 "!TARGET_64BIT && TARGET_80387

--- 22 unchanged lines hidden (view full) ---

3594 abort ();
3595 }
3596}
3597 [(set_attr "type" "fmov")
3598 (set_attr "mode" "DF,XF")])
3599
3600(define_expand "extenddftf2"
3601 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4226 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
3602 (float_extend:TF (match_operand:DF 1 "general_operand" "")))]
3603 "TARGET_80387"
3604{
3605 /* ??? Needed for compress_float_constant since all fp constants
3606 are LEGITIMATE_CONSTANT_P. */
3607 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3608 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3609 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3610 operands[1] = force_reg (DFmode, operands[1]);
3611})
3612
3613(define_insn "*extenddftf2_1"
3614 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3615 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3616 "TARGET_80387

--- 83 unchanged lines hidden (view full) ---

3700 else
3701 return "fst%z0\t%y0";
3702 case 4:
3703 return "cvtsd2ss\t{%1, %0|%0, %1}";
3704 default:
3705 abort ();
3706 }
3707}
4328 [(set_attr "type" "fmov,multi,multi,multi,sse")
3708 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3709 (set_attr "mode" "SF,SF,SF,SF,DF")])
3710
3711(define_insn "*truncdfsf2_2"
3712 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
3713 (float_truncate:SF
3714 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
3715 "TARGET_80387 && TARGET_SSE2
3716 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"

--- 6 unchanged lines hidden (view full) ---

3723 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3724 return "fstp%z0\t%y0";
3725 else
3726 return "fst%z0\t%y0";
3727 default:
3728 abort ();
3729 }
3730}
4351 [(set_attr "type" "sse,fmov")
3731 [(set_attr "type" "ssecvt,fmov")
3732 (set_attr "mode" "DF,SF")])
3733
3734(define_insn "truncdfsf2_3"
3735 [(set (match_operand:SF 0 "memory_operand" "=m")
3736 (float_truncate:SF
3737 (match_operand:DF 1 "register_operand" "f")))]
3738 "TARGET_80387"
3739{

--- 6 unchanged lines hidden (view full) ---

3746 (set_attr "mode" "SF")])
3747
3748(define_insn "truncdfsf2_sse_only"
3749 [(set (match_operand:SF 0 "register_operand" "=Y")
3750 (float_truncate:SF
3751 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
3752 "!TARGET_80387 && TARGET_SSE2"
3753 "cvtsd2ss\t{%1, %0|%0, %1}"
4374 [(set_attr "type" "sse")
3754 [(set_attr "type" "ssecvt")
3755 (set_attr "mode" "DF")])
3756
3757(define_split
3758 [(set (match_operand:SF 0 "memory_operand" "")
3759 (float_truncate:SF
3760 (match_operand:DF 1 "register_operand" "")))
3761 (clobber (match_operand:SF 2 "memory_operand" ""))]
3762 "TARGET_80387"

--- 8 unchanged lines hidden (view full) ---

3771 "TARGET_80387 && reload_completed
3772 && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
3773 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3774 "")
3775
3776(define_split
3777 [(set (match_operand:SF 0 "register_operand" "")
3778 (float_truncate:SF
4399 (match_operand:DF 1 "register_operand" "")))
3779 (match_operand:DF 1 "fp_register_operand" "")))
3780 (clobber (match_operand:SF 2 "memory_operand" ""))]
4401 "TARGET_80387 && reload_completed
4402 && FP_REG_P (operands[1])"
3781 "TARGET_80387 && reload_completed"
3782 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3783 (set (match_dup 0) (match_dup 2))]
3784 "")
3785
3786(define_expand "truncxfsf2"
3787 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3788 (float_truncate:SF
3789 (match_operand:XF 1 "register_operand" "")))

--- 372 unchanged lines hidden (view full) ---

4162 "")
4163
4164;; When SSE available, it is always faster to use it!
4165(define_insn "fix_truncsfdi_sse"
4166 [(set (match_operand:DI 0 "register_operand" "=r")
4167 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4168 "TARGET_64BIT && TARGET_SSE"
4169 "cvttss2si{q}\t{%1, %0|%0, %1}"
4791 [(set_attr "type" "sse")])
4170 [(set_attr "type" "ssecvt")])
4171
4172(define_insn "fix_truncdfdi_sse"
4173 [(set (match_operand:DI 0 "register_operand" "=r")
4174 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4175 "TARGET_64BIT && TARGET_SSE2"
4176 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4798 [(set_attr "type" "sse")])
4177 [(set_attr "type" "ssecvt")])
4178
4179;; Signed conversion to SImode.
4180
4181(define_expand "fix_truncxfsi2"
4182 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4183 (fix:SI (match_operand:XF 1 "register_operand" "")))]
4184 "!TARGET_64BIT && TARGET_80387"
4185 "")

--- 84 unchanged lines hidden (view full) ---

4270 [(set_attr "type" "fistp")])
4271
4272;; When SSE available, it is always faster to use it!
4273(define_insn "fix_truncsfsi_sse"
4274 [(set (match_operand:SI 0 "register_operand" "=r")
4275 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4276 "TARGET_SSE"
4277 "cvttss2si\t{%1, %0|%0, %1}"
4899 [(set_attr "type" "sse")])
4278 [(set_attr "type" "ssecvt")])
4279
4280(define_insn "fix_truncdfsi_sse"
4281 [(set (match_operand:SI 0 "register_operand" "=r")
4282 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4283 "TARGET_SSE2"
4284 "cvttsd2si\t{%1, %0|%0, %1}"
4906 [(set_attr "type" "sse")])
4285 [(set_attr "type" "ssecvt")])
4286
4287(define_split
4288 [(set (match_operand:SI 0 "register_operand" "")
4289 (fix:SI (match_operand 1 "register_operand" "")))
4290 (use (match_operand:HI 2 "memory_operand" ""))
4291 (use (match_operand:HI 3 "memory_operand" ""))
4292 (clobber (match_operand:SI 4 "memory_operand" ""))]
4293 "reload_completed"

--- 114 unchanged lines hidden (view full) ---

4408 (use (match_dup 3))
4409 (clobber (match_dup 4))])
4410 (set (match_dup 0) (match_dup 4))]
4411 "")
4412
4413;; %% Not used yet.
4414(define_insn "x86_fnstcw_1"
4415 [(set (match_operand:HI 0 "memory_operand" "=m")
5037 (unspec:HI [(reg:HI 18)] 11))]
4416 (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))]
4417 "TARGET_80387"
4418 "fnstcw\t%0"
4419 [(set_attr "length" "2")
4420 (set_attr "mode" "HI")
5042 (set_attr "i387" "1")
4421 (set_attr "unit" "i387")
4422 (set_attr "ppro_uops" "few")])
4423
4424(define_insn "x86_fldcw_1"
4425 [(set (reg:HI 18)
5047 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] 12))]
4426 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4427 "TARGET_80387"
4428 "fldcw\t%0"
4429 [(set_attr "length" "2")
4430 (set_attr "mode" "HI")
5052 (set_attr "i387" "1")
4431 (set_attr "unit" "i387")
4432 (set_attr "athlon_decode" "vector")
4433 (set_attr "ppro_uops" "few")])
4434
4435;; Conversion between fixed point and floating point.
4436
4437;; Even though we only accept memory inputs, the backend _really_
4438;; wants to be able to do this between registers.
4439

--- 17 unchanged lines hidden (view full) ---

4457(define_insn "*floatsisf2_i387"
4458 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
4459 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
4460 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4461 "@
4462 fild%z1\t%1
4463 #
4464 cvtsi2ss\t{%1, %0|%0, %1}"
5086 [(set_attr "type" "fmov,multi,sse")
4465 [(set_attr "type" "fmov,multi,ssecvt")
4466 (set_attr "mode" "SF")
4467 (set_attr "fp_int_src" "true")])
4468
4469(define_insn "*floatsisf2_sse"
4470 [(set (match_operand:SF 0 "register_operand" "=x")
4471 (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
4472 "TARGET_SSE"
4473 "cvtsi2ss\t{%1, %0|%0, %1}"
5095 [(set_attr "type" "sse")
4474 [(set_attr "type" "ssecvt")
4475 (set_attr "mode" "SF")
4476 (set_attr "fp_int_src" "true")])
4477
4478(define_expand "floatdisf2"
4479 [(set (match_operand:SF 0 "register_operand" "")
4480 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4481 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
4482 "")

--- 12 unchanged lines hidden (view full) ---

4495(define_insn "*floatdisf2_i387"
4496 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
4497 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
4498 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4499 "@
4500 fild%z1\t%1
4501 #
4502 cvtsi2ss{q}\t{%1, %0|%0, %1}"
5124 [(set_attr "type" "fmov,multi,sse")
4503 [(set_attr "type" "fmov,multi,ssecvt")
4504 (set_attr "mode" "SF")
4505 (set_attr "fp_int_src" "true")])
4506
4507(define_insn "*floatdisf2_sse"
4508 [(set (match_operand:SF 0 "register_operand" "=x")
4509 (float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
4510 "TARGET_64BIT && TARGET_SSE"
4511 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
5133 [(set_attr "type" "sse")
4512 [(set_attr "type" "ssecvt")
4513 (set_attr "mode" "SF")
4514 (set_attr "fp_int_src" "true")])
4515
4516(define_insn "floathidf2"
4517 [(set (match_operand:DF 0 "register_operand" "=f,f")
4518 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4519 "TARGET_80387 && !TARGET_SSE2"
4520 "@

--- 12 unchanged lines hidden (view full) ---

4533(define_insn "*floatsidf2_i387"
4534 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
4535 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
4536 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4537 "@
4538 fild%z1\t%1
4539 #
4540 cvtsi2sd\t{%1, %0|%0, %1}"
5162 [(set_attr "type" "fmov,multi,sse")
4541 [(set_attr "type" "fmov,multi,ssecvt")
4542 (set_attr "mode" "DF")
4543 (set_attr "fp_int_src" "true")])
4544
4545(define_insn "*floatsidf2_sse"
4546 [(set (match_operand:DF 0 "register_operand" "=Y")
4547 (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
4548 "TARGET_SSE2"
4549 "cvtsi2sd\t{%1, %0|%0, %1}"
5171 [(set_attr "type" "sse")
4550 [(set_attr "type" "ssecvt")
4551 (set_attr "mode" "DF")
4552 (set_attr "fp_int_src" "true")])
4553
4554(define_expand "floatdidf2"
4555 [(set (match_operand:DF 0 "register_operand" "")
4556 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
4557 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
4558 "")

--- 12 unchanged lines hidden (view full) ---

4571(define_insn "*floatdidf2_i387"
4572 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
4573 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
4574 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4575 "@
4576 fild%z1\t%1
4577 #
4578 cvtsi2sd{q}\t{%1, %0|%0, %1}"
5200 [(set_attr "type" "fmov,multi,sse")
4579 [(set_attr "type" "fmov,multi,ssecvt")
4580 (set_attr "mode" "DF")
4581 (set_attr "fp_int_src" "true")])
4582
4583(define_insn "*floatdidf2_sse"
4584 [(set (match_operand:DF 0 "register_operand" "=Y")
4585 (float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
4586 "TARGET_SSE2"
4587 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
5209 [(set_attr "type" "sse")
4588 [(set_attr "type" "ssecvt")
4589 (set_attr "mode" "DF")
4590 (set_attr "fp_int_src" "true")])
4591
4592(define_insn "floathixf2"
4593 [(set (match_operand:XF 0 "register_operand" "=f,f")
4594 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4595 "!TARGET_64BIT && TARGET_80387"
4596 "@

--- 55 unchanged lines hidden (view full) ---

4652 fild%z1\t%1
4653 #"
4654 [(set_attr "type" "fmov,multi")
4655 (set_attr "mode" "XF")
4656 (set_attr "fp_int_src" "true")])
4657
4658;; %%% Kill these when reload knows how to do it.
4659(define_split
5281 [(set (match_operand 0 "register_operand" "")
4660 [(set (match_operand 0 "fp_register_operand" "")
4661 (float (match_operand 1 "register_operand" "")))]
5283 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))
5284 && FP_REG_P (operands[0])"
4662 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
4663 [(const_int 0)]
4664{
4665 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
4666 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
4667 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
4668 ix86_free_from_memory (GET_MODE (operands[1]));
4669 DONE;
4670})

--- 22 unchanged lines hidden (view full) ---

4693 "#")
4694
4695(define_split
4696 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4697 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4698 (match_operand:DI 2 "general_operand" "")))
4699 (clobber (reg:CC 17))]
4700 "!TARGET_64BIT && reload_completed"
5323 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12))
4701 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)]
4702 UNSPEC_ADD_CARRY))
4703 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
4704 (parallel [(set (match_dup 3)
4705 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4706 (match_dup 4))
4707 (match_dup 5)))
4708 (clobber (reg:CC 17))])]
4709 "split_di (operands+0, 1, operands+0, operands+3);
4710 split_di (operands+1, 1, operands+1, operands+4);

--- 8 unchanged lines hidden (view full) ---

4719 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4720 "adc{q}\t{%2, %0|%0, %2}"
4721 [(set_attr "type" "alu")
4722 (set_attr "pent_pair" "pu")
4723 (set_attr "mode" "DI")
4724 (set_attr "ppro_uops" "few")])
4725
4726(define_insn "*adddi3_cc_rex64"
5348 [(set (reg:CC 17) (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5349 (match_operand:DI 2 "x86_64_general_operand" "re,rm")] 12))
4727 [(set (reg:CC 17)
4728 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
4729 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
4730 UNSPEC_ADD_CARRY))
4731 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4732 (plus:DI (match_dup 1) (match_dup 2)))]
4733 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4734 "add{q}\t{%2, %0|%0, %2}"
4735 [(set_attr "type" "alu")
4736 (set_attr "mode" "DI")])
4737
4738(define_insn "*addsi3_carry"

--- 19 unchanged lines hidden (view full) ---

4758 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
4759 "adc{l}\t{%2, %k0|%k0, %2}"
4760 [(set_attr "type" "alu")
4761 (set_attr "pent_pair" "pu")
4762 (set_attr "mode" "SI")
4763 (set_attr "ppro_uops" "few")])
4764
4765(define_insn "*addsi3_cc"
5385 [(set (reg:CC 17) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5386 (match_operand:SI 2 "general_operand" "ri,rm")] 12))
4766 [(set (reg:CC 17)
4767 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
4768 (match_operand:SI 2 "general_operand" "ri,rm")]
4769 UNSPEC_ADD_CARRY))
4770 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4771 (plus:SI (match_dup 1) (match_dup 2)))]
4772 "ix86_binary_operator_ok (PLUS, SImode, operands)"
4773 "add{l}\t{%2, %0|%0, %2}"
4774 [(set_attr "type" "alu")
4775 (set_attr "mode" "SI")])
4776
4777(define_insn "addqi3_cc"
5395 [(set (reg:CC 17) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5396 (match_operand:QI 2 "general_operand" "qi,qm")] 12))
4778 [(set (reg:CC 17)
4779 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
4780 (match_operand:QI 2 "general_operand" "qi,qm")]
4781 UNSPEC_ADD_CARRY))
4782 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4783 (plus:QI (match_dup 1) (match_dup 2)))]
4784 "ix86_binary_operator_ok (PLUS, QImode, operands)"
4785 "add{b}\t{%2, %0|%0, %2}"
4786 [(set_attr "type" "alu")
4787 (set_attr "mode" "QI")])
4788
4789(define_expand "addsi3"

--- 36 unchanged lines hidden (view full) ---

4826 [(set_attr "type" "lea")
4827 (set_attr "mode" "DI")])
4828
4829;; The lea patterns for non-Pmodes needs to be matched by several
4830;; insns converted to real lea by splitters.
4831
4832(define_insn_and_split "*lea_general_1"
4833 [(set (match_operand 0 "register_operand" "=r")
5449 (plus (plus (match_operand 1 "register_operand" "r")
4834 (plus (plus (match_operand 1 "index_register_operand" "r")
4835 (match_operand 2 "register_operand" "r"))
4836 (match_operand 3 "immediate_operand" "i")))]
4837 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
4838 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
4839 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4840 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4841 && GET_MODE (operands[0]) == GET_MODE (operands[2])
4842 && (GET_MODE (operands[0]) == GET_MODE (operands[3])

--- 15 unchanged lines hidden (view full) ---

4858 DONE;
4859}
4860 [(set_attr "type" "lea")
4861 (set_attr "mode" "SI")])
4862
4863(define_insn_and_split "*lea_general_1_zext"
4864 [(set (match_operand:DI 0 "register_operand" "=r")
4865 (zero_extend:DI
5481 (plus:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
4866 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r")
4867 (match_operand:SI 2 "register_operand" "r"))
4868 (match_operand:SI 3 "immediate_operand" "i"))))]
4869 "TARGET_64BIT"
4870 "#"
4871 "&& reload_completed"
4872 [(set (match_dup 0)
4873 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
4874 (match_dup 2))
4875 (match_dup 3)) 0)))]
4876{
4877 operands[1] = gen_lowpart (Pmode, operands[1]);
4878 operands[2] = gen_lowpart (Pmode, operands[2]);
4879 operands[3] = gen_lowpart (Pmode, operands[3]);
4880}
4881 [(set_attr "type" "lea")
4882 (set_attr "mode" "SI")])
4883
4884(define_insn_and_split "*lea_general_2"
4885 [(set (match_operand 0 "register_operand" "=r")
5501 (plus (mult (match_operand 1 "register_operand" "r")
4886 (plus (mult (match_operand 1 "index_register_operand" "r")
4887 (match_operand 2 "const248_operand" "i"))
4888 (match_operand 3 "nonmemory_operand" "ri")))]
4889 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
4890 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
4891 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4892 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4893 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
4894 || GET_MODE (operands[3]) == VOIDmode)"

--- 13 unchanged lines hidden (view full) ---

4908 DONE;
4909}
4910 [(set_attr "type" "lea")
4911 (set_attr "mode" "SI")])
4912
4913(define_insn_and_split "*lea_general_2_zext"
4914 [(set (match_operand:DI 0 "register_operand" "=r")
4915 (zero_extend:DI
5531 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4916 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
4917 (match_operand:SI 2 "const248_operand" "n"))
4918 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
4919 "TARGET_64BIT"
4920 "#"
4921 "&& reload_completed"
4922 [(set (match_dup 0)
4923 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
4924 (match_dup 2))
4925 (match_dup 3)) 0)))]
4926{
4927 operands[1] = gen_lowpart (Pmode, operands[1]);
4928 operands[3] = gen_lowpart (Pmode, operands[3]);
4929}
4930 [(set_attr "type" "lea")
4931 (set_attr "mode" "SI")])
4932
4933(define_insn_and_split "*lea_general_3"
4934 [(set (match_operand 0 "register_operand" "=r")
5550 (plus (plus (mult (match_operand 1 "register_operand" "r")
4935 (plus (plus (mult (match_operand 1 "index_register_operand" "r")
4936 (match_operand 2 "const248_operand" "i"))
4937 (match_operand 3 "register_operand" "r"))
4938 (match_operand 4 "immediate_operand" "i")))]
4939 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
4940 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
4941 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4942 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4943 && GET_MODE (operands[0]) == GET_MODE (operands[3])"

--- 17 unchanged lines hidden (view full) ---

4961 DONE;
4962}
4963 [(set_attr "type" "lea")
4964 (set_attr "mode" "SI")])
4965
4966(define_insn_and_split "*lea_general_3_zext"
4967 [(set (match_operand:DI 0 "register_operand" "=r")
4968 (zero_extend:DI
5584 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4969 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
4970 (match_operand:SI 2 "const248_operand" "n"))
4971 (match_operand:SI 3 "register_operand" "r"))
4972 (match_operand:SI 4 "immediate_operand" "i"))))]
4973 "TARGET_64BIT"
4974 "#"
4975 "&& reload_completed"
4976 [(set (match_dup 0)
4977 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)

--- 720 unchanged lines hidden (view full) ---

5698{
5699 switch (get_attr_type (insn))
5700 {
5701 case TYPE_LEA:
5702 return "#";
5703 case TYPE_INCDEC:
5704 if (operands[2] == const1_rtx)
5705 return "inc{w}\t%0";
6321 else if (operands[2] == constm1_rtx
6322 || (GET_CODE (operands[2]) == CONST_INT
6323 && INTVAL (operands[2]) == 65535))
5706 else if (operands[2] == constm1_rtx)
5707 return "dec{w}\t%0";
5708 abort();
5709
5710 default:
5711 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5712 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5713 if (GET_CODE (operands[2]) == CONST_INT
5714 && (INTVAL (operands[2]) == 128

--- 22 unchanged lines hidden (view full) ---

5737 "TARGET_PARTIAL_REG_STALL
5738 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5739{
5740 switch (get_attr_type (insn))
5741 {
5742 case TYPE_INCDEC:
5743 if (operands[2] == const1_rtx)
5744 return "inc{w}\t%0";
6362 else if (operands[2] == constm1_rtx
6363 || (GET_CODE (operands[2]) == CONST_INT
6364 && INTVAL (operands[2]) == 65535))
5745 else if (operands[2] == constm1_rtx)
5746 return "dec{w}\t%0";
5747 abort();
5748
5749 default:
5750 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5751 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5752 if (GET_CODE (operands[2]) == CONST_INT
5753 && (INTVAL (operands[2]) == 128

--- 23 unchanged lines hidden (view full) ---

5777 "ix86_match_ccmode (insn, CCGOCmode)
5778 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5779{
5780 switch (get_attr_type (insn))
5781 {
5782 case TYPE_INCDEC:
5783 if (operands[2] == const1_rtx)
5784 return "inc{w}\t%0";
6404 else if (operands[2] == constm1_rtx
6405 || (GET_CODE (operands[2]) == CONST_INT
6406 && INTVAL (operands[2]) == 65535))
5785 else if (operands[2] == constm1_rtx)
5786 return "dec{w}\t%0";
5787 abort();
5788
5789 default:
5790 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5791 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5792 if (GET_CODE (operands[2]) == CONST_INT
5793 && (INTVAL (operands[2]) == 128

--- 20 unchanged lines hidden (view full) ---

5814 "ix86_match_ccmode (insn, CCZmode)
5815 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5816{
5817 switch (get_attr_type (insn))
5818 {
5819 case TYPE_INCDEC:
5820 if (operands[2] == const1_rtx)
5821 return "inc{w}\t%0";
6443 else if (operands[2] == constm1_rtx
6444 || (GET_CODE (operands[2]) == CONST_INT
6445 && INTVAL (operands[2]) == 65535))
5822 else if (operands[2] == constm1_rtx)
5823 return "dec{w}\t%0";
5824 abort();
5825
5826 default:
5827 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5828 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5829 if (GET_CODE (operands[2]) == CONST_INT
5830 && (INTVAL (operands[2]) == 128

--- 19 unchanged lines hidden (view full) ---

5850 (match_operand:HI 2 "const_int_operand" "n")))
5851 (clobber (match_scratch:HI 0 "=rm"))]
5852 "ix86_match_ccmode (insn, CCGCmode)
5853 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
5854{
5855 switch (get_attr_type (insn))
5856 {
5857 case TYPE_INCDEC:
6481 if (operands[2] == constm1_rtx
6482 || (GET_CODE (operands[2]) == CONST_INT
6483 && INTVAL (operands[2]) == 65535))
5858 if (operands[2] == constm1_rtx)
5859 return "inc{w}\t%0";
5860 else if (operands[2] == const1_rtx)
5861 return "dec{w}\t%0";
5862 else
5863 abort();
5864
5865 default:
5866 if (! rtx_equal_p (operands[0], operands[1]))

--- 25 unchanged lines hidden (view full) ---

5892 "ix86_match_ccmode (insn, CCGOCmode)
5893 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5894{
5895 switch (get_attr_type (insn))
5896 {
5897 case TYPE_INCDEC:
5898 if (operands[2] == const1_rtx)
5899 return "inc{w}\t%0";
6525 else if (operands[2] == constm1_rtx
6526 || (GET_CODE (operands[2]) == CONST_INT
6527 && INTVAL (operands[2]) == 65535))
5900 else if (operands[2] == constm1_rtx)
5901 return "dec{w}\t%0";
5902 abort();
5903
5904 default:
5905 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5906 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5907 if (GET_CODE (operands[2]) == CONST_INT
5908 && (INTVAL (operands[2]) == 128

--- 32 unchanged lines hidden (view full) ---

5941 int widen = (which_alternative == 2);
5942 switch (get_attr_type (insn))
5943 {
5944 case TYPE_LEA:
5945 return "#";
5946 case TYPE_INCDEC:
5947 if (operands[2] == const1_rtx)
5948 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6576 else if (operands[2] == constm1_rtx
6577 || (GET_CODE (operands[2]) == CONST_INT
6578 && INTVAL (operands[2]) == 255))
5949 else if (operands[2] == constm1_rtx)
5950 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
5951 abort();
5952
5953 default:
5954 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5955 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5956 if (GET_CODE (operands[2]) == CONST_INT
5957 && (INTVAL (operands[2]) == 128

--- 29 unchanged lines hidden (view full) ---

5987 && ix86_binary_operator_ok (PLUS, QImode, operands)"
5988{
5989 int widen = (which_alternative == 2);
5990 switch (get_attr_type (insn))
5991 {
5992 case TYPE_INCDEC:
5993 if (operands[2] == const1_rtx)
5994 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6624 else if (operands[2] == constm1_rtx
6625 || (GET_CODE (operands[2]) == CONST_INT
6626 && INTVAL (operands[2]) == 255))
5995 else if (operands[2] == constm1_rtx)
5996 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
5997 abort();
5998
5999 default:
6000 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6001 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6002 if (GET_CODE (operands[2]) == CONST_INT
6003 && (INTVAL (operands[2]) == 128

--- 13 unchanged lines hidden (view full) ---

6017 }
6018}
6019 [(set (attr "type")
6020 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6021 (const_string "incdec")
6022 (const_string "alu")))
6023 (set_attr "mode" "QI,QI,SI")])
6024
6025(define_insn "*addqi_1_slp"
6026 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6027 (plus:QI (match_dup 0)
6028 (match_operand:QI 1 "general_operand" "qn,qnm")))
6029 (clobber (reg:CC 17))]
6030 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6031 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6032{
6033 switch (get_attr_type (insn))
6034 {
6035 case TYPE_INCDEC:
6036 if (operands[1] == const1_rtx)
6037 return "inc{b}\t%0";
6038 else if (operands[1] == constm1_rtx)
6039 return "dec{b}\t%0";
6040 abort();
6041
6042 default:
6043 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6044 if (GET_CODE (operands[1]) == CONST_INT
6045 && INTVAL (operands[1]) < 0)
6046 {
6047 operands[2] = GEN_INT (-INTVAL (operands[2]));
6048 return "sub{b}\t{%1, %0|%0, %1}";
6049 }
6050 return "add{b}\t{%1, %0|%0, %1}";
6051 }
6052}
6053 [(set (attr "type")
6054 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6055 (const_string "incdec")
6056 (const_string "alu1")))
6057 (set_attr "mode" "QI")])
6058
6059(define_insn "*addqi_2"
6060 [(set (reg 17)
6061 (compare
6062 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6063 (match_operand:QI 2 "general_operand" "qmni,qni"))
6064 (const_int 0)))
6065 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6066 (plus:QI (match_dup 1) (match_dup 2)))]

--- 515 unchanged lines hidden (view full) ---

6582 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6583 (match_operand:QI 2 "general_operand" "qn,qmn")))
6584 (clobber (reg:CC 17))]
6585 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6586 "sub{b}\t{%2, %0|%0, %2}"
6587 [(set_attr "type" "alu")
6588 (set_attr "mode" "QI")])
6589
6590(define_insn "*subqi_1_slp"
6591 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6592 (minus:QI (match_dup 0)
6593 (match_operand:QI 1 "general_operand" "qn,qmn")))
6594 (clobber (reg:CC 17))]
6595 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6596 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6597 "sub{b}\t{%1, %0|%0, %1}"
6598 [(set_attr "type" "alu1")
6599 (set_attr "mode" "QI")])
6600
6601(define_insn "*subqi_2"
6602 [(set (reg 17)
6603 (compare
6604 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6605 (match_operand:QI 2 "general_operand" "qi,qm"))
6606 (const_int 0)))
6607 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6608 (minus:HI (match_dup 1) (match_dup 2)))]

--- 622 unchanged lines hidden (view full) ---

7231 (clobber (reg:CC 17))])
7232 (parallel [(set (match_dup 0)
7233 (div:DI (reg:DI 0) (match_dup 2)))
7234 (set (match_dup 3)
7235 (mod:DI (reg:DI 0) (match_dup 2)))
7236 (use (match_dup 3))
7237 (clobber (reg:CC 17))])]
7238{
7825 /* Avoid use of cltd in favour of a mov+shift. */
7239 /* Avoid use of cltd in favor of a mov+shift. */
7240 if (!TARGET_USE_CLTD && !optimize_size)
7241 {
7242 if (true_regnum (operands[1]))
7243 emit_move_insn (operands[0], operands[1]);
7244 else
7245 emit_move_insn (operands[3], operands[1]);
7246 operands[4] = operands[3];
7247 }

--- 68 unchanged lines hidden (view full) ---

7316 (clobber (reg:CC 17))])
7317 (parallel [(set (match_dup 0)
7318 (div:SI (reg:SI 0) (match_dup 2)))
7319 (set (match_dup 3)
7320 (mod:SI (reg:SI 0) (match_dup 2)))
7321 (use (match_dup 3))
7322 (clobber (reg:CC 17))])]
7323{
7910 /* Avoid use of cltd in favour of a mov+shift. */
7324 /* Avoid use of cltd in favor of a mov+shift. */
7325 if (!TARGET_USE_CLTD && !optimize_size)
7326 {
7327 if (true_regnum (operands[1]))
7328 emit_move_insn (operands[0], operands[1]);
7329 else
7330 emit_move_insn (operands[3], operands[1]);
7331 operands[4] = operands[3];
7332 }

--- 256 unchanged lines hidden (view full) ---

7589 (compare
7590 (and:SI
7591 (zero_extract:SI
7592 (match_operand 0 "ext_register_operand" "Q")
7593 (const_int 8)
7594 (const_int 8))
7595 (match_operand 1 "const_int_operand" "n"))
7596 (const_int 0)))]
8183 "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff
8184 && ix86_match_ccmode (insn, CCNOmode)"
7597 "ix86_match_ccmode (insn, CCNOmode)"
7598 "test{b}\t{%1, %h0|%h0, %1}"
7599 [(set_attr "type" "test")
7600 (set_attr "mode" "QI")
7601 (set_attr "length_immediate" "1")
7602 (set_attr "pent_pair" "np")])
7603
7604(define_insn "*testqi_ext_1"
7605 [(set (reg 17)

--- 121 unchanged lines hidden (view full) ---

7727 /* Small HImode tests can be converted to QImode. */
7728 mode = QImode;
7729 operands[0] = gen_lowpart (QImode, operands[0]);
7730 }
7731
7732 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
7733 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
7734
8322 operands[3] = gen_rtx_AND (mode, operands[0],
8323 GEN_INT (trunc_int_for_mode (mask, mode)));
7735 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
7736})
7737
7738;; Convert HImode/SImode test instructions with immediate to QImode ones.
7739;; i386 does not allow to encode test with 8bit sign extended immediate, so
7740;; this is relatively important trick.
7741;; Do the converison only post-reload to avoid limiting of the register class
7742;; to QI regs.
7743(define_split
7744 [(set (reg 17)
7745 (compare
7746 (and (match_operand 0 "register_operand" "")
7747 (match_operand 1 "const_int_operand" ""))
7748 (const_int 0)))]
7749 "reload_completed
7750 && QI_REG_P (operands[0])
7751 && ((ix86_match_ccmode (insn, CCZmode)
7752 && !(INTVAL (operands[1]) & ~(255 << 8)))
7753 || (ix86_match_ccmode (insn, CCNOmode)
7754 && !(INTVAL (operands[1]) & ~(127 << 8))))
7755 && GET_MODE (operands[0]) != QImode"
7756 [(set (reg:CCNO 17)
7757 (compare:CCNO
7758 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
7759 (match_dup 1))
7760 (const_int 0)))]
7761 "operands[0] = gen_lowpart (SImode, operands[0]);
7762 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
7763
7764(define_split
7765 [(set (reg 17)
7766 (compare
7767 (and (match_operand 0 "nonimmediate_operand" "")
7768 (match_operand 1 "const_int_operand" ""))
7769 (const_int 0)))]
7770 "reload_completed
7771 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
7772 && ((ix86_match_ccmode (insn, CCZmode)
7773 && !(INTVAL (operands[1]) & ~255))
7774 || (ix86_match_ccmode (insn, CCNOmode)
7775 && !(INTVAL (operands[1]) & ~127)))
7776 && GET_MODE (operands[0]) != QImode"
7777 [(set (reg:CCNO 17)
7778 (compare:CCNO
7779 (and:QI (match_dup 0)
7780 (match_dup 1))
7781 (const_int 0)))]
7782 "operands[0] = gen_lowpart (QImode, operands[0]);
7783 operands[1] = gen_lowpart (QImode, operands[1]);")
7784
7785
7786;; %%% This used to optimize known byte-wide and operations to memory,
7787;; and sometimes to QImode registers. If this is considered useful,
7788;; it should be done with splitters.
7789
7790(define_expand "anddi3"
7791 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7792 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
7793 (match_operand:DI 2 "x86_64_szext_general_operand" "")))

--- 106 unchanged lines hidden (view full) ---

7900 (set_attr "length_immediate" "*,*,0")
7901 (set_attr "mode" "SI")])
7902
7903(define_split
7904 [(set (match_operand 0 "register_operand" "")
7905 (and (match_dup 0)
7906 (const_int -65536)))
7907 (clobber (reg:CC 17))]
8448 "optimize_size"
7908 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
7909 [(set (strict_low_part (match_dup 1)) (const_int 0))]
7910 "operands[1] = gen_lowpart (HImode, operands[0]);")
7911
7912(define_split
7913 [(set (match_operand 0 "ext_register_operand" "")
7914 (and (match_dup 0)
7915 (const_int -256)))
7916 (clobber (reg:CC 17))]

--- 129 unchanged lines hidden (view full) ---

8046 [(set_attr "type" "alu")
8047 (set_attr "mode" "QI,QI,SI")])
8048
8049(define_insn "*andqi_1_slp"
8050 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8051 (and:QI (match_dup 0)
8052 (match_operand:QI 1 "general_operand" "qi,qmi")))
8053 (clobber (reg:CC 17))]
8594 ""
8054 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8055 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8056 "and{b}\t{%1, %0|%0, %1}"
8057 [(set_attr "type" "alu1")
8058 (set_attr "mode" "QI")])
8059
8060(define_insn "*andqi_2"
8061 [(set (reg 17)
8062 (compare (and:QI
8063 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")

--- 19 unchanged lines hidden (view full) ---

8083(define_insn "*andqi_2_slp"
8084 [(set (reg 17)
8085 (compare (and:QI
8086 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8087 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8088 (const_int 0)))
8089 (set (strict_low_part (match_dup 0))
8090 (and:QI (match_dup 0) (match_dup 1)))]
8630 "ix86_match_ccmode (insn, CCNOmode)"
8091 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8092 && ix86_match_ccmode (insn, CCNOmode)
8093 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8094 "and{b}\t{%1, %0|%0, %1}"
8095 [(set_attr "type" "alu1")
8096 (set_attr "mode" "QI")])
8097
8098;; ??? A bug in recog prevents it from recognizing a const_int as an
8099;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8100;; for a QImode operand, which of course failed.
8101
8102(define_insn "andqi_ext_0"
8103 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8104 (const_int 8)
8105 (const_int 8))
8106 (and:SI
8107 (zero_extract:SI
8108 (match_operand 1 "ext_register_operand" "0")
8109 (const_int 8)
8110 (const_int 8))
8111 (match_operand 2 "const_int_operand" "n")))
8112 (clobber (reg:CC 17))]
8650 "(unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8113 ""
8114 "and{b}\t{%2, %h0|%h0, %2}"
8115 [(set_attr "type" "alu")
8116 (set_attr "length_immediate" "1")
8117 (set_attr "mode" "QI")])
8118
8119;; Generated by peephole translating test to and. This shows up
8120;; often in fp comparisons.
8121

--- 11 unchanged lines hidden (view full) ---

8133 (const_int 8)
8134 (const_int 8))
8135 (and:SI
8136 (zero_extract:SI
8137 (match_dup 1)
8138 (const_int 8)
8139 (const_int 8))
8140 (match_dup 2)))]
8678 "ix86_match_ccmode (insn, CCNOmode)
8679 && (unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8141 "ix86_match_ccmode (insn, CCNOmode)"
8142 "and{b}\t{%2, %h0|%h0, %2}"
8143 [(set_attr "type" "alu")
8144 (set_attr "length_immediate" "1")
8145 (set_attr "mode" "QI")])
8146
8147(define_insn "*andqi_ext_1"
8148 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8149 (const_int 8)

--- 44 unchanged lines hidden (view full) ---

8194 (const_int 8)
8195 (const_int 8))))
8196 (clobber (reg:CC 17))]
8197 ""
8198 "and{b}\t{%h2, %h0|%h0, %h2}"
8199 [(set_attr "type" "alu")
8200 (set_attr "length_immediate" "0")
8201 (set_attr "mode" "QI")])
8202
8203;; Convert wide AND instructions with immediate operand to shorter QImode
8204;; equivalents when possible.
8205;; Don't do the splitting with memory operands, since it intoduces risc
8206;; of memory mismatch stalls. We may want to do the splitting for optimizing
8207;; for size, but that can (should?) be handled by generic code instead.
8208(define_split
8209 [(set (match_operand 0 "register_operand" "")
8210 (and (match_operand 1 "register_operand" "")
8211 (match_operand 2 "const_int_operand" "")))
8212 (clobber (reg:CC 17))]
8213 "reload_completed
8214 && QI_REG_P (operands[0])
8215 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8216 && !(~INTVAL (operands[2]) & ~(255 << 8))
8217 && GET_MODE (operands[0]) != QImode"
8218 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8219 (and:SI (zero_extract:SI (match_dup 1)
8220 (const_int 8) (const_int 8))
8221 (match_dup 2)))
8222 (clobber (reg:CC 17))])]
8223 "operands[0] = gen_lowpart (SImode, operands[0]);
8224 operands[1] = gen_lowpart (SImode, operands[1]);
8225 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8226
8227;; Since AND can be encoded with sign extended immediate, this is only
8228;; profitable when 7th bit is not set.
8229(define_split
8230 [(set (match_operand 0 "register_operand" "")
8231 (and (match_operand 1 "general_operand" "")
8232 (match_operand 2 "const_int_operand" "")))
8233 (clobber (reg:CC 17))]
8234 "reload_completed
8235 && ANY_QI_REG_P (operands[0])
8236 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8237 && !(~INTVAL (operands[2]) & ~255)
8238 && !(INTVAL (operands[2]) & 128)
8239 && GET_MODE (operands[0]) != QImode"
8240 [(parallel [(set (strict_low_part (match_dup 0))
8241 (and:QI (match_dup 1)
8242 (match_dup 2)))
8243 (clobber (reg:CC 17))])]
8244 "operands[0] = gen_lowpart (QImode, operands[0]);
8245 operands[1] = gen_lowpart (QImode, operands[1]);
8246 operands[2] = gen_lowpart (QImode, operands[2]);")
8247
8248;; Logical inclusive OR instructions
8249
8250;; %%% This used to optimize known byte-wide and operations to memory.
8251;; If this is considered useful, it should be done with splitters.
8252
8253(define_expand "iordi3"
8254 [(set (match_operand:DI 0 "nonimmediate_operand" "")

--- 200 unchanged lines hidden (view full) ---

8455 [(set_attr "type" "alu")
8456 (set_attr "mode" "QI,QI,SI")])
8457
8458(define_insn "*iorqi_1_slp"
8459 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8460 (ior:QI (match_dup 0)
8461 (match_operand:QI 1 "general_operand" "qmi,qi")))
8462 (clobber (reg:CC 17))]
8956 ""
8463 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8464 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8465 "or{b}\t{%1, %0|%0, %1}"
8466 [(set_attr "type" "alu1")
8467 (set_attr "mode" "QI")])
8468
8469(define_insn "*iorqi_2"
8470 [(set (reg 17)
8471 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8472 (match_operand:QI 2 "general_operand" "qim,qi"))

--- 8 unchanged lines hidden (view full) ---

8481
8482(define_insn "*iorqi_2_slp"
8483 [(set (reg 17)
8484 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8485 (match_operand:QI 1 "general_operand" "qim,qi"))
8486 (const_int 0)))
8487 (set (strict_low_part (match_dup 0))
8488 (ior:QI (match_dup 0) (match_dup 1)))]
8981 "ix86_match_ccmode (insn, CCNOmode)"
8489 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8490 && ix86_match_ccmode (insn, CCNOmode)
8491 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8492 "or{b}\t{%1, %0|%0, %1}"
8493 [(set_attr "type" "alu1")
8494 (set_attr "mode" "QI")])
8495
8496(define_insn "*iorqi_3"
8497 [(set (reg 17)
8498 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8499 (match_operand:QI 2 "general_operand" "qim"))
8500 (const_int 0)))
8501 (clobber (match_scratch:QI 0 "=q"))]
8502 "ix86_match_ccmode (insn, CCNOmode)
8503 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8504 "or{b}\t{%2, %0|%0, %2}"
8505 [(set_attr "type" "alu")
8506 (set_attr "mode" "QI")])
8507
8508(define_insn "iorqi_ext_0"
8509 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8510 (const_int 8)
8511 (const_int 8))
8512 (ior:SI
8513 (zero_extract:SI
8514 (match_operand 1 "ext_register_operand" "0")
8515 (const_int 8)
8516 (const_int 8))
8517 (match_operand 2 "const_int_operand" "n")))
8518 (clobber (reg:CC 17))]
8519 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8520 "or{b}\t{%2, %h0|%h0, %2}"
8521 [(set_attr "type" "alu")
8522 (set_attr "length_immediate" "1")
8523 (set_attr "mode" "QI")])
8524
8525(define_insn "*iorqi_ext_1"
8526 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8527 (const_int 8)
8528 (const_int 8))
8529 (ior:SI
8530 (zero_extract:SI
8531 (match_operand 1 "ext_register_operand" "0")
8532 (const_int 8)
8533 (const_int 8))
8534 (zero_extend:SI
8535 (match_operand:QI 2 "general_operand" "Qm"))))
8536 (clobber (reg:CC 17))]
8537 "!TARGET_64BIT
8538 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8539 "or{b}\t{%2, %h0|%h0, %2}"
8540 [(set_attr "type" "alu")
8541 (set_attr "length_immediate" "0")
8542 (set_attr "mode" "QI")])
8543
8544(define_insn "*iorqi_ext_1_rex64"
8545 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8546 (const_int 8)
8547 (const_int 8))
8548 (ior:SI
8549 (zero_extract:SI
8550 (match_operand 1 "ext_register_operand" "0")
8551 (const_int 8)
8552 (const_int 8))
8553 (zero_extend:SI
8554 (match_operand 2 "ext_register_operand" "Q"))))
8555 (clobber (reg:CC 17))]
8556 "TARGET_64BIT
8557 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8558 "or{b}\t{%2, %h0|%h0, %2}"
8559 [(set_attr "type" "alu")
8560 (set_attr "length_immediate" "0")
8561 (set_attr "mode" "QI")])
8562
8563(define_insn "*iorqi_ext_2"
8564 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8565 (const_int 8)
8566 (const_int 8))
8567 (ior:SI
8568 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8569 (const_int 8)
8570 (const_int 8))
8571 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8572 (const_int 8)
8573 (const_int 8))))
8574 (clobber (reg:CC 17))]
8575 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8576 "ior{b}\t{%h2, %h0|%h0, %h2}"
8577 [(set_attr "type" "alu")
8578 (set_attr "length_immediate" "0")
8579 (set_attr "mode" "QI")])
8580
8581(define_split
8582 [(set (match_operand 0 "register_operand" "")
8583 (ior (match_operand 1 "register_operand" "")
8584 (match_operand 2 "const_int_operand" "")))
8585 (clobber (reg:CC 17))]
8586 "reload_completed
8587 && QI_REG_P (operands[0])
8588 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8589 && !(INTVAL (operands[2]) & ~(255 << 8))
8590 && GET_MODE (operands[0]) != QImode"
8591 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8592 (ior:SI (zero_extract:SI (match_dup 1)
8593 (const_int 8) (const_int 8))
8594 (match_dup 2)))
8595 (clobber (reg:CC 17))])]
8596 "operands[0] = gen_lowpart (SImode, operands[0]);
8597 operands[1] = gen_lowpart (SImode, operands[1]);
8598 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8599
8600;; Since OR can be encoded with sign extended immediate, this is only
8601;; profitable when 7th bit is set.
8602(define_split
8603 [(set (match_operand 0 "register_operand" "")
8604 (ior (match_operand 1 "general_operand" "")
8605 (match_operand 2 "const_int_operand" "")))
8606 (clobber (reg:CC 17))]
8607 "reload_completed
8608 && ANY_QI_REG_P (operands[0])
8609 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8610 && !(INTVAL (operands[2]) & ~255)
8611 && (INTVAL (operands[2]) & 128)
8612 && GET_MODE (operands[0]) != QImode"
8613 [(parallel [(set (strict_low_part (match_dup 0))
8614 (ior:QI (match_dup 1)
8615 (match_dup 2)))
8616 (clobber (reg:CC 17))])]
8617 "operands[0] = gen_lowpart (QImode, operands[0]);
8618 operands[1] = gen_lowpart (QImode, operands[1]);
8619 operands[2] = gen_lowpart (QImode, operands[2]);")
8620
8621;; Logical XOR instructions
8622
8623;; %%% This used to optimize known byte-wide and operations to memory.
8624;; If this is considered useful, it should be done with splitters.
8625
8626(define_expand "xordi3"
8627 [(set (match_operand:DI 0 "nonimmediate_operand" "")

--- 199 unchanged lines hidden (view full) ---

8827 "ix86_binary_operator_ok (XOR, QImode, operands)"
8828 "@
8829 xor{b}\t{%2, %0|%0, %2}
8830 xor{b}\t{%2, %0|%0, %2}
8831 xor{l}\t{%k2, %k0|%k0, %k2}"
8832 [(set_attr "type" "alu")
8833 (set_attr "mode" "QI,QI,SI")])
8834
8835(define_insn "*xorqi_1_slp"
8836 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8837 (xor:QI (match_dup 0)
8838 (match_operand:QI 1 "general_operand" "qi,qmi")))
8839 (clobber (reg:CC 17))]
8840 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8841 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8842 "xor{b}\t{%1, %0|%0, %1}"
8843 [(set_attr "type" "alu1")
8844 (set_attr "mode" "QI")])
8845
8846(define_insn "xorqi_ext_0"
8847 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8848 (const_int 8)
8849 (const_int 8))
8850 (xor:SI
8851 (zero_extract:SI
8852 (match_operand 1 "ext_register_operand" "0")
8853 (const_int 8)
8854 (const_int 8))
8855 (match_operand 2 "const_int_operand" "n")))
8856 (clobber (reg:CC 17))]
8857 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8858 "xor{b}\t{%2, %h0|%h0, %2}"
8859 [(set_attr "type" "alu")
8860 (set_attr "length_immediate" "1")
8861 (set_attr "mode" "QI")])
8862
8863(define_insn "*xorqi_ext_1"
8864 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8865 (const_int 8)
8866 (const_int 8))
8867 (xor:SI
8868 (zero_extract:SI
8869 (match_operand 1 "ext_register_operand" "0")
8870 (const_int 8)
8871 (const_int 8))
8872 (zero_extend:SI
8873 (match_operand:QI 2 "general_operand" "Qm"))))
8874 (clobber (reg:CC 17))]
8875 "!TARGET_64BIT
8876 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8877 "xor{b}\t{%2, %h0|%h0, %2}"
8878 [(set_attr "type" "alu")
8879 (set_attr "length_immediate" "0")
8880 (set_attr "mode" "QI")])
8881
8882(define_insn "*xorqi_ext_1_rex64"
8883 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8884 (const_int 8)
8885 (const_int 8))
8886 (xor:SI
8887 (zero_extract:SI
8888 (match_operand 1 "ext_register_operand" "0")
8889 (const_int 8)
8890 (const_int 8))
8891 (zero_extend:SI
8892 (match_operand 2 "ext_register_operand" "Q"))))
8893 (clobber (reg:CC 17))]
8894 "TARGET_64BIT
8895 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8896 "xor{b}\t{%2, %h0|%h0, %2}"
8897 [(set_attr "type" "alu")
8898 (set_attr "length_immediate" "0")
8899 (set_attr "mode" "QI")])
8900
8901(define_insn "*xorqi_ext_2"
8902 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8903 (const_int 8)
8904 (const_int 8))
8905 (xor:SI
8906 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8907 (const_int 8)
8908 (const_int 8))
8909 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8910 (const_int 8)
8911 (const_int 8))))
8912 (clobber (reg:CC 17))]
9225 ""
8913 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8914 "xor{b}\t{%h2, %h0|%h0, %h2}"
8915 [(set_attr "type" "alu")
8916 (set_attr "length_immediate" "0")
8917 (set_attr "mode" "QI")])
8918
8919(define_insn "*xorqi_cc_1"
8920 [(set (reg 17)
8921 (compare
8922 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8923 (match_operand:QI 2 "general_operand" "qim,qi"))
8924 (const_int 0)))
8925 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8926 (xor:QI (match_dup 1) (match_dup 2)))]
8927 "ix86_match_ccmode (insn, CCNOmode)
8928 && ix86_binary_operator_ok (XOR, QImode, operands)"
8929 "xor{b}\t{%2, %0|%0, %2}"
8930 [(set_attr "type" "alu")
8931 (set_attr "mode" "QI")])
8932
8933(define_insn "*xorqi_2_slp"
8934 [(set (reg 17)
8935 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8936 (match_operand:QI 1 "general_operand" "qim,qi"))
8937 (const_int 0)))
8938 (set (strict_low_part (match_dup 0))
8939 (xor:QI (match_dup 0) (match_dup 1)))]
8940 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8941 && ix86_match_ccmode (insn, CCNOmode)
8942 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8943 "xor{b}\t{%1, %0|%0, %1}"
8944 [(set_attr "type" "alu1")
8945 (set_attr "mode" "QI")])
8946
8947(define_insn "*xorqi_cc_2"
8948 [(set (reg 17)
8949 (compare
8950 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8951 (match_operand:QI 2 "general_operand" "qim"))
8952 (const_int 0)))
8953 (clobber (match_scratch:QI 0 "=q"))]
8954 "ix86_match_ccmode (insn, CCNOmode)

--- 58 unchanged lines hidden (view full) ---

9013 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9014 (const_int 8)
9015 (const_int 8))
9016 (xor:SI
9017 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9018 (match_dup 2)))])]
9019 ""
9020 "")
9021
9022(define_split
9023 [(set (match_operand 0 "register_operand" "")
9024 (xor (match_operand 1 "register_operand" "")
9025 (match_operand 2 "const_int_operand" "")))
9026 (clobber (reg:CC 17))]
9027 "reload_completed
9028 && QI_REG_P (operands[0])
9029 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9030 && !(INTVAL (operands[2]) & ~(255 << 8))
9031 && GET_MODE (operands[0]) != QImode"
9032 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9033 (xor:SI (zero_extract:SI (match_dup 1)
9034 (const_int 8) (const_int 8))
9035 (match_dup 2)))
9036 (clobber (reg:CC 17))])]
9037 "operands[0] = gen_lowpart (SImode, operands[0]);
9038 operands[1] = gen_lowpart (SImode, operands[1]);
9039 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9040
9041;; Since XOR can be encoded with sign extended immediate, this is only
9042;; profitable when 7th bit is set.
9043(define_split
9044 [(set (match_operand 0 "register_operand" "")
9045 (xor (match_operand 1 "general_operand" "")
9046 (match_operand 2 "const_int_operand" "")))
9047 (clobber (reg:CC 17))]
9048 "reload_completed
9049 && ANY_QI_REG_P (operands[0])
9050 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9051 && !(INTVAL (operands[2]) & ~255)
9052 && (INTVAL (operands[2]) & 128)
9053 && GET_MODE (operands[0]) != QImode"
9054 [(parallel [(set (strict_low_part (match_dup 0))
9055 (xor:QI (match_dup 1)
9056 (match_dup 2)))
9057 (clobber (reg:CC 17))])]
9058 "operands[0] = gen_lowpart (QImode, operands[0]);
9059 operands[1] = gen_lowpart (QImode, operands[1]);
9060 operands[2] = gen_lowpart (QImode, operands[2]);")
9061
9062;; Negation instructions
9063
9064(define_expand "negdi2"
9065 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9066 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9067 (clobber (reg:CC 17))])]
9068 ""

--- 187 unchanged lines hidden (view full) ---

9256 in register. */
9257 rtx reg = gen_reg_rtx (SFmode);
9258 rtx dest = operands[0];
9259
9260 operands[1] = force_reg (SFmode, operands[1]);
9261 operands[0] = force_reg (SFmode, operands[0]);
9262 emit_move_insn (reg,
9263 gen_lowpart (SFmode,
9522 GEN_INT (trunc_int_for_mode (0x80000000,
9523 SImode))));
9264 gen_int_mode (0x80000000, SImode)));
9265 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9266 if (dest != operands[0])
9267 emit_move_insn (dest, operands[0]);
9268 }
9269 DONE;
9270 }
9271 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9272

--- 62 unchanged lines hidden (view full) ---

9335 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9336 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9337 (clobber (reg:CC 17))]
9338 "TARGET_80387 && !TARGET_SSE
9339 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9340 "#")
9341
9342(define_split
9602 [(set (match_operand:SF 0 "register_operand" "")
9343 [(set (match_operand:SF 0 "fp_register_operand" "")
9344 (neg:SF (match_operand:SF 1 "register_operand" "")))
9345 (clobber (reg:CC 17))]
9605 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9346 "TARGET_80387 && reload_completed"
9347 [(set (match_dup 0)
9348 (neg:SF (match_dup 1)))]
9349 "")
9350
9351(define_split
9611 [(set (match_operand:SF 0 "register_operand" "")
9352 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
9353 (neg:SF (match_operand:SF 1 "register_operand" "")))
9354 (clobber (reg:CC 17))]
9614 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9355 "TARGET_80387 && reload_completed"
9356 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9357 (clobber (reg:CC 17))])]
9617 "operands[1] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
9358 "operands[1] = gen_int_mode (0x80000000, SImode);
9359 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9360
9361(define_split
9362 [(set (match_operand 0 "memory_operand" "")
9363 (neg (match_operand 1 "memory_operand" "")))
9364 (clobber (reg:CC 17))]
9365 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9366 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9367 (clobber (reg:CC 17))])]
9368{
9369 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9370
9371 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9372 if (size >= 12)
9373 size = 10;
9374 operands[0] = adjust_address (operands[0], QImode, size - 1);
9634 operands[1] = GEN_INT (trunc_int_for_mode (0x80, QImode));
9375 operands[1] = gen_int_mode (0x80, QImode);
9376})
9377
9378(define_expand "negdf2"
9379 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9380 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9381 (clobber (reg:CC 17))])]
9382 "TARGET_80387"
9383 "if (TARGET_SSE2)
9384 {
9385 /* In case operand is in memory, we will not use SSE. */
9386 if (memory_operand (operands[0], VOIDmode)
9387 && rtx_equal_p (operands[0], operands[1]))
9388 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9389 else
9390 {
9391 /* Using SSE is tricky, since we need bitwise negation of -0
9392 in register. */
9393 rtx reg = gen_reg_rtx (DFmode);
9394#if HOST_BITS_PER_WIDE_INT >= 64
9654 rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63,
9655 DImode));
9395 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
9396#else
9397 rtx imm = immed_double_const (0, 0x80000000, DImode);
9398#endif
9399 rtx dest = operands[0];
9400
9401 operands[1] = force_reg (DFmode, operands[1]);
9402 operands[0] = force_reg (DFmode, operands[0]);
9403 emit_move_insn (reg, gen_lowpart (DFmode, imm));

--- 19 unchanged lines hidden (view full) ---

9423 (clobber (reg:CC 17))]
9424 "!TARGET_64BIT && TARGET_SSE2
9425 && (reload_in_progress || reload_completed
9426 || (register_operand (operands[0], VOIDmode)
9427 && register_operand (operands[1], VOIDmode)))"
9428 "#")
9429
9430(define_insn "*negdf2_ifs_rex64"
9691 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,fm#Yr,r#Yf")
9692 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9693 (use (match_operand:DF 2 "general_operand" "Y,0,*g#Yr,*rm"))
9431 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,fm#Y")
9432 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#f,0")))
9433 (use (match_operand:DF 2 "general_operand" "Y,0,*g#Y*r"))
9434 (clobber (reg:CC 17))]
9435 "TARGET_64BIT && TARGET_SSE2
9436 && (reload_in_progress || reload_completed
9437 || (register_operand (operands[0], VOIDmode)
9438 && register_operand (operands[1], VOIDmode)))"
9439 "#")
9440
9441(define_split

--- 68 unchanged lines hidden (view full) ---

9510 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9511 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9512 (clobber (reg:CC 17))]
9513 "TARGET_64BIT && TARGET_80387
9514 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9515 "#")
9516
9517(define_split
9778 [(set (match_operand:DF 0 "register_operand" "")
9518 [(set (match_operand:DF 0 "fp_register_operand" "")
9519 (neg:DF (match_operand:DF 1 "register_operand" "")))
9520 (clobber (reg:CC 17))]
9781 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9521 "TARGET_80387 && reload_completed"
9522 [(set (match_dup 0)
9523 (neg:DF (match_dup 1)))]
9524 "")
9525
9526(define_split
9787 [(set (match_operand:DF 0 "register_operand" "")
9527 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
9528 (neg:DF (match_operand:DF 1 "register_operand" "")))
9529 (clobber (reg:CC 17))]
9790 "!TARGET_64BIT && TARGET_80387 && reload_completed
9791 && !FP_REGNO_P (REGNO (operands[0]))"
9530 "!TARGET_64BIT && TARGET_80387 && reload_completed"
9531 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9532 (clobber (reg:CC 17))])]
9794 "operands[4] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
9533 "operands[4] = gen_int_mode (0x80000000, SImode);
9534 split_di (operands+0, 1, operands+2, operands+3);")
9535
9536(define_expand "negxf2"
9537 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9538 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9539 (clobber (reg:CC 17))])]
9540 "!TARGET_64BIT && TARGET_80387"
9541 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")

--- 12 unchanged lines hidden (view full) ---

9554 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9555 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9556 (clobber (reg:CC 17))]
9557 "!TARGET_64BIT && TARGET_80387
9558 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9559 "#")
9560
9561(define_split
9823 [(set (match_operand:XF 0 "register_operand" "")
9562 [(set (match_operand:XF 0 "fp_register_operand" "")
9563 (neg:XF (match_operand:XF 1 "register_operand" "")))
9564 (clobber (reg:CC 17))]
9826 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9565 "TARGET_80387 && reload_completed"
9566 [(set (match_dup 0)
9567 (neg:XF (match_dup 1)))]
9568 "")
9569
9570(define_split
9832 [(set (match_operand:XF 0 "register_operand" "")
9571 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
9572 (neg:XF (match_operand:XF 1 "register_operand" "")))
9573 (clobber (reg:CC 17))]
9835 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9574 "TARGET_80387 && reload_completed"
9575 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9576 (clobber (reg:CC 17))])]
9577 "operands[1] = GEN_INT (0x8000);
9578 operands[0] = gen_rtx_REG (SImode,
9579 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9580
9581;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9582;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9583;; to itself.
9584(define_insn "*negtf2_if"
9585 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
9586 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
9587 (clobber (reg:CC 17))]
9588 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
9589 "#")
9590
9591(define_split
9853 [(set (match_operand:TF 0 "register_operand" "")
9592 [(set (match_operand:TF 0 "fp_register_operand" "")
9593 (neg:TF (match_operand:TF 1 "register_operand" "")))
9594 (clobber (reg:CC 17))]
9856 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9595 "TARGET_80387 && reload_completed"
9596 [(set (match_dup 0)
9597 (neg:TF (match_dup 1)))]
9598 "")
9599
9600(define_split
9862 [(set (match_operand:TF 0 "register_operand" "")
9601 [(set (match_operand:TF 0 "register_and_not_fp_reg_operand" "")
9602 (neg:TF (match_operand:TF 1 "register_operand" "")))
9603 (clobber (reg:CC 17))]
9865 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9604 "TARGET_80387 && reload_completed"
9605 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9606 (clobber (reg:CC 17))])]
9607 "operands[1] = GEN_INT (0x8000);
9608 operands[0] = gen_rtx_REG (SImode,
9609 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9610
9611;; Conditionize these after reload. If they matches before reload, we
9612;; lose the clobber and ability to use integer instructions.

--- 103 unchanged lines hidden (view full) ---

9716 in register. */
9717 rtx reg = gen_reg_rtx (SFmode);
9718 rtx dest = operands[0];
9719
9720 operands[1] = force_reg (SFmode, operands[1]);
9721 operands[0] = force_reg (SFmode, operands[0]);
9722 emit_move_insn (reg,
9723 gen_lowpart (SFmode,
9985 GEN_INT (trunc_int_for_mode (0x80000000,
9986 SImode))));
9724 gen_int_mode (0x80000000, SImode)));
9725 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
9726 if (dest != operands[0])
9727 emit_move_insn (dest, operands[0]);
9728 }
9729 DONE;
9730 }
9731 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
9732

--- 51 unchanged lines hidden (view full) ---

9784(define_insn "*abssf2_if"
9785 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9786 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9787 (clobber (reg:CC 17))]
9788 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
9789 "#")
9790
9791(define_split
10054 [(set (match_operand:SF 0 "register_operand" "")
9792 [(set (match_operand:SF 0 "fp_register_operand" "")
9793 (abs:SF (match_operand:SF 1 "register_operand" "")))
9794 (clobber (reg:CC 17))]
10057 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0]))"
9795 "TARGET_80387"
9796 [(set (match_dup 0)
9797 (abs:SF (match_dup 1)))]
9798 "")
9799
9800(define_split
10063 [(set (match_operand:SF 0 "register_operand" "")
9801 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
9802 (abs:SF (match_operand:SF 1 "register_operand" "")))
9803 (clobber (reg:CC 17))]
10066 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9804 "TARGET_80387 && reload_completed"
9805 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
9806 (clobber (reg:CC 17))])]
10069 "operands[1] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
9807 "operands[1] = gen_int_mode (~0x80000000, SImode);
9808 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9809
9810(define_split
9811 [(set (match_operand 0 "memory_operand" "")
9812 (abs (match_operand 1 "memory_operand" "")))
9813 (clobber (reg:CC 17))]
9814 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9815 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
9816 (clobber (reg:CC 17))])]
9817{
9818 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9819
9820 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9821 if (size >= 12)
9822 size = 10;
9823 operands[0] = adjust_address (operands[0], QImode, size - 1);
10086 operands[1] = GEN_INT (trunc_int_for_mode (~0x80, QImode));
9824 operands[1] = gen_int_mode (~0x80, QImode);
9825})
9826
9827(define_expand "absdf2"
9828 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9829 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9830 (clobber (reg:CC 17))])]
9831 "TARGET_80387"
9832 "if (TARGET_SSE2)
9833 {
9834 /* In case operand is in memory, we will not use SSE. */
9835 if (memory_operand (operands[0], VOIDmode)
9836 && rtx_equal_p (operands[0], operands[1]))
9837 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
9838 else
9839 {
9840 /* Using SSE is tricky, since we need bitwise negation of -0
9841 in register. */
9842 rtx reg = gen_reg_rtx (DFmode);
9843#if HOST_BITS_PER_WIDE_INT >= 64
10106 rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63,
10107 DImode));
9844 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
9845#else
9846 rtx imm = immed_double_const (0, 0x80000000, DImode);
9847#endif
9848 rtx dest = operands[0];
9849
9850 operands[1] = force_reg (DFmode, operands[1]);
9851 operands[0] = force_reg (DFmode, operands[0]);
9852 emit_move_insn (reg, gen_lowpart (DFmode, imm));

--- 84 unchanged lines hidden (view full) ---

9937 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9938 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9939 (clobber (reg:CC 17))]
9940 "TARGET_64BIT && TARGET_80387
9941 && ix86_unary_operator_ok (ABS, DFmode, operands)"
9942 "#")
9943
9944(define_split
10208 [(set (match_operand:DF 0 "register_operand" "")
9945 [(set (match_operand:DF 0 "fp_register_operand" "")
9946 (abs:DF (match_operand:DF 1 "register_operand" "")))
9947 (clobber (reg:CC 17))]
10211 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9948 "TARGET_80387 && reload_completed"
9949 [(set (match_dup 0)
9950 (abs:DF (match_dup 1)))]
9951 "")
9952
9953(define_split
10217 [(set (match_operand:DF 0 "register_operand" "")
9954 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
9955 (abs:DF (match_operand:DF 1 "register_operand" "")))
9956 (clobber (reg:CC 17))]
10220 "!TARGET_64BIT && TARGET_80387 && reload_completed &&
10221 !FP_REGNO_P (REGNO (operands[0]))"
9957 "!TARGET_64BIT && TARGET_80387 && reload_completed"
9958 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
9959 (clobber (reg:CC 17))])]
10224 "operands[4] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
9960 "operands[4] = gen_int_mode (~0x80000000, SImode);
9961 split_di (operands+0, 1, operands+2, operands+3);")
9962
9963(define_expand "absxf2"
9964 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9965 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9966 (clobber (reg:CC 17))])]
9967 "!TARGET_64BIT && TARGET_80387"
9968 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")

--- 12 unchanged lines hidden (view full) ---

9981 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9982 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9983 (clobber (reg:CC 17))]
9984 "!TARGET_64BIT && TARGET_80387
9985 && ix86_unary_operator_ok (ABS, XFmode, operands)"
9986 "#")
9987
9988(define_split
10253 [(set (match_operand:XF 0 "register_operand" "")
9989 [(set (match_operand:XF 0 "fp_register_operand" "")
9990 (abs:XF (match_operand:XF 1 "register_operand" "")))
9991 (clobber (reg:CC 17))]
10256 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9992 "TARGET_80387 && reload_completed"
9993 [(set (match_dup 0)
9994 (abs:XF (match_dup 1)))]
9995 "")
9996
9997(define_split
10262 [(set (match_operand:XF 0 "register_operand" "")
9998 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
9999 (abs:XF (match_operand:XF 1 "register_operand" "")))
10000 (clobber (reg:CC 17))]
10265 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
10001 "TARGET_80387 && reload_completed"
10002 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10003 (clobber (reg:CC 17))])]
10004 "operands[1] = GEN_INT (~0x8000);
10005 operands[0] = gen_rtx_REG (SImode,
10006 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10007
10008(define_insn "*abstf2_if"
10009 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10010 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10011 (clobber (reg:CC 17))]
10012 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
10013 "#")
10014
10015(define_split
10280 [(set (match_operand:TF 0 "register_operand" "")
10016 [(set (match_operand:TF 0 "fp_register_operand" "")
10017 (abs:TF (match_operand:TF 1 "register_operand" "")))
10018 (clobber (reg:CC 17))]
10283 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10019 "TARGET_80387 && reload_completed"
10020 [(set (match_dup 0)
10021 (abs:TF (match_dup 1)))]
10022 "")
10023
10024(define_split
10289 [(set (match_operand:TF 0 "register_operand" "")
10025 [(set (match_operand:TF 0 "register_and_not_any_fp_reg_operand" "")
10026 (abs:TF (match_operand:TF 1 "register_operand" "")))
10027 (clobber (reg:CC 17))]
10292 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
10028 "TARGET_80387 && reload_completed"
10029 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10030 (clobber (reg:CC 17))])]
10031 "operands[1] = GEN_INT (~0x8000);
10032 operands[0] = gen_rtx_REG (SImode,
10033 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10034
10035(define_insn "*abssf2_1"
10036 [(set (match_operand:SF 0 "register_operand" "=f")

--- 337 unchanged lines hidden (view full) ---

10374 GEN_INT (1 << INTVAL (operands[2])));
10375 return "lea{q}\t{%a1, %0|%0, %a1}";
10376
10377 default:
10378 if (REG_P (operands[2]))
10379 return "sal{q}\t{%b2, %0|%0, %b2}";
10380 else if (GET_CODE (operands[2]) == CONST_INT
10381 && INTVAL (operands[2]) == 1
10646 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10382 && (TARGET_SHIFT1 || optimize_size))
10383 return "sal{q}\t%0";
10384 else
10385 return "sal{q}\t{%2, %0|%0, %2}";
10386 }
10387}
10388 [(set (attr "type")
10389 (cond [(eq_attr "alternative" "1")
10390 (const_string "lea")

--- 12 unchanged lines hidden (view full) ---

10403 (ashift:DI (match_operand:DI 1 "register_operand" "")
10404 (match_operand:QI 2 "immediate_operand" "")))
10405 (clobber (reg:CC 17))]
10406 "TARGET_64BIT && reload_completed
10407 && true_regnum (operands[0]) != true_regnum (operands[1])"
10408 [(set (match_dup 0)
10409 (mult:DI (match_dup 1)
10410 (match_dup 2)))]
10675 "operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10676 DImode));")
10411 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
10412
10413;; This pattern can't accept a variable shift count, since shifts by
10414;; zero don't affect the flags. We assume that shifts by constant
10415;; zero are optimized away.
10416(define_insn "*ashldi3_cmp_rex64"
10417 [(set (reg 17)
10418 (compare
10419 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")

--- 11 unchanged lines hidden (view full) ---

10431 abort ();
10432 return "add{q}\t{%0, %0|%0, %0}";
10433
10434 default:
10435 if (REG_P (operands[2]))
10436 return "sal{q}\t{%b2, %0|%0, %b2}";
10437 else if (GET_CODE (operands[2]) == CONST_INT
10438 && INTVAL (operands[2]) == 1
10704 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10439 && (TARGET_SHIFT1 || optimize_size))
10440 return "sal{q}\t%0";
10441 else
10442 return "sal{q}\t{%2, %0|%0, %2}";
10443 }
10444}
10445 [(set (attr "type")
10446 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10447 (const_int 0))

--- 131 unchanged lines hidden (view full) ---

10579 case TYPE_LEA:
10580 return "#";
10581
10582 default:
10583 if (REG_P (operands[2]))
10584 return "sal{l}\t{%b2, %0|%0, %b2}";
10585 else if (GET_CODE (operands[2]) == CONST_INT
10586 && INTVAL (operands[2]) == 1
10852 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10587 && (TARGET_SHIFT1 || optimize_size))
10588 return "sal{l}\t%0";
10589 else
10590 return "sal{l}\t{%2, %0|%0, %2}";
10591 }
10592}
10593 [(set (attr "type")
10594 (cond [(eq_attr "alternative" "1")
10595 (const_string "lea")

--- 4 unchanged lines hidden (view full) ---

10600 (const_string "alu")
10601 ]
10602 (const_string "ishift")))
10603 (set_attr "mode" "SI")])
10604
10605;; Convert lea to the lea pattern to avoid flags dependency.
10606(define_split
10607 [(set (match_operand 0 "register_operand" "")
10873 (ashift (match_operand 1 "register_operand" "")
10608 (ashift (match_operand 1 "index_register_operand" "")
10609 (match_operand:QI 2 "const_int_operand" "")))
10610 (clobber (reg:CC 17))]
10611 "reload_completed
10612 && true_regnum (operands[0]) != true_regnum (operands[1])"
10613 [(const_int 0)]
10614{
10615 rtx pat;
10616 operands[0] = gen_lowpart (SImode, operands[0]);
10617 operands[1] = gen_lowpart (Pmode, operands[1]);
10883 operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10884 Pmode));
10618 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10619 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10620 if (Pmode != SImode)
10621 pat = gen_rtx_SUBREG (SImode, pat, 0);
10622 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10623 DONE;
10624})
10625
10626;; Rare case of shifting RSP is handled by generating move and shift
10627(define_split
10628 [(set (match_operand 0 "register_operand" "")
10629 (ashift (match_operand 1 "register_operand" "")
10630 (match_operand:QI 2 "const_int_operand" "")))
10631 (clobber (reg:CC 17))]
10632 "reload_completed
10633 && true_regnum (operands[0]) != true_regnum (operands[1])"
10634 [(const_int 0)]
10635{
10636 rtx pat, clob;
10637 emit_move_insn (operands[1], operands[0]);
10638 pat = gen_rtx_SET (VOIDmode, operands[0],
10639 gen_rtx_ASHIFT (GET_MODE (operands[0]),
10640 operands[0], operands[2]));
10641 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10642 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
10643 DONE;
10644})
10645
10646(define_insn "*ashlsi3_1_zext"
10647 [(set (match_operand:DI 0 "register_operand" "=r,r")
10648 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
10649 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10650 (clobber (reg:CC 17))]
10651 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10652{
10653 switch (get_attr_type (insn))

--- 6 unchanged lines hidden (view full) ---

10660 case TYPE_LEA:
10661 return "#";
10662
10663 default:
10664 if (REG_P (operands[2]))
10665 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10666 else if (GET_CODE (operands[2]) == CONST_INT
10667 && INTVAL (operands[2]) == 1
10914 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10668 && (TARGET_SHIFT1 || optimize_size))
10669 return "sal{l}\t%k0";
10670 else
10671 return "sal{l}\t{%2, %k0|%k0, %2}";
10672 }
10673}
10674 [(set (attr "type")
10675 (cond [(eq_attr "alternative" "1")
10676 (const_string "lea")

--- 11 unchanged lines hidden (view full) ---

10688 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10689 (match_operand:QI 2 "const_int_operand" ""))))
10690 (clobber (reg:CC 17))]
10691 "reload_completed
10692 && true_regnum (operands[0]) != true_regnum (operands[1])"
10693 [(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))]
10694{
10695 operands[1] = gen_lowpart (Pmode, operands[1]);
10942 operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10943 Pmode));
10696 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10697})
10698
10699;; This pattern can't accept a variable shift count, since shifts by
10700;; zero don't affect the flags. We assume that shifts by constant
10701;; zero are optimized away.
10702(define_insn "*ashlsi3_cmp"
10703 [(set (reg 17)
10704 (compare

--- 12 unchanged lines hidden (view full) ---

10717 abort ();
10718 return "add{l}\t{%0, %0|%0, %0}";
10719
10720 default:
10721 if (REG_P (operands[2]))
10722 return "sal{l}\t{%b2, %0|%0, %b2}";
10723 else if (GET_CODE (operands[2]) == CONST_INT
10724 && INTVAL (operands[2]) == 1
10972 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10725 && (TARGET_SHIFT1 || optimize_size))
10726 return "sal{l}\t%0";
10727 else
10728 return "sal{l}\t{%2, %0|%0, %2}";
10729 }
10730}
10731 [(set (attr "type")
10732 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10733 (const_int 0))

--- 22 unchanged lines hidden (view full) ---

10756 abort ();
10757 return "add{l}\t{%k0, %k0|%k0, %k0}";
10758
10759 default:
10760 if (REG_P (operands[2]))
10761 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10762 else if (GET_CODE (operands[2]) == CONST_INT
10763 && INTVAL (operands[2]) == 1
11011 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10764 && (TARGET_SHIFT1 || optimize_size))
10765 return "sal{l}\t%k0";
10766 else
10767 return "sal{l}\t{%2, %k0|%k0, %2}";
10768 }
10769}
10770 [(set (attr "type")
10771 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10772 (const_int 0))

--- 28 unchanged lines hidden (view full) ---

10801 abort ();
10802 return "add{w}\t{%0, %0|%0, %0}";
10803
10804 default:
10805 if (REG_P (operands[2]))
10806 return "sal{w}\t{%b2, %0|%0, %b2}";
10807 else if (GET_CODE (operands[2]) == CONST_INT
10808 && INTVAL (operands[2]) == 1
11056 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10809 && (TARGET_SHIFT1 || optimize_size))
10810 return "sal{w}\t%0";
10811 else
10812 return "sal{w}\t{%2, %0|%0, %2}";
10813 }
10814}
10815 [(set (attr "type")
10816 (cond [(eq_attr "alternative" "1")
10817 (const_string "lea")

--- 21 unchanged lines hidden (view full) ---

10839 abort ();
10840 return "add{w}\t{%0, %0|%0, %0}";
10841
10842 default:
10843 if (REG_P (operands[2]))
10844 return "sal{w}\t{%b2, %0|%0, %b2}";
10845 else if (GET_CODE (operands[2]) == CONST_INT
10846 && INTVAL (operands[2]) == 1
11094 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10847 && (TARGET_SHIFT1 || optimize_size))
10848 return "sal{w}\t%0";
10849 else
10850 return "sal{w}\t{%2, %0|%0, %2}";
10851 }
10852}
10853 [(set (attr "type")
10854 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10855 (const_int 0))

--- 25 unchanged lines hidden (view full) ---

10881 abort ();
10882 return "add{w}\t{%0, %0|%0, %0}";
10883
10884 default:
10885 if (REG_P (operands[2]))
10886 return "sal{w}\t{%b2, %0|%0, %b2}";
10887 else if (GET_CODE (operands[2]) == CONST_INT
10888 && INTVAL (operands[2]) == 1
11136 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10889 && (TARGET_SHIFT1 || optimize_size))
10890 return "sal{w}\t%0";
10891 else
10892 return "sal{w}\t{%2, %0|%0, %2}";
10893 }
10894}
10895 [(set (attr "type")
10896 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10897 (const_int 0))

--- 39 unchanged lines hidden (view full) ---

10937 {
10938 if (get_attr_mode (insn) == MODE_SI)
10939 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10940 else
10941 return "sal{b}\t{%b2, %0|%0, %b2}";
10942 }
10943 else if (GET_CODE (operands[2]) == CONST_INT
10944 && INTVAL (operands[2]) == 1
11192 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10945 && (TARGET_SHIFT1 || optimize_size))
10946 {
10947 if (get_attr_mode (insn) == MODE_SI)
10948 return "sal{l}\t%0";
10949 else
10950 return "sal{b}\t%0";
10951 }
10952 else
10953 {

--- 39 unchanged lines hidden (view full) ---

10993 {
10994 if (get_attr_mode (insn) == MODE_SI)
10995 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10996 else
10997 return "sal{b}\t{%b2, %0|%0, %b2}";
10998 }
10999 else if (GET_CODE (operands[2]) == CONST_INT
11000 && INTVAL (operands[2]) == 1
11248 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11001 && (TARGET_SHIFT1 || optimize_size))
11002 {
11003 if (get_attr_mode (insn) == MODE_SI)
11004 return "sal{l}\t%0";
11005 else
11006 return "sal{b}\t%0";
11007 }
11008 else
11009 {

--- 35 unchanged lines hidden (view full) ---

11045 abort ();
11046 return "add{b}\t{%0, %0|%0, %0}";
11047
11048 default:
11049 if (REG_P (operands[2]))
11050 return "sal{b}\t{%b2, %0|%0, %b2}";
11051 else if (GET_CODE (operands[2]) == CONST_INT
11052 && INTVAL (operands[2]) == 1
11300 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11053 && (TARGET_SHIFT1 || optimize_size))
11054 return "sal{b}\t%0";
11055 else
11056 return "sal{b}\t{%2, %0|%0, %2}";
11057 }
11058}
11059 [(set (attr "type")
11060 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11061 (const_int 0))

--- 39 unchanged lines hidden (view full) ---

11101 (set_attr "mode" "DI")])
11102
11103(define_insn "*ashrdi3_1_one_bit_rex64"
11104 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11105 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11106 (match_operand:QI 2 "const_int_1_operand" "")))
11107 (clobber (reg:CC 17))]
11108 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11356 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11109 && (TARGET_SHIFT1 || optimize_size)"
11110 "sar{q}\t%0"
11111 [(set_attr "type" "ishift")
11112 (set (attr "length")
11113 (if_then_else (match_operand:DI 0 "register_operand" "")
11114 (const_string "2")
11115 (const_string "*")))])
11116
11117(define_insn "*ashrdi3_1_rex64"

--- 15 unchanged lines hidden (view full) ---

11133 [(set (reg 17)
11134 (compare
11135 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11136 (match_operand:QI 2 "const_int_1_operand" ""))
11137 (const_int 0)))
11138 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11139 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11140 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11388 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11141 && (TARGET_SHIFT1 || optimize_size)
11142 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11143 "sar{q}\t%0"
11144 [(set_attr "type" "ishift")
11145 (set (attr "length")
11146 (if_then_else (match_operand:DI 0 "register_operand" "")
11147 (const_string "2")
11148 (const_string "*")))])
11149

--- 140 unchanged lines hidden (view full) ---

11290 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11291
11292(define_insn "*ashrsi3_1_one_bit"
11293 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11294 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11295 (match_operand:QI 2 "const_int_1_operand" "")))
11296 (clobber (reg:CC 17))]
11297 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11545 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11298 && (TARGET_SHIFT1 || optimize_size)"
11299 "sar{l}\t%0"
11300 [(set_attr "type" "ishift")
11301 (set (attr "length")
11302 (if_then_else (match_operand:SI 0 "register_operand" "")
11303 (const_string "2")
11304 (const_string "*")))])
11305
11306(define_insn "*ashrsi3_1_one_bit_zext"
11307 [(set (match_operand:DI 0 "register_operand" "=r")
11308 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11309 (match_operand:QI 2 "const_int_1_operand" ""))))
11310 (clobber (reg:CC 17))]
11311 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11559 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11312 && (TARGET_SHIFT1 || optimize_size)"
11313 "sar{l}\t%k0"
11314 [(set_attr "type" "ishift")
11315 (set_attr "length" "2")])
11316
11317(define_insn "*ashrsi3_1"
11318 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11319 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11320 (match_operand:QI 2 "nonmemory_operand" "I,c")))

--- 24 unchanged lines hidden (view full) ---

11345 [(set (reg 17)
11346 (compare
11347 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11348 (match_operand:QI 2 "const_int_1_operand" ""))
11349 (const_int 0)))
11350 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11351 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11352 "ix86_match_ccmode (insn, CCGOCmode)
11600 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11353 && (TARGET_SHIFT1 || optimize_size)
11354 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11355 "sar{l}\t%0"
11356 [(set_attr "type" "ishift")
11357 (set (attr "length")
11358 (if_then_else (match_operand:SI 0 "register_operand" "")
11359 (const_string "2")
11360 (const_string "*")))])
11361
11362(define_insn "*ashrsi3_one_bit_cmp_zext"
11363 [(set (reg 17)
11364 (compare
11365 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11366 (match_operand:QI 2 "const_int_1_operand" ""))
11367 (const_int 0)))
11368 (set (match_operand:DI 0 "register_operand" "=r")
11369 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11370 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11618 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11371 && (TARGET_SHIFT1 || optimize_size)
11372 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11373 "sar{l}\t%k0"
11374 [(set_attr "type" "ishift")
11375 (set_attr "length" "2")])
11376
11377;; This pattern can't accept a variable shift count, since shifts by
11378;; zero don't affect the flags. We assume that shifts by constant
11379;; zero are optimized away.

--- 34 unchanged lines hidden (view full) ---

11414 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11415
11416(define_insn "*ashrhi3_1_one_bit"
11417 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11418 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11419 (match_operand:QI 2 "const_int_1_operand" "")))
11420 (clobber (reg:CC 17))]
11421 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11669 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11422 && (TARGET_SHIFT1 || optimize_size)"
11423 "sar{w}\t%0"
11424 [(set_attr "type" "ishift")
11425 (set (attr "length")
11426 (if_then_else (match_operand 0 "register_operand" "")
11427 (const_string "2")
11428 (const_string "*")))])
11429
11430(define_insn "*ashrhi3_1"

--- 15 unchanged lines hidden (view full) ---

11446 [(set (reg 17)
11447 (compare
11448 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11449 (match_operand:QI 2 "const_int_1_operand" ""))
11450 (const_int 0)))
11451 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11452 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11453 "ix86_match_ccmode (insn, CCGOCmode)
11701 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11454 && (TARGET_SHIFT1 || optimize_size)
11455 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11456 "sar{w}\t%0"
11457 [(set_attr "type" "ishift")
11458 (set (attr "length")
11459 (if_then_else (match_operand 0 "register_operand" "")
11460 (const_string "2")
11461 (const_string "*")))])
11462

--- 23 unchanged lines hidden (view full) ---

11486 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11487
11488(define_insn "*ashrqi3_1_one_bit"
11489 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11490 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11491 (match_operand:QI 2 "const_int_1_operand" "")))
11492 (clobber (reg:CC 17))]
11493 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11741 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11494 && (TARGET_SHIFT1 || optimize_size)"
11495 "sar{b}\t%0"
11496 [(set_attr "type" "ishift")
11497 (set (attr "length")
11498 (if_then_else (match_operand 0 "register_operand" "")
11499 (const_string "2")
11500 (const_string "*")))])
11501
11502(define_insn "*ashrqi3_1_one_bit_slp"
11503 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11504 (ashiftrt:QI (match_dup 0)
11505 (match_operand:QI 1 "const_int_1_operand" "")))
11506 (clobber (reg:CC 17))]
11507 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11508 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
11509 && (TARGET_SHIFT1 || optimize_size)"
11510 "sar{b}\t%0"
11511 [(set_attr "type" "ishift1")
11512 (set (attr "length")
11513 (if_then_else (match_operand 0 "register_operand" "")
11514 (const_string "2")
11515 (const_string "*")))])
11516
11517(define_insn "*ashrqi3_1"
11518 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11519 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11520 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11521 (clobber (reg:CC 17))]
11522 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11523 "@
11524 sar{b}\t{%2, %0|%0, %2}
11525 sar{b}\t{%b2, %0|%0, %b2}"
11526 [(set_attr "type" "ishift")
11527 (set_attr "mode" "QI")])
11528
11529(define_insn "*ashrqi3_1_slp"
11530 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11531 (ashiftrt:QI (match_dup 0)
11532 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11533 (clobber (reg:CC 17))]
11534 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11535 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11536 "@
11537 sar{b}\t{%1, %0|%0, %1}
11538 sar{b}\t{%b1, %0|%0, %b1}"
11539 [(set_attr "type" "ishift1")
11540 (set_attr "mode" "QI")])
11541
11542;; This pattern can't accept a variable shift count, since shifts by
11543;; zero don't affect the flags. We assume that shifts by constant
11544;; zero are optimized away.
11545(define_insn "*ashrqi3_one_bit_cmp"
11546 [(set (reg 17)
11547 (compare
11548 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11549 (match_operand:QI 2 "const_int_1_operand" "I"))
11550 (const_int 0)))
11551 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11552 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11553 "ix86_match_ccmode (insn, CCGOCmode)
11773 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11554 && (TARGET_SHIFT1 || optimize_size)
11555 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11556 "sar{b}\t%0"
11557 [(set_attr "type" "ishift")
11558 (set (attr "length")
11559 (if_then_else (match_operand 0 "register_operand" "")
11560 (const_string "2")
11561 (const_string "*")))])
11562

--- 35 unchanged lines hidden (view full) ---

11598})
11599
11600(define_insn "*lshrdi3_1_one_bit_rex64"
11601 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11602 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11603 (match_operand:QI 2 "const_int_1_operand" "")))
11604 (clobber (reg:CC 17))]
11605 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11825 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11606 && (TARGET_SHIFT1 || optimize_size)"
11607 "shr{q}\t%0"
11608 [(set_attr "type" "ishift")
11609 (set (attr "length")
11610 (if_then_else (match_operand:DI 0 "register_operand" "")
11611 (const_string "2")
11612 (const_string "*")))])
11613
11614(define_insn "*lshrdi3_1_rex64"

--- 15 unchanged lines hidden (view full) ---

11630 [(set (reg 17)
11631 (compare
11632 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11633 (match_operand:QI 2 "const_int_1_operand" ""))
11634 (const_int 0)))
11635 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11636 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11637 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11857 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11638 && (TARGET_SHIFT1 || optimize_size)
11639 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11640 "shr{q}\t%0"
11641 [(set_attr "type" "ishift")
11642 (set (attr "length")
11643 (if_then_else (match_operand:DI 0 "register_operand" "")
11644 (const_string "2")
11645 (const_string "*")))])
11646

--- 61 unchanged lines hidden (view full) ---

11708 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11709
11710(define_insn "*lshrsi3_1_one_bit"
11711 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11712 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11713 (match_operand:QI 2 "const_int_1_operand" "")))
11714 (clobber (reg:CC 17))]
11715 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11935 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11716 && (TARGET_SHIFT1 || optimize_size)"
11717 "shr{l}\t%0"
11718 [(set_attr "type" "ishift")
11719 (set (attr "length")
11720 (if_then_else (match_operand:SI 0 "register_operand" "")
11721 (const_string "2")
11722 (const_string "*")))])
11723
11724(define_insn "*lshrsi3_1_one_bit_zext"
11725 [(set (match_operand:DI 0 "register_operand" "=r")
11726 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11727 (match_operand:QI 2 "const_int_1_operand" "")))
11728 (clobber (reg:CC 17))]
11729 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11949 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11730 && (TARGET_SHIFT1 || optimize_size)"
11731 "shr{l}\t%k0"
11732 [(set_attr "type" "ishift")
11733 (set_attr "length" "2")])
11734
11735(define_insn "*lshrsi3_1"
11736 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11737 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11738 (match_operand:QI 2 "nonmemory_operand" "I,c")))

--- 25 unchanged lines hidden (view full) ---

11764 [(set (reg 17)
11765 (compare
11766 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11767 (match_operand:QI 2 "const_int_1_operand" ""))
11768 (const_int 0)))
11769 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11770 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11771 "ix86_match_ccmode (insn, CCGOCmode)
11991 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11772 && (TARGET_SHIFT1 || optimize_size)
11773 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11774 "shr{l}\t%0"
11775 [(set_attr "type" "ishift")
11776 (set (attr "length")
11777 (if_then_else (match_operand:SI 0 "register_operand" "")
11778 (const_string "2")
11779 (const_string "*")))])
11780
11781(define_insn "*lshrsi3_cmp_one_bit_zext"
11782 [(set (reg 17)
11783 (compare
11784 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11785 (match_operand:QI 2 "const_int_1_operand" ""))
11786 (const_int 0)))
11787 (set (match_operand:DI 0 "register_operand" "=r")
11788 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11789 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12009 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11790 && (TARGET_SHIFT1 || optimize_size)
11791 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11792 "shr{l}\t%k0"
11793 [(set_attr "type" "ishift")
11794 (set_attr "length" "2")])
11795
11796;; This pattern can't accept a variable shift count, since shifts by
11797;; zero don't affect the flags. We assume that shifts by constant
11798;; zero are optimized away.

--- 34 unchanged lines hidden (view full) ---

11833 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
11834
11835(define_insn "*lshrhi3_1_one_bit"
11836 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11837 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11838 (match_operand:QI 2 "const_int_1_operand" "")))
11839 (clobber (reg:CC 17))]
11840 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12060 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11841 && (TARGET_SHIFT1 || optimize_size)"
11842 "shr{w}\t%0"
11843 [(set_attr "type" "ishift")
11844 (set (attr "length")
11845 (if_then_else (match_operand 0 "register_operand" "")
11846 (const_string "2")
11847 (const_string "*")))])
11848
11849(define_insn "*lshrhi3_1"

--- 15 unchanged lines hidden (view full) ---

11865 [(set (reg 17)
11866 (compare
11867 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11868 (match_operand:QI 2 "const_int_1_operand" ""))
11869 (const_int 0)))
11870 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11871 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11872 "ix86_match_ccmode (insn, CCGOCmode)
12092 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11873 && (TARGET_SHIFT1 || optimize_size)
11874 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11875 "shr{w}\t%0"
11876 [(set_attr "type" "ishift")
11877 (set (attr "length")
11878 (if_then_else (match_operand:SI 0 "register_operand" "")
11879 (const_string "2")
11880 (const_string "*")))])
11881

--- 23 unchanged lines hidden (view full) ---

11905 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
11906
11907(define_insn "*lshrqi3_1_one_bit"
11908 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11909 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11910 (match_operand:QI 2 "const_int_1_operand" "")))
11911 (clobber (reg:CC 17))]
11912 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
12132 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11913 && (TARGET_SHIFT1 || optimize_size)"
11914 "shr{b}\t%0"
11915 [(set_attr "type" "ishift")
11916 (set (attr "length")
11917 (if_then_else (match_operand 0 "register_operand" "")
11918 (const_string "2")
11919 (const_string "*")))])
11920
11921(define_insn "*lshrqi3_1_one_bit_slp"
11922 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11923 (lshiftrt:QI (match_dup 0)
11924 (match_operand:QI 1 "const_int_1_operand" "")))
11925 (clobber (reg:CC 17))]
11926 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11927 && (TARGET_SHIFT1 || optimize_size)"
11928 "shr{b}\t%0"
11929 [(set_attr "type" "ishift1")
11930 (set (attr "length")
11931 (if_then_else (match_operand 0 "register_operand" "")
11932 (const_string "2")
11933 (const_string "*")))])
11934
11935(define_insn "*lshrqi3_1"
11936 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11937 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11938 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11939 (clobber (reg:CC 17))]
11940 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11941 "@
11942 shr{b}\t{%2, %0|%0, %2}
11943 shr{b}\t{%b2, %0|%0, %b2}"
11944 [(set_attr "type" "ishift")
11945 (set_attr "mode" "QI")])
11946
11947(define_insn "*lshrqi3_1_slp"
11948 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11949 (lshiftrt:QI (match_dup 0)
11950 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11951 (clobber (reg:CC 17))]
11952 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11953 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11954 "@
11955 shr{b}\t{%1, %0|%0, %1}
11956 shr{b}\t{%b1, %0|%0, %b1}"
11957 [(set_attr "type" "ishift1")
11958 (set_attr "mode" "QI")])
11959
11960;; This pattern can't accept a variable shift count, since shifts by
11961;; zero don't affect the flags. We assume that shifts by constant
11962;; zero are optimized away.
11963(define_insn "*lshrqi2_one_bit_cmp"
11964 [(set (reg 17)
11965 (compare
11966 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11967 (match_operand:QI 2 "const_int_1_operand" ""))
11968 (const_int 0)))
11969 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11970 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11971 "ix86_match_ccmode (insn, CCGOCmode)
12164 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11972 && (TARGET_SHIFT1 || optimize_size)
11973 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11974 "shr{b}\t%0"
11975 [(set_attr "type" "ishift")
11976 (set (attr "length")
11977 (if_then_else (match_operand:SI 0 "register_operand" "")
11978 (const_string "2")
11979 (const_string "*")))])
11980

--- 25 unchanged lines hidden (view full) ---

12006 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12007
12008(define_insn "*rotlsi3_1_one_bit_rex64"
12009 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12010 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12011 (match_operand:QI 2 "const_int_1_operand" "")))
12012 (clobber (reg:CC 17))]
12013 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12206 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12014 && (TARGET_SHIFT1 || optimize_size)"
12015 "rol{q}\t%0"
12208 [(set_attr "type" "ishift")
12016 [(set_attr "type" "rotate")
12017 (set (attr "length")
12018 (if_then_else (match_operand:DI 0 "register_operand" "")
12019 (const_string "2")
12020 (const_string "*")))])
12021
12022(define_insn "*rotldi3_1_rex64"
12023 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12024 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12025 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12026 (clobber (reg:CC 17))]
12027 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12028 "@
12029 rol{q}\t{%2, %0|%0, %2}
12030 rol{q}\t{%b2, %0|%0, %b2}"
12223 [(set_attr "type" "ishift")
12031 [(set_attr "type" "rotate")
12032 (set_attr "mode" "DI")])
12033
12034(define_expand "rotlsi3"
12035 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12036 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12037 (match_operand:QI 2 "nonmemory_operand" "")))
12038 (clobber (reg:CC 17))]
12039 ""
12040 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12041
12042(define_insn "*rotlsi3_1_one_bit"
12043 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12044 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12045 (match_operand:QI 2 "const_int_1_operand" "")))
12046 (clobber (reg:CC 17))]
12047 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12240 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12048 && (TARGET_SHIFT1 || optimize_size)"
12049 "rol{l}\t%0"
12242 [(set_attr "type" "ishift")
12050 [(set_attr "type" "rotate")
12051 (set (attr "length")
12052 (if_then_else (match_operand:SI 0 "register_operand" "")
12053 (const_string "2")
12054 (const_string "*")))])
12055
12056(define_insn "*rotlsi3_1_one_bit_zext"
12057 [(set (match_operand:DI 0 "register_operand" "=r")
12058 (zero_extend:DI
12059 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12060 (match_operand:QI 2 "const_int_1_operand" ""))))
12061 (clobber (reg:CC 17))]
12062 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12255 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12063 && (TARGET_SHIFT1 || optimize_size)"
12064 "rol{l}\t%k0"
12257 [(set_attr "type" "ishift")
12065 [(set_attr "type" "rotate")
12066 (set_attr "length" "2")])
12067
12068(define_insn "*rotlsi3_1"
12069 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12070 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12071 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12072 (clobber (reg:CC 17))]
12073 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12074 "@
12075 rol{l}\t{%2, %0|%0, %2}
12076 rol{l}\t{%b2, %0|%0, %b2}"
12269 [(set_attr "type" "ishift")
12077 [(set_attr "type" "rotate")
12078 (set_attr "mode" "SI")])
12079
12080(define_insn "*rotlsi3_1_zext"
12081 [(set (match_operand:DI 0 "register_operand" "=r,r")
12082 (zero_extend:DI
12083 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12084 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12085 (clobber (reg:CC 17))]
12086 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12087 "@
12088 rol{l}\t{%2, %k0|%k0, %2}
12089 rol{l}\t{%b2, %k0|%k0, %b2}"
12282 [(set_attr "type" "ishift")
12090 [(set_attr "type" "rotate")
12091 (set_attr "mode" "SI")])
12092
12093(define_expand "rotlhi3"
12094 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12095 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12096 (match_operand:QI 2 "nonmemory_operand" "")))
12097 (clobber (reg:CC 17))]
12098 "TARGET_HIMODE_MATH"
12099 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12100
12101(define_insn "*rotlhi3_1_one_bit"
12102 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12103 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12104 (match_operand:QI 2 "const_int_1_operand" "")))
12105 (clobber (reg:CC 17))]
12106 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12299 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12107 && (TARGET_SHIFT1 || optimize_size)"
12108 "rol{w}\t%0"
12301 [(set_attr "type" "ishift")
12109 [(set_attr "type" "rotate")
12110 (set (attr "length")
12111 (if_then_else (match_operand 0 "register_operand" "")
12112 (const_string "2")
12113 (const_string "*")))])
12114
12115(define_insn "*rotlhi3_1"
12116 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12117 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12118 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12119 (clobber (reg:CC 17))]
12120 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12121 "@
12122 rol{w}\t{%2, %0|%0, %2}
12123 rol{w}\t{%b2, %0|%0, %b2}"
12316 [(set_attr "type" "ishift")
12124 [(set_attr "type" "rotate")
12125 (set_attr "mode" "HI")])
12126
12127(define_expand "rotlqi3"
12128 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12129 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12130 (match_operand:QI 2 "nonmemory_operand" "")))
12131 (clobber (reg:CC 17))]
12132 "TARGET_QIMODE_MATH"
12133 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12134
12135(define_insn "*rotlqi3_1_one_bit_slp"
12136 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12137 (rotate:QI (match_dup 0)
12138 (match_operand:QI 1 "const_int_1_operand" "")))
12139 (clobber (reg:CC 17))]
12140 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12141 && (TARGET_SHIFT1 || optimize_size)"
12142 "rol{b}\t%0"
12143 [(set_attr "type" "rotate1")
12144 (set (attr "length")
12145 (if_then_else (match_operand 0 "register_operand" "")
12146 (const_string "2")
12147 (const_string "*")))])
12148
12149(define_insn "*rotlqi3_1_one_bit"
12150 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12151 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12152 (match_operand:QI 2 "const_int_1_operand" "")))
12153 (clobber (reg:CC 17))]
12154 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12333 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12155 && (TARGET_SHIFT1 || optimize_size)"
12156 "rol{b}\t%0"
12335 [(set_attr "type" "ishift")
12157 [(set_attr "type" "rotate")
12158 (set (attr "length")
12159 (if_then_else (match_operand 0 "register_operand" "")
12160 (const_string "2")
12161 (const_string "*")))])
12162
12163(define_insn "*rotlqi3_1_slp"
12164 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12165 (rotate:QI (match_dup 0)
12166 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12167 (clobber (reg:CC 17))]
12168 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12169 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12170 "@
12171 rol{b}\t{%1, %0|%0, %1}
12172 rol{b}\t{%b1, %0|%0, %b1}"
12173 [(set_attr "type" "rotate1")
12174 (set_attr "mode" "QI")])
12175
12176(define_insn "*rotlqi3_1"
12177 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12178 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12179 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12180 (clobber (reg:CC 17))]
12181 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12182 "@
12183 rol{b}\t{%2, %0|%0, %2}
12184 rol{b}\t{%b2, %0|%0, %b2}"
12350 [(set_attr "type" "ishift")
12185 [(set_attr "type" "rotate")
12186 (set_attr "mode" "QI")])
12187
12188(define_expand "rotrdi3"
12189 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12190 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12191 (match_operand:QI 2 "nonmemory_operand" "")))
12192 (clobber (reg:CC 17))]
12193 "TARGET_64BIT"
12194 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12195
12196(define_insn "*rotrdi3_1_one_bit_rex64"
12197 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12198 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12199 (match_operand:QI 2 "const_int_1_operand" "")))
12200 (clobber (reg:CC 17))]
12201 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12367 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12202 && (TARGET_SHIFT1 || optimize_size)"
12203 "ror{q}\t%0"
12369 [(set_attr "type" "ishift")
12204 [(set_attr "type" "rotate")
12205 (set (attr "length")
12206 (if_then_else (match_operand:DI 0 "register_operand" "")
12207 (const_string "2")
12208 (const_string "*")))])
12209
12210(define_insn "*rotrdi3_1_rex64"
12211 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12212 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12213 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12214 (clobber (reg:CC 17))]
12215 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12216 "@
12217 ror{q}\t{%2, %0|%0, %2}
12218 ror{q}\t{%b2, %0|%0, %b2}"
12384 [(set_attr "type" "ishift")
12219 [(set_attr "type" "rotate")
12220 (set_attr "mode" "DI")])
12221
12222(define_expand "rotrsi3"
12223 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12224 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12225 (match_operand:QI 2 "nonmemory_operand" "")))
12226 (clobber (reg:CC 17))]
12227 ""
12228 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12229
12230(define_insn "*rotrsi3_1_one_bit"
12231 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12232 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12233 (match_operand:QI 2 "const_int_1_operand" "")))
12234 (clobber (reg:CC 17))]
12235 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12401 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12236 && (TARGET_SHIFT1 || optimize_size)"
12237 "ror{l}\t%0"
12403 [(set_attr "type" "ishift")
12238 [(set_attr "type" "rotate")
12239 (set (attr "length")
12240 (if_then_else (match_operand:SI 0 "register_operand" "")
12241 (const_string "2")
12242 (const_string "*")))])
12243
12244(define_insn "*rotrsi3_1_one_bit_zext"
12245 [(set (match_operand:DI 0 "register_operand" "=r")
12246 (zero_extend:DI
12247 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12248 (match_operand:QI 2 "const_int_1_operand" ""))))
12249 (clobber (reg:CC 17))]
12250 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12416 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12251 && (TARGET_SHIFT1 || optimize_size)"
12252 "ror{l}\t%k0"
12418 [(set_attr "type" "ishift")
12253 [(set_attr "type" "rotate")
12254 (set (attr "length")
12255 (if_then_else (match_operand:SI 0 "register_operand" "")
12256 (const_string "2")
12257 (const_string "*")))])
12258
12259(define_insn "*rotrsi3_1"
12260 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12261 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12262 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12263 (clobber (reg:CC 17))]
12264 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12265 "@
12266 ror{l}\t{%2, %0|%0, %2}
12267 ror{l}\t{%b2, %0|%0, %b2}"
12433 [(set_attr "type" "ishift")
12268 [(set_attr "type" "rotate")
12269 (set_attr "mode" "SI")])
12270
12271(define_insn "*rotrsi3_1_zext"
12272 [(set (match_operand:DI 0 "register_operand" "=r,r")
12273 (zero_extend:DI
12274 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12275 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12276 (clobber (reg:CC 17))]
12277 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12278 "@
12279 ror{l}\t{%2, %k0|%k0, %2}
12280 ror{l}\t{%b2, %k0|%k0, %b2}"
12446 [(set_attr "type" "ishift")
12281 [(set_attr "type" "rotate")
12282 (set_attr "mode" "SI")])
12283
12284(define_expand "rotrhi3"
12285 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12286 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12287 (match_operand:QI 2 "nonmemory_operand" "")))
12288 (clobber (reg:CC 17))]
12289 "TARGET_HIMODE_MATH"
12290 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12291
12292(define_insn "*rotrhi3_one_bit"
12293 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12294 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12295 (match_operand:QI 2 "const_int_1_operand" "")))
12296 (clobber (reg:CC 17))]
12297 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12463 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12298 && (TARGET_SHIFT1 || optimize_size)"
12299 "ror{w}\t%0"
12465 [(set_attr "type" "ishift")
12300 [(set_attr "type" "rotate")
12301 (set (attr "length")
12302 (if_then_else (match_operand 0 "register_operand" "")
12303 (const_string "2")
12304 (const_string "*")))])
12305
12306(define_insn "*rotrhi3"
12307 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12308 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12309 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12310 (clobber (reg:CC 17))]
12311 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12312 "@
12313 ror{w}\t{%2, %0|%0, %2}
12314 ror{w}\t{%b2, %0|%0, %b2}"
12480 [(set_attr "type" "ishift")
12315 [(set_attr "type" "rotate")
12316 (set_attr "mode" "HI")])
12317
12318(define_expand "rotrqi3"
12319 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12320 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12321 (match_operand:QI 2 "nonmemory_operand" "")))
12322 (clobber (reg:CC 17))]
12323 "TARGET_QIMODE_MATH"
12324 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12325
12326(define_insn "*rotrqi3_1_one_bit"
12327 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12328 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12329 (match_operand:QI 2 "const_int_1_operand" "")))
12330 (clobber (reg:CC 17))]
12331 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12497 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12332 && (TARGET_SHIFT1 || optimize_size)"
12333 "ror{b}\t%0"
12499 [(set_attr "type" "ishift")
12334 [(set_attr "type" "rotate")
12335 (set (attr "length")
12336 (if_then_else (match_operand 0 "register_operand" "")
12337 (const_string "2")
12338 (const_string "*")))])
12339
12340(define_insn "*rotrqi3_1_one_bit_slp"
12341 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12342 (rotatert:QI (match_dup 0)
12343 (match_operand:QI 1 "const_int_1_operand" "")))
12344 (clobber (reg:CC 17))]
12345 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12346 && (TARGET_SHIFT1 || optimize_size)"
12347 "ror{b}\t%0"
12348 [(set_attr "type" "rotate1")
12349 (set (attr "length")
12350 (if_then_else (match_operand 0 "register_operand" "")
12351 (const_string "2")
12352 (const_string "*")))])
12353
12354(define_insn "*rotrqi3_1"
12355 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12356 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12357 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12358 (clobber (reg:CC 17))]
12359 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12360 "@
12361 ror{b}\t{%2, %0|%0, %2}
12362 ror{b}\t{%b2, %0|%0, %b2}"
12514 [(set_attr "type" "ishift")
12363 [(set_attr "type" "rotate")
12364 (set_attr "mode" "QI")])
12365
12366(define_insn "*rotrqi3_1_slp"
12367 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12368 (rotatert:QI (match_dup 0)
12369 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12370 (clobber (reg:CC 17))]
12371 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12372 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12373 "@
12374 ror{b}\t{%1, %0|%0, %1}
12375 ror{b}\t{%b1, %0|%0, %b1}"
12376 [(set_attr "type" "rotate1")
12377 (set_attr "mode" "QI")])
12378
12379;; Bit set / bit test instructions
12380
12381(define_expand "extv"
12382 [(set (match_operand:SI 0 "register_operand" "")
12383 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12384 (match_operand:SI 2 "immediate_operand" "")
12385 (match_operand:SI 3 "immediate_operand" "")))]

--- 260 unchanged lines hidden (view full) ---

12646
12647(define_insn "*sse_setccsf"
12648 [(set (match_operand:SF 0 "register_operand" "=x")
12649 (match_operator:SF 1 "sse_comparison_operator"
12650 [(match_operand:SF 2 "register_operand" "0")
12651 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12652 "TARGET_SSE && reload_completed"
12653 "cmp%D1ss\t{%3, %0|%0, %3}"
12792 [(set_attr "type" "sse")
12654 [(set_attr "type" "ssecmp")
12655 (set_attr "mode" "SF")])
12656
12657(define_insn "*sse_setccdf"
12658 [(set (match_operand:DF 0 "register_operand" "=Y")
12659 (match_operator:DF 1 "sse_comparison_operator"
12660 [(match_operand:DF 2 "register_operand" "0")
12661 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12662 "TARGET_SSE2 && reload_completed"
12663 "cmp%D1sd\t{%3, %0|%0, %3}"
12802 [(set_attr "type" "sse")
12664 [(set_attr "type" "ssecmp")
12665 (set_attr "mode" "DF")])
12666
12667;; Basic conditional jump instructions.
12668;; We ignore the overflow flag for signed branch instructions.
12669
12670;; For all bCOND expanders, also expand the compare or test insn that
12671;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
12672

--- 145 unchanged lines hidden (view full) ---

12818 [(set (pc)
12819 (if_then_else (match_operator 1 "ix86_comparison_operator"
12820 [(reg 17) (const_int 0)])
12821 (label_ref (match_operand 0 "" ""))
12822 (pc)))]
12823 ""
12824 "%+j%C1\t%l0"
12825 [(set_attr "type" "ibr")
12964 (set (attr "prefix_0f")
12826 (set_attr "modrm" "0")
12827 (set (attr "length")
12828 (if_then_else (and (ge (minus (match_dup 0) (pc))
12966 (const_int -128))
12829 (const_int -126))
12830 (lt (minus (match_dup 0) (pc))
12968 (const_int 124)))
12969 (const_int 0)
12970 (const_int 1)))])
12831 (const_int 128)))
12832 (const_int 2)
12833 (const_int 6)))])
12834
12835(define_insn "*jcc_2"
12836 [(set (pc)
12837 (if_then_else (match_operator 1 "ix86_comparison_operator"
12838 [(reg 17) (const_int 0)])
12839 (pc)
12840 (label_ref (match_operand 0 "" ""))))]
12841 ""
12842 "%+j%c1\t%l0"
12843 [(set_attr "type" "ibr")
12981 (set (attr "prefix_0f")
12844 (set_attr "modrm" "0")
12845 (set (attr "length")
12846 (if_then_else (and (ge (minus (match_dup 0) (pc))
12983 (const_int -128))
12847 (const_int -126))
12848 (lt (minus (match_dup 0) (pc))
12985 (const_int 124)))
12986 (const_int 0)
12987 (const_int 1)))])
12849 (const_int 128)))
12850 (const_int 2)
12851 (const_int 6)))])
12852
12853;; In general it is not safe to assume too much about CCmode registers,
12854;; so simplify-rtx stops when it sees a second one. Under certain
12855;; conditions this is safe on x86, so help combine not create
12856;;
12857;; seta %al
12858;; testb %al, %al
12859;; je Lfoo

--- 243 unchanged lines hidden (view full) ---

13103
13104;; Unconditional and other jump instructions
13105
13106(define_insn "jump"
13107 [(set (pc)
13108 (label_ref (match_operand 0 "" "")))]
13109 ""
13110 "jmp\t%l0"
13247 [(set_attr "type" "ibr")])
13111 [(set_attr "type" "ibr")
13112 (set (attr "length")
13113 (if_then_else (and (ge (minus (match_dup 0) (pc))
13114 (const_int -126))
13115 (lt (minus (match_dup 0) (pc))
13116 (const_int 128)))
13117 (const_int 2)
13118 (const_int 5)))
13119 (set_attr "modrm" "0")])
13120
13121(define_expand "indirect_jump"
13122 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13123 ""
13124 "")
13125
13126(define_insn "*indirect_jump"
13127 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]

--- 9 unchanged lines hidden (view full) ---

13137 [(set_attr "type" "ibr")
13138 (set_attr "length_immediate" "0")])
13139
13140(define_expand "tablejump"
13141 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13142 (use (label_ref (match_operand 1 "" "")))])]
13143 ""
13144{
13273 /* In PIC mode, the table entries are stored GOT-relative. Convert
13274 the relative address to an absolute address. */
13145 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13146 relative. Convert the relative address to an absolute address. */
13147 if (flag_pic)
13148 {
13149 rtx op0, op1;
13150 enum rtx_code code;
13151
13152 if (TARGET_64BIT)
13278 operands[0] = expand_simple_binop (Pmode, PLUS, operands[0],
13279 gen_rtx_LABEL_REF (Pmode, operands[1]),
13280 NULL_RTX, 0,
13281 OPTAB_DIRECT);
13282 else if (HAVE_AS_GOTOFF_IN_DATA)
13153 {
13284 operands[0] = expand_simple_binop (Pmode, PLUS, operands[0],
13285 pic_offset_table_rtx, NULL_RTX,
13286 1, OPTAB_DIRECT);
13287 current_function_uses_pic_offset_table = 1;
13154 code = PLUS;
13155 op0 = operands[0];
13156 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13157 }
13158 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13159 {
13160 code = PLUS;
13161 op0 = operands[0];
13162 op1 = pic_offset_table_rtx;
13163 }
13164 else
13165 {
13291 operands[0] = expand_simple_binop (Pmode, MINUS, pic_offset_table_rtx,
13292 operands[0], NULL_RTX, 1,
13293 OPTAB_DIRECT);
13294 current_function_uses_pic_offset_table = 1;
13166 code = MINUS;
13167 op0 = pic_offset_table_rtx;
13168 op1 = operands[0];
13169 }
13170
13171 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13172 OPTAB_DIRECT);
13173 }
13174})
13175
13176(define_insn "*tablejump_1"
13177 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13178 (use (label_ref (match_operand 1 "" "")))]
13179 "!TARGET_64BIT"
13180 "jmp\t%A0"

--- 48 unchanged lines hidden (view full) ---

13229 if (which_alternative != 0)
13230 return "#";
13231 if (get_attr_length (insn) == 2)
13232 return "%+loop\t%l0";
13233 else
13234 return "dec{l}\t%1\;%+jne\t%l0";
13235}
13236 [(set_attr "ppro_uops" "many")
13360 (set (attr "type")
13237 (set (attr "length")
13238 (if_then_else (and (eq_attr "alternative" "0")
13239 (and (ge (minus (match_dup 0) (pc))
13363 (const_int -128))
13240 (const_int -126))
13241 (lt (minus (match_dup 0) (pc))
13365 (const_int 124))))
13366 (const_string "ibr")
13367 (const_string "multi")))])
13242 (const_int 128))))
13243 (const_int 2)
13244 (const_int 16)))
13245 ;; We don't know the type before shorten branches. Optimistically expect
13246 ;; the loop instruction to match.
13247 (set (attr "type") (const_string "ibr"))])
13248
13249(define_split
13250 [(set (pc)
13251 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13252 (const_int 1))
13253 (match_operand 0 "" "")
13254 (pc)))
13255 (set (match_dup 1)

--- 93 unchanged lines hidden (view full) ---

13349(define_expand "call_pop"
13350 [(parallel [(call (match_operand:QI 0 "" "")
13351 (match_operand:SI 1 "" ""))
13352 (set (reg:SI 7)
13353 (plus:SI (reg:SI 7)
13354 (match_operand:SI 3 "" "")))])]
13355 "!TARGET_64BIT"
13356{
13477 if (operands[3] == const0_rtx)
13478 {
13479 emit_insn (gen_call (operands[0], operands[1], constm1_rtx));
13480 DONE;
13481 }
13482 /* Static functions and indirect calls don't need
13483 current_function_uses_pic_offset_table. */
13484 if (flag_pic
13485 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
13486 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
13487 current_function_uses_pic_offset_table = 1;
13488 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
13489 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
13490 if (TARGET_64BIT)
13491 abort();
13357 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3]);
13358 DONE;
13359})
13360
13361(define_insn "*call_pop_0"
13362 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13363 (match_operand:SI 1 "" ""))
13364 (set (reg:SI 7) (plus:SI (reg:SI 7)
13365 (match_operand:SI 2 "immediate_operand" "")))]
13366 "!TARGET_64BIT"

--- 25 unchanged lines hidden (view full) ---

13392 return "call\t%A0";
13393}
13394 [(set_attr "type" "call")])
13395
13396(define_expand "call"
13397 [(call (match_operand:QI 0 "" "")
13398 (match_operand 1 "" ""))
13399 (use (match_operand 2 "" ""))]
13533 ;; Operand 1 not used on the i386.
13400 ""
13401{
13536 rtx insn;
13537 /* Static functions and indirect calls don't need
13538 current_function_uses_pic_offset_table. */
13539 if (flag_pic
13540 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
13541 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
13542 current_function_uses_pic_offset_table = 1;
13543
13544 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
13545 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
13546 if (TARGET_64BIT && INTVAL (operands[2]) >= 0)
13547 {
13548 rtx reg = gen_rtx_REG (QImode, 0);
13549 emit_move_insn (reg, operands[2]);
13550 insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
13551 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
13552 DONE;
13553 }
13554 insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
13555 DONE;
13402 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL);
13403 DONE;
13404})
13405
13558(define_expand "call_exp"
13559 [(call (match_operand:QI 0 "" "")
13560 (match_operand 1 "" ""))]
13561 ""
13562 "")
13563
13406(define_insn "*call_0"
13407 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13408 (match_operand 1 "" ""))]
13409 ""
13410{
13411 if (SIBLING_CALL_P (insn))
13412 return "jmp\t%P0";
13413 else

--- 35 unchanged lines hidden (view full) ---

13449 if (SIBLING_CALL_P (insn))
13450 return "jmp\t%A0";
13451 else
13452 return "call\t%A0";
13453}
13454 [(set_attr "type" "call")])
13455
13456;; Call subroutine, returning value in operand 0
13615;; (which must be a hard register).
13457
13458(define_expand "call_value_pop"
13459 [(parallel [(set (match_operand 0 "" "")
13460 (call (match_operand:QI 1 "" "")
13461 (match_operand:SI 2 "" "")))
13462 (set (reg:SI 7)
13463 (plus:SI (reg:SI 7)
13464 (match_operand:SI 4 "" "")))])]
13465 "!TARGET_64BIT"
13466{
13626 if (operands[4] == const0_rtx)
13627 {
13628 emit_insn (gen_call_value (operands[0], operands[1], operands[2],
13629 constm1_rtx));
13630 DONE;
13631 }
13632 /* Static functions and indirect calls don't need
13633 current_function_uses_pic_offset_table. */
13634 if (flag_pic
13635 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13636 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
13637 current_function_uses_pic_offset_table = 1;
13638 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
13639 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
13467 ix86_expand_call (operands[0], operands[1], operands[2],
13468 operands[3], operands[4]);
13469 DONE;
13470})
13471
13472(define_expand "call_value"
13473 [(set (match_operand 0 "" "")
13474 (call (match_operand:QI 1 "" "")
13475 (match_operand:SI 2 "" "")))
13476 (use (match_operand:SI 3 "" ""))]
13477 ;; Operand 2 not used on the i386.
13478 ""
13479{
13650 rtx insn;
13651 /* Static functions and indirect calls don't need
13652 current_function_uses_pic_offset_table. */
13653 if (flag_pic
13654 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13655 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
13656 current_function_uses_pic_offset_table = 1;
13657 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
13658 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
13659 if (TARGET_64BIT && INTVAL (operands[3]) >= 0)
13660 {
13661 rtx reg = gen_rtx_REG (QImode, 0);
13662 emit_move_insn (reg, operands[3]);
13663 insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
13664 operands[2]));
13665 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
13666 DONE;
13667 }
13668 insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
13669 operands[2]));
13480 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL);
13481 DONE;
13482})
13483
13673(define_expand "call_value_exp"
13674 [(set (match_operand 0 "" "")
13675 (call (match_operand:QI 1 "" "")
13676 (match_operand:SI 2 "" "")))]
13677 ""
13678 "")
13679
13484;; Call subroutine returning any type.
13485
13486(define_expand "untyped_call"
13487 [(parallel [(call (match_operand 0 "" "")
13488 (const_int 0))
13489 (match_operand 1 "" "")
13490 (match_operand 2 "" "")])]
13491 ""
13492{
13493 int i;
13494
13495 /* In order to give reg-stack an easier job in validating two
13496 coprocessor registers as containing a possible return value,
13497 simply pretend the untyped call returns a complex long double
13498 value. */
13499
13696 emit_call_insn (TARGET_FLOAT_RETURNS_IN_80387
13697 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
13698 operands[0], const0_rtx,
13699 GEN_INT (SSE_REGPARM_MAX - 1))
13700 : gen_call (operands[0], const0_rtx,
13701 GEN_INT (SSE_REGPARM_MAX - 1)));
13500 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
13501 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
13502 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
13503 NULL);
13504
13505 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13506 {
13507 rtx set = XVECEXP (operands[2], 0, i);
13508 emit_move_insn (SET_DEST (set), SET_SRC (set));
13509 }
13510
13511 /* The optimizer does not know that the call sets the function value
13512 registers we stored in the result block. We avoid problems by
13513 claiming that all hard registers are used and clobbered at this
13514 point. */
13713 emit_insn (gen_blockage ());
13515 emit_insn (gen_blockage (const0_rtx));
13516
13517 DONE;
13518})
13519
13520;; Prologue and epilogue instructions
13521
13522;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13523;; all of memory. This blocks insns from being moved across this point.
13524
13525(define_insn "blockage"
13724 [(unspec_volatile [(const_int 0)] 0)]
13526 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
13527 ""
13528 ""
13529 [(set_attr "length" "0")])
13530
13531;; Insn emitted into the body of a function to return from a function.
13532;; This is only done if the function's epilogue is known to be simple.
13533;; See comments for ix86_can_use_return_insn_p in i386.c.
13534

--- 43 unchanged lines hidden (view full) ---

13578 (set_attr "modrm" "0")
13579 (set_attr "ppro_uops" "one")])
13580
13581(define_expand "prologue"
13582 [(const_int 1)]
13583 ""
13584 "ix86_expand_prologue (); DONE;")
13585
13784(define_insn "prologue_set_got"
13586(define_insn "set_got"
13587 [(set (match_operand:SI 0 "register_operand" "=r")
13786 (unspec_volatile:SI
13787 [(plus:SI (match_dup 0)
13788 (plus:SI (match_operand:SI 1 "symbolic_operand" "")
13789 (minus:SI (pc) (match_operand 2 "" ""))))] 1))
13588 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13589 (clobber (reg:CC 17))]
13590 "!TARGET_64BIT"
13792{
13793 if (GET_CODE (operands[2]) == LABEL_REF)
13794 operands[2] = XEXP (operands[2], 0);
13795 if (TARGET_DEEP_BRANCH_PREDICTION)
13796 return "add{l}\t{%1, %0|%0, %1}";
13797 else
13798 return "add{l}\t{%1+[.-%X2], %0|%0, %a1+(.-%X2)}";
13799}
13800 [(set_attr "type" "alu")
13801 ; Since this insn may have two constant operands, we must set the
13802 ; length manually.
13803 (set_attr "length_immediate" "4")
13804 (set_attr "mode" "SI")])
13591 { return output_set_got (operands[0]); }
13592 [(set_attr "type" "multi")
13593 (set_attr "length" "12")])
13594
13806(define_insn "prologue_get_pc"
13807 [(set (match_operand:SI 0 "register_operand" "=r")
13808 (unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
13809 "!TARGET_64BIT"
13810{
13811 if (GET_CODE (operands[1]) == LABEL_REF)
13812 operands[1] = XEXP (operands[1], 0);
13813 output_asm_insn ("call\t%X1", operands);
13814 if (! TARGET_DEEP_BRANCH_PREDICTION)
13815 {
13816 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
13817 CODE_LABEL_NUMBER (operands[1]));
13818 return "pop{l}\t%0";
13819 }
13820 RET;
13821}
13822 [(set_attr "type" "multi")])
13823
13595(define_expand "epilogue"
13596 [(const_int 1)]
13597 ""
13598 "ix86_expand_epilogue (1); DONE;")
13599
13600(define_expand "sibcall_epilogue"
13601 [(const_int 1)]
13602 ""
13603 "ix86_expand_epilogue (0); DONE;")
13604
13605(define_expand "eh_return"
13835 [(use (match_operand 0 "register_operand" ""))
13836 (use (match_operand 1 "register_operand" ""))]
13606 [(use (match_operand 0 "register_operand" ""))]
13607 ""
13608{
13839 rtx tmp, sa = operands[0], ra = operands[1];
13609 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
13610
13611 /* Tricky bit: we write the address of the handler to which we will
13612 be returning into someone else's stack frame, one word below the
13613 stack address we wish to restore. */
13614 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13615 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13616 tmp = gen_rtx_MEM (Pmode, tmp);
13617 emit_move_insn (tmp, ra);
13618
13619 if (Pmode == SImode)
13620 emit_insn (gen_eh_return_si (sa));
13621 else
13622 emit_insn (gen_eh_return_di (sa));
13623 emit_barrier ();
13624 DONE;
13625})
13626
13627(define_insn_and_split "eh_return_si"
13858 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")] 13)]
13628 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")]
13629 UNSPECV_EH_RETURN)]
13630 "!TARGET_64BIT"
13631 "#"
13632 "reload_completed"
13633 [(const_int 1)]
13634 "ix86_expand_epilogue (2); DONE;")
13635
13636(define_insn_and_split "eh_return_di"
13866 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 13)]
13637 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
13638 UNSPECV_EH_RETURN)]
13639 "TARGET_64BIT"
13640 "#"
13641 "reload_completed"
13642 [(const_int 1)]
13643 "ix86_expand_epilogue (2); DONE;")
13644
13645(define_insn "leave"
13646 [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4)))
13647 (set (reg:SI 6) (mem:SI (reg:SI 6)))
13648 (clobber (mem:BLK (scratch)))]
13649 "!TARGET_64BIT"
13650 "leave"
13651 [(set_attr "length_immediate" "0")
13652 (set_attr "length" "1")
13653 (set_attr "modrm" "0")
13882 (set_attr "modrm" "0")
13654 (set_attr "athlon_decode" "vector")
13655 (set_attr "ppro_uops" "few")])
13656
13657(define_insn "leave_rex64"
13658 [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8)))
13659 (set (reg:DI 6) (mem:DI (reg:DI 6)))
13660 (clobber (mem:BLK (scratch)))]
13661 "TARGET_64BIT"
13662 "leave"
13663 [(set_attr "length_immediate" "0")
13664 (set_attr "length" "1")
13665 (set_attr "modrm" "0")
13895 (set_attr "modrm" "0")
13666 (set_attr "athlon_decode" "vector")
13667 (set_attr "ppro_uops" "few")])
13668
13669(define_expand "ffssi2"
13670 [(set (match_operand:SI 0 "nonimmediate_operand" "")
13901 (ffs:SI (match_operand:SI 1 "general_operand" "")))]
13671 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
13672 ""
13673{
13674 rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
13675 rtx in = operands[1];
13676
13677 if (TARGET_CMOVE)
13678 {
13679 emit_move_insn (tmp, constm1_rtx);

--- 72 unchanged lines hidden (view full) ---

13752 DONE;
13753})
13754
13755(define_insn "ffssi_1"
13756 [(set (reg:CCZ 17)
13757 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
13758 (const_int 0)))
13759 (set (match_operand:SI 0 "register_operand" "=r")
13990 (unspec:SI [(match_dup 1)] 5))]
13760 (unspec:SI [(match_dup 1)] UNSPEC_BSF))]
13761 ""
13762 "bsf{l}\t{%1, %0|%0, %1}"
13763 [(set_attr "prefix_0f" "1")
13764 (set_attr "ppro_uops" "few")])
13765
13766;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger
13767;; and slower than the two-byte movzx insn needed to do the work in SImode.
13768
13769;; Thread-local storage patterns for ELF.
13770;;
13771;; Note that these code sequences must appear exactly as shown
13772;; in order to allow linker relaxation.
13773
13774(define_insn "*tls_global_dynamic_32_gnu"
13775 [(set (match_operand:SI 0 "register_operand" "=a")
13776 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13777 (match_operand:SI 2 "tls_symbolic_operand" "")
13778 (match_operand:SI 3 "call_insn_operand" "")]
13779 UNSPEC_TLS_GD))
13780 (clobber (match_scratch:SI 4 "=d"))
13781 (clobber (match_scratch:SI 5 "=c"))
13782 (clobber (reg:CC 17))]
13783 "!TARGET_64BIT && TARGET_GNU_TLS"
13784 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
13785 [(set_attr "type" "multi")
13786 (set_attr "length" "12")])
13787
13788(define_insn "*tls_global_dynamic_32_sun"
13789 [(set (match_operand:SI 0 "register_operand" "=a")
13790 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13791 (match_operand:SI 2 "tls_symbolic_operand" "")
13792 (match_operand:SI 3 "call_insn_operand" "")]
13793 UNSPEC_TLS_GD))
13794 (clobber (match_scratch:SI 4 "=d"))
13795 (clobber (match_scratch:SI 5 "=c"))
13796 (clobber (reg:CC 17))]
13797 "!TARGET_64BIT && TARGET_SUN_TLS"
13798 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
13799 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
13800 [(set_attr "type" "multi")
13801 (set_attr "length" "14")])
13802
13803(define_expand "tls_global_dynamic_32"
13804 [(parallel [(set (match_operand:SI 0 "register_operand" "")
13805 (unspec:SI
13806 [(match_dup 2)
13807 (match_operand:SI 1 "tls_symbolic_operand" "")
13808 (match_dup 3)]
13809 UNSPEC_TLS_GD))
13810 (clobber (match_scratch:SI 4 ""))
13811 (clobber (match_scratch:SI 5 ""))
13812 (clobber (reg:CC 17))])]
13813 ""
13814{
13815 if (flag_pic)
13816 operands[2] = pic_offset_table_rtx;
13817 else
13818 {
13819 operands[2] = gen_reg_rtx (Pmode);
13820 emit_insn (gen_set_got (operands[2]));
13821 }
13822 operands[3] = ix86_tls_get_addr ();
13823})
13824
13825(define_insn "*tls_global_dynamic_64"
13826 [(set (match_operand:DI 0 "register_operand" "=a")
13827 (call (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
13828 (match_operand:DI 3 "" "")))
13829 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
13830 UNSPEC_TLS_GD)]
13831 "TARGET_64BIT"
13832 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
13833 [(set_attr "type" "multi")
13834 (set_attr "length" "16")])
13835
13836(define_expand "tls_global_dynamic_64"
13837 [(parallel [(set (match_operand:DI 0 "register_operand" "")
13838 (call (mem:QI (match_dup 2)) (const_int 0)))
13839 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
13840 UNSPEC_TLS_GD)])]
13841 ""
13842{
13843 operands[2] = ix86_tls_get_addr ();
13844})
13845
13846(define_insn "*tls_local_dynamic_base_32_gnu"
13847 [(set (match_operand:SI 0 "register_operand" "=a")
13848 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13849 (match_operand:SI 2 "call_insn_operand" "")]
13850 UNSPEC_TLS_LD_BASE))
13851 (clobber (match_scratch:SI 3 "=d"))
13852 (clobber (match_scratch:SI 4 "=c"))
13853 (clobber (reg:CC 17))]
13854 "!TARGET_64BIT && TARGET_GNU_TLS"
13855 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
13856 [(set_attr "type" "multi")
13857 (set_attr "length" "11")])
13858
13859(define_insn "*tls_local_dynamic_base_32_sun"
13860 [(set (match_operand:SI 0 "register_operand" "=a")
13861 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13862 (match_operand:SI 2 "call_insn_operand" "")]
13863 UNSPEC_TLS_LD_BASE))
13864 (clobber (match_scratch:SI 3 "=d"))
13865 (clobber (match_scratch:SI 4 "=c"))
13866 (clobber (reg:CC 17))]
13867 "!TARGET_64BIT && TARGET_SUN_TLS"
13868 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
13869 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
13870 [(set_attr "type" "multi")
13871 (set_attr "length" "13")])
13872
13873(define_expand "tls_local_dynamic_base_32"
13874 [(parallel [(set (match_operand:SI 0 "register_operand" "")
13875 (unspec:SI [(match_dup 1) (match_dup 2)]
13876 UNSPEC_TLS_LD_BASE))
13877 (clobber (match_scratch:SI 3 ""))
13878 (clobber (match_scratch:SI 4 ""))
13879 (clobber (reg:CC 17))])]
13880 ""
13881{
13882 if (flag_pic)
13883 operands[1] = pic_offset_table_rtx;
13884 else
13885 {
13886 operands[1] = gen_reg_rtx (Pmode);
13887 emit_insn (gen_set_got (operands[1]));
13888 }
13889 operands[2] = ix86_tls_get_addr ();
13890})
13891
13892(define_insn "*tls_local_dynamic_base_64"
13893 [(set (match_operand:DI 0 "register_operand" "=a")
13894 (call (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
13895 (match_operand:DI 2 "" "")))
13896 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
13897 "TARGET_64BIT"
13898 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
13899 [(set_attr "type" "multi")
13900 (set_attr "length" "12")])
13901
13902(define_expand "tls_local_dynamic_base_64"
13903 [(parallel [(set (match_operand:DI 0 "register_operand" "")
13904 (call (mem:QI (match_dup 1)) (const_int 0)))
13905 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
13906 ""
13907{
13908 operands[1] = ix86_tls_get_addr ();
13909})
13910
13911;; Local dynamic of a single variable is a lose. Show combine how
13912;; to convert that back to global dynamic.
13913
13914(define_insn_and_split "*tls_local_dynamic_32_once"
13915 [(set (match_operand:SI 0 "register_operand" "=a")
13916 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13917 (match_operand:SI 2 "call_insn_operand" "")]
13918 UNSPEC_TLS_LD_BASE)
13919 (const:SI (unspec:SI
13920 [(match_operand:SI 3 "tls_symbolic_operand" "")]
13921 UNSPEC_DTPOFF))))
13922 (clobber (match_scratch:SI 4 "=d"))
13923 (clobber (match_scratch:SI 5 "=c"))
13924 (clobber (reg:CC 17))]
13925 ""
13926 "#"
13927 ""
13928 [(parallel [(set (match_dup 0)
13929 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
13930 UNSPEC_TLS_GD))
13931 (clobber (match_dup 4))
13932 (clobber (match_dup 5))
13933 (clobber (reg:CC 17))])]
13934 "")
13935
13936;; These patterns match the binary 387 instructions for addM3, subM3,
13937;; mulM3 and divM3. There are three patterns for each of DFmode and
13938;; SFmode. The first is the normal insn, the second the same insn but
13939;; with one operand a conversion, and the third the same insn but with
13940;; the other operand a conversion. The conversion may be SFmode or
13941;; SImode if the target mode DFmode, but only SImode if the target mode
13942;; is SFmode.
13943

--- 20 unchanged lines hidden (view full) ---

13964 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
13965 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
13966 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
13967 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13968 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13969 "* return output_387_binary_op (insn, operands);"
13970 [(set (attr "type")
13971 (if_then_else (eq_attr "alternative" "1")
14035 (const_string "sse")
13972 (if_then_else (match_operand:SF 3 "mult_operator" "")
13973 (const_string "ssemul")
13974 (const_string "sseadd"))
13975 (if_then_else (match_operand:SF 3 "mult_operator" "")
13976 (const_string "fmul")
13977 (const_string "fop"))))
13978 (set_attr "mode" "SF")])
13979
13980(define_insn "*fop_sf_comm_sse"
13981 [(set (match_operand:SF 0 "register_operand" "=x")
13982 (match_operator:SF 3 "binary_fp_operator"
13983 [(match_operand:SF 1 "nonimmediate_operand" "%0")
13984 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13985 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13986 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13987 "* return output_387_binary_op (insn, operands);"
14049 [(set_attr "type" "sse")
13988 [(set (attr "type")
13989 (if_then_else (match_operand:SF 3 "mult_operator" "")
13990 (const_string "ssemul")
13991 (const_string "sseadd")))
13992 (set_attr "mode" "SF")])
13993
13994(define_insn "*fop_df_comm_nosse"
13995 [(set (match_operand:DF 0 "register_operand" "=f")
13996 (match_operator:DF 3 "binary_fp_operator"
13997 [(match_operand:DF 1 "nonimmediate_operand" "%0")
13998 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
13999 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)

--- 12 unchanged lines hidden (view full) ---

14012 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
14013 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14014 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
14015 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14016 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14017 "* return output_387_binary_op (insn, operands);"
14018 [(set (attr "type")
14019 (if_then_else (eq_attr "alternative" "1")
14078 (const_string "sse")
14020 (if_then_else (match_operand:SF 3 "mult_operator" "")
14021 (const_string "ssemul")
14022 (const_string "sseadd"))
14023 (if_then_else (match_operand:SF 3 "mult_operator" "")
14024 (const_string "fmul")
14025 (const_string "fop"))))
14026 (set_attr "mode" "DF")])
14027
14028(define_insn "*fop_df_comm_sse"
14029 [(set (match_operand:DF 0 "register_operand" "=Y")
14030 (match_operator:DF 3 "binary_fp_operator"
14031 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14032 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14033 "TARGET_SSE2 && TARGET_SSE_MATH
14034 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14035 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14036 "* return output_387_binary_op (insn, operands);"
14093 [(set_attr "type" "sse")
14037 [(set (attr "type")
14038 (if_then_else (match_operand:SF 3 "mult_operator" "")
14039 (const_string "ssemul")
14040 (const_string "sseadd")))
14041 (set_attr "mode" "DF")])
14042
14043(define_insn "*fop_xf_comm"
14044 [(set (match_operand:XF 0 "register_operand" "=f")
14045 (match_operator:XF 3 "binary_fp_operator"
14046 [(match_operand:XF 1 "register_operand" "%0")
14047 (match_operand:XF 2 "register_operand" "f")]))]
14048 "!TARGET_64BIT && TARGET_80387

--- 41 unchanged lines hidden (view full) ---

14090 (match_operator:SF 3 "binary_fp_operator"
14091 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14092 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14093 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14094 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14095 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14096 "* return output_387_binary_op (insn, operands);"
14097 [(set (attr "type")
14151 (cond [(eq_attr "alternative" "2")
14152 (const_string "sse")
14098 (cond [(and (eq_attr "alternative" "2")
14099 (match_operand:SF 3 "mult_operator" ""))
14100 (const_string "ssemul")
14101 (and (eq_attr "alternative" "2")
14102 (match_operand:SF 3 "div_operator" ""))
14103 (const_string "ssediv")
14104 (eq_attr "alternative" "2")
14105 (const_string "sseadd")
14106 (match_operand:SF 3 "mult_operator" "")
14107 (const_string "fmul")
14108 (match_operand:SF 3 "div_operator" "")
14109 (const_string "fdiv")
14110 ]
14111 (const_string "fop")))
14112 (set_attr "mode" "SF")])
14113
14114(define_insn "*fop_sf_1_sse"
14115 [(set (match_operand:SF 0 "register_operand" "=x")
14116 (match_operator:SF 3 "binary_fp_operator"
14117 [(match_operand:SF 1 "register_operand" "0")
14118 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14119 "TARGET_SSE_MATH
14120 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14121 "* return output_387_binary_op (insn, operands);"
14169 [(set_attr "type" "sse")
14122 [(set (attr "type")
14123 (cond [(match_operand:SF 3 "mult_operator" "")
14124 (const_string "ssemul")
14125 (match_operand:SF 3 "div_operator" "")
14126 (const_string "ssediv")
14127 ]
14128 (const_string "sseadd")))
14129 (set_attr "mode" "SF")])
14130
14131;; ??? Add SSE splitters for these!
14132(define_insn "*fop_sf_2"
14133 [(set (match_operand:SF 0 "register_operand" "=f,f")
14134 (match_operator:SF 3 "binary_fp_operator"
14135 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14136 (match_operand:SF 2 "register_operand" "0,0")]))]

--- 35 unchanged lines hidden (view full) ---

14172 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14173 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14174 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14175 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14176 "* return output_387_binary_op (insn, operands);"
14177 [(set (attr "type")
14178 (cond [(match_operand:DF 3 "mult_operator" "")
14179 (const_string "fmul")
14221 (match_operand:DF 3 "div_operator" "")
14180 (match_operand:DF 3 "div_operator" "")
14181 (const_string "fdiv")
14182 ]
14183 (const_string "fop")))
14184 (set_attr "mode" "DF")])
14185
14186
14187(define_insn "*fop_df_1"
14188 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14189 (match_operator:DF 3 "binary_fp_operator"
14190 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14191 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14192 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14193 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14194 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14195 "* return output_387_binary_op (insn, operands);"
14196 [(set (attr "type")
14238 (cond [(eq_attr "alternative" "2")
14239 (const_string "sse")
14197 (cond [(and (eq_attr "alternative" "2")
14198 (match_operand:SF 3 "mult_operator" ""))
14199 (const_string "ssemul")
14200 (and (eq_attr "alternative" "2")
14201 (match_operand:SF 3 "div_operator" ""))
14202 (const_string "ssediv")
14203 (eq_attr "alternative" "2")
14204 (const_string "sseadd")
14205 (match_operand:DF 3 "mult_operator" "")
14206 (const_string "fmul")
14207 (match_operand:DF 3 "div_operator" "")
14208 (const_string "fdiv")
14209 ]
14210 (const_string "fop")))
14211 (set_attr "mode" "DF")])
14212
14213(define_insn "*fop_df_1_sse"
14214 [(set (match_operand:DF 0 "register_operand" "=Y")
14215 (match_operator:DF 3 "binary_fp_operator"
14216 [(match_operand:DF 1 "register_operand" "0")
14217 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14218 "TARGET_SSE2 && TARGET_SSE_MATH
14219 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14220 "* return output_387_binary_op (insn, operands);"
14256 [(set_attr "type" "sse")])
14221 [(set_attr "mode" "DF")
14222 (set (attr "type")
14223 (cond [(match_operand:SF 3 "mult_operator" "")
14224 (const_string "ssemul")
14225 (match_operand:SF 3 "div_operator" "")
14226 (const_string "ssediv")
14227 ]
14228 (const_string "sseadd")))])
14229
14230;; ??? Add SSE splitters for these!
14231(define_insn "*fop_df_2"
14232 [(set (match_operand:DF 0 "register_operand" "=f,f")
14233 (match_operator:DF 3 "binary_fp_operator"
14234 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14235 (match_operand:DF 2 "register_operand" "0,0")]))]
14236 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"

--- 490 unchanged lines hidden (view full) ---

14727 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14728 "fsqrt"
14729 [(set_attr "type" "fpspc")
14730 (set_attr "mode" "XF")
14731 (set_attr "athlon_decode" "direct")])
14732
14733(define_insn "sindf2"
14734 [(set (match_operand:DF 0 "register_operand" "=f")
14763 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
14735 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
14736 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14737 && flag_unsafe_math_optimizations"
14738 "fsin"
14739 [(set_attr "type" "fpspc")
14740 (set_attr "mode" "DF")])
14741
14742(define_insn "sinsf2"
14743 [(set (match_operand:SF 0 "register_operand" "=f")
14772 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
14744 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
14745 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14746 && flag_unsafe_math_optimizations"
14747 "fsin"
14748 [(set_attr "type" "fpspc")
14749 (set_attr "mode" "SF")])
14750
14751(define_insn "*sinextendsfdf2"
14752 [(set (match_operand:DF 0 "register_operand" "=f")
14753 (unspec:DF [(float_extend:DF
14782 (match_operand:SF 1 "register_operand" "0"))] 1))]
14754 (match_operand:SF 1 "register_operand" "0"))]
14755 UNSPEC_SIN))]
14756 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14757 && flag_unsafe_math_optimizations"
14758 "fsin"
14759 [(set_attr "type" "fpspc")
14760 (set_attr "mode" "DF")])
14761
14762(define_insn "sinxf2"
14763 [(set (match_operand:XF 0 "register_operand" "=f")
14791 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
14764 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
14765 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14766 && flag_unsafe_math_optimizations"
14767 "fsin"
14768 [(set_attr "type" "fpspc")
14769 (set_attr "mode" "XF")])
14770
14771(define_insn "sintf2"
14772 [(set (match_operand:TF 0 "register_operand" "=f")
14800 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))]
14773 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))]
14774 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14775 && flag_unsafe_math_optimizations"
14776 "fsin"
14777 [(set_attr "type" "fpspc")
14778 (set_attr "mode" "XF")])
14779
14780(define_insn "cosdf2"
14781 [(set (match_operand:DF 0 "register_operand" "=f")
14809 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
14782 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
14783 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14784 && flag_unsafe_math_optimizations"
14785 "fcos"
14786 [(set_attr "type" "fpspc")
14787 (set_attr "mode" "DF")])
14788
14789(define_insn "cossf2"
14790 [(set (match_operand:SF 0 "register_operand" "=f")
14818 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
14791 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
14792 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14793 && flag_unsafe_math_optimizations"
14794 "fcos"
14795 [(set_attr "type" "fpspc")
14796 (set_attr "mode" "SF")])
14797
14798(define_insn "*cosextendsfdf2"
14799 [(set (match_operand:DF 0 "register_operand" "=f")
14800 (unspec:DF [(float_extend:DF
14828 (match_operand:SF 1 "register_operand" "0"))] 2))]
14801 (match_operand:SF 1 "register_operand" "0"))]
14802 UNSPEC_COS))]
14803 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14804 && flag_unsafe_math_optimizations"
14805 "fcos"
14806 [(set_attr "type" "fpspc")
14807 (set_attr "mode" "DF")])
14808
14809(define_insn "cosxf2"
14810 [(set (match_operand:XF 0 "register_operand" "=f")
14837 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))]
14838 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14811 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
14812 "!TARGET_64BIT && ! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14813 && flag_unsafe_math_optimizations"
14814 "fcos"
14815 [(set_attr "type" "fpspc")
14816 (set_attr "mode" "XF")])
14817
14818(define_insn "costf2"
14819 [(set (match_operand:TF 0 "register_operand" "=f")
14846 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 2))]
14820 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))]
14821 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14822 && flag_unsafe_math_optimizations"
14823 "fcos"
14824 [(set_attr "type" "fpspc")
14825 (set_attr "mode" "XF")])
14826
14827;; Block operation instructions
14828

--- 877 unchanged lines hidden (view full) ---

15706 [(set_attr "type" "str")
15707 (set_attr "mode" "QI")
15708 (set_attr "prefix_rep" "1")])
15709
15710(define_expand "strlensi"
15711 [(set (match_operand:SI 0 "register_operand" "")
15712 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
15713 (match_operand:QI 2 "immediate_operand" "")
15740 (match_operand 3 "immediate_operand" "")] 0))]
15714 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
15715 ""
15716{
15717 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15718 DONE;
15719 else
15720 FAIL;
15721})
15722
15723(define_expand "strlendi"
15724 [(set (match_operand:DI 0 "register_operand" "")
15725 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
15726 (match_operand:QI 2 "immediate_operand" "")
15753 (match_operand 3 "immediate_operand" "")] 0))]
15727 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
15728 ""
15729{
15730 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15731 DONE;
15732 else
15733 FAIL;
15734})
15735
15736(define_insn "strlenqi_1"
15737 [(set (match_operand:SI 0 "register_operand" "=&c")
15738 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
15739 (match_operand:QI 2 "register_operand" "a")
15740 (match_operand:SI 3 "immediate_operand" "i")
15767 (match_operand:SI 4 "register_operand" "0")] 0))
15741 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
15742 (use (reg:SI 19))
15743 (clobber (match_operand:SI 1 "register_operand" "=D"))
15744 (clobber (reg:CC 17))]
15745 "!TARGET_64BIT"
15746 "repnz{\;| }scasb"
15747 [(set_attr "type" "str")
15748 (set_attr "mode" "QI")
15749 (set_attr "prefix_rep" "1")])
15750
15751(define_insn "strlenqi_rex_1"
15752 [(set (match_operand:DI 0 "register_operand" "=&c")
15753 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
15754 (match_operand:QI 2 "register_operand" "a")
15755 (match_operand:DI 3 "immediate_operand" "i")
15782 (match_operand:DI 4 "register_operand" "0")] 0))
15756 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
15757 (use (reg:SI 19))
15758 (clobber (match_operand:DI 1 "register_operand" "=D"))
15759 (clobber (reg:CC 17))]
15760 "TARGET_64BIT"
15761 "repnz{\;| }scasb"
15762 [(set_attr "type" "str")
15763 (set_attr "mode" "QI")
15764 (set_attr "prefix_rep" "1")])

--- 99 unchanged lines hidden (view full) ---

15864 (const_int -1)
15865 (const_int 0)))
15866 (clobber (reg:CC 17))]
15867 "TARGET_64BIT"
15868 "sbb{q}\t%0, %0"
15869 ; Since we don't have the proper number of operands for an alu insn,
15870 ; fill in all the blanks.
15871 [(set_attr "type" "alu")
15872 (set_attr "pent_pair" "pu")
15873 (set_attr "memory" "none")
15874 (set_attr "imm_disp" "false")
15875 (set_attr "mode" "DI")
15876 (set_attr "length_immediate" "0")])
15877
15878(define_insn "*movdicc_c_rex64"
15879 [(set (match_operand:DI 0 "register_operand" "=r,r")
15880 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"

--- 26 unchanged lines hidden (view full) ---

15907 (const_int -1)
15908 (const_int 0)))
15909 (clobber (reg:CC 17))]
15910 ""
15911 "sbb{l}\t%0, %0"
15912 ; Since we don't have the proper number of operands for an alu insn,
15913 ; fill in all the blanks.
15914 [(set_attr "type" "alu")
15915 (set_attr "pent_pair" "pu")
15916 (set_attr "memory" "none")
15917 (set_attr "imm_disp" "false")
15918 (set_attr "mode" "SI")
15919 (set_attr "length_immediate" "0")])
15920
15921(define_insn "*movsicc_noc"
15922 [(set (match_operand:SI 0 "register_operand" "=r,r")
15923 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"

--- 90 unchanged lines hidden (view full) ---

16014 fcmov%F1\t{%2, %0|%0, %2}
16015 fcmov%f1\t{%3, %0|%0, %3}
16016 cmov%O2%C1\t{%2, %0|%0, %2}
16017 cmov%O2%c1\t{%3, %0|%0, %3}"
16018 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16019 (set_attr "mode" "DF")])
16020
16021(define_split
16046 [(set (match_operand:DF 0 "register_operand" "")
16022 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
16023 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16024 [(match_operand 4 "" "") (const_int 0)])
16025 (match_operand:DF 2 "nonimmediate_operand" "")
16026 (match_operand:DF 3 "nonimmediate_operand" "")))]
16051 "!TARGET_64BIT && !ANY_FP_REG_P (operands[0]) && reload_completed"
16027 "!TARGET_64BIT && reload_completed"
16028 [(set (match_dup 2)
16029 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16030 (match_dup 5)
16031 (match_dup 7)))
16032 (set (match_dup 3)
16033 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16034 (match_dup 6)
16035 (match_dup 8)))]

--- 91 unchanged lines hidden (view full) ---

16127 (if_then_else:SF (lt (match_dup 1)
16128 (match_dup 2))
16129 (match_dup 1)
16130 (match_dup 2)))])
16131
16132;; We can't represent the LT test directly. Do this by swapping the operands.
16133
16134(define_split
16159 [(set (match_operand:SF 0 "register_operand" "")
16135 [(set (match_operand:SF 0 "fp_register_operand" "")
16136 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16137 (match_operand:SF 2 "register_operand" ""))
16138 (match_operand:SF 3 "register_operand" "")
16139 (match_operand:SF 4 "register_operand" "")))
16140 (clobber (reg:CC 17))]
16165 "FP_REG_P (operands[0]) && reload_completed
16141 "reload_completed
16142 && ((operands_match_p (operands[1], operands[3])
16143 && operands_match_p (operands[2], operands[4]))
16144 || (operands_match_p (operands[1], operands[4])
16145 && operands_match_p (operands[2], operands[3])))"
16146 [(set (reg:CCFP 17)
16147 (compare:CCFP (match_dup 2)
16148 (match_dup 1)))
16149 (set (match_dup 0)

--- 59 unchanged lines hidden (view full) ---

16209 [(set (match_dup 0)
16210 (if_then_else:DF (lt (match_dup 1)
16211 (match_dup 2))
16212 (match_dup 1)
16213 (match_dup 2)))])
16214
16215;; We can't represent the LT test directly. Do this by swapping the operands.
16216(define_split
16241 [(set (match_operand:DF 0 "register_operand" "")
16217 [(set (match_operand:DF 0 "fp_register_operand" "")
16218 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16219 (match_operand:DF 2 "register_operand" ""))
16220 (match_operand:DF 3 "register_operand" "")
16221 (match_operand:DF 4 "register_operand" "")))
16222 (clobber (reg:CC 17))]
16247 "FP_REG_P (operands[0]) && reload_completed
16223 "reload_completed
16224 && ((operands_match_p (operands[1], operands[3])
16225 && operands_match_p (operands[2], operands[4]))
16226 || (operands_match_p (operands[1], operands[4])
16227 && operands_match_p (operands[2], operands[3])))"
16228 [(set (reg:CCFP 17)
16229 (compare:CCFP (match_dup 2)
16230 (match_dup 2)))
16231 (set (match_dup 0)

--- 58 unchanged lines hidden (view full) ---

16290 && operands_match_p (operands[2], operands[3])))"
16291 [(set (match_dup 0)
16292 (if_then_else:SF (gt (match_dup 1)
16293 (match_dup 2))
16294 (match_dup 1)
16295 (match_dup 2)))])
16296
16297(define_split
16322 [(set (match_operand:SF 0 "register_operand" "")
16298 [(set (match_operand:SF 0 "fp_register_operand" "")
16299 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16300 (match_operand:SF 2 "register_operand" ""))
16301 (match_operand:SF 3 "register_operand" "")
16302 (match_operand:SF 4 "register_operand" "")))
16303 (clobber (reg:CC 17))]
16328 "FP_REG_P (operands[0]) && reload_completed
16304 "reload_completed
16305 && ((operands_match_p (operands[1], operands[3])
16306 && operands_match_p (operands[2], operands[4]))
16307 || (operands_match_p (operands[1], operands[4])
16308 && operands_match_p (operands[2], operands[3])))"
16309 [(set (reg:CCFP 17)
16310 (compare:CCFP (match_dup 1)
16311 (match_dup 2)))
16312 (set (match_dup 0)

--- 58 unchanged lines hidden (view full) ---

16371 && operands_match_p (operands[2], operands[3])))"
16372 [(set (match_dup 0)
16373 (if_then_else:DF (gt (match_dup 1)
16374 (match_dup 2))
16375 (match_dup 1)
16376 (match_dup 2)))])
16377
16378(define_split
16403 [(set (match_operand:DF 0 "register_operand" "")
16379 [(set (match_operand:DF 0 "fp_register_operand" "")
16380 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16381 (match_operand:DF 2 "register_operand" ""))
16382 (match_operand:DF 3 "register_operand" "")
16383 (match_operand:DF 4 "register_operand" "")))
16384 (clobber (reg:CC 17))]
16409 "FP_REG_P (operands[0]) && reload_completed
16385 "reload_completed
16386 && ((operands_match_p (operands[1], operands[3])
16387 && operands_match_p (operands[2], operands[4]))
16388 || (operands_match_p (operands[1], operands[4])
16389 && operands_match_p (operands[2], operands[3])))"
16390 [(set (reg:CCFP 17)
16391 (compare:CCFP (match_dup 1)
16392 (match_dup 2)))
16393 (set (match_dup 0)

--- 205 unchanged lines hidden (view full) ---

16599 ix86_expand_fp_movcc (operands);
16600 DONE;
16601})
16602
16603;; Split SSE based conditional move into seqence:
16604;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
16605;; and op2, op0 - zero op2 if comparison was false
16606;; nand op0, op3 - load op3 to op0 if comparison was false
16631;; or op2, op0 - get the non-zero one into the result.
16607;; or op2, op0 - get the nonzero one into the result.
16608(define_split
16609 [(set (match_operand 0 "register_operand" "")
16610 (if_then_else (match_operator 1 "sse_comparison_operator"
16611 [(match_operand 4 "register_operand" "")
16612 (match_operand 5 "nonimmediate_operand" "")])
16613 (match_operand 2 "register_operand" "")
16614 (match_operand 3 "register_operand" "")))
16615 (clobber (match_operand 6 "" ""))

--- 99 unchanged lines hidden (view full) ---

16715 (match_operand:DF 2 "const0_operand" "X")
16716 (match_operand:DF 3 "register_operand" "Y")))]
16717 "TARGET_SSE2"
16718 "#")
16719
16720(define_split
16721 [(set (match_operand 0 "register_operand" "")
16722 (if_then_else (match_operator 1 "comparison_operator"
16747 [(match_operand 4 "register_operand" "")
16723 [(match_operand 4 "nonimmediate_operand" "")
16724 (match_operand 5 "nonimmediate_operand" "")])
16725 (match_operand 2 "nonmemory_operand" "")
16726 (match_operand 3 "nonmemory_operand" "")))]
16727 "SSE_REG_P (operands[0]) && reload_completed
16728 && (const0_operand (operands[2], GET_MODE (operands[0]))
16729 || const0_operand (operands[3], GET_MODE (operands[0])))"
16730 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
16731 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
16732 (subreg:TI (match_dup 7) 0)))]
16733{
16734 PUT_MODE (operands[1], GET_MODE (operands[0]));
16759 if (!sse_comparison_operator (operands[1], VOIDmode))
16735 if (!sse_comparison_operator (operands[1], VOIDmode)
16736 || !rtx_equal_p (operands[0], operands[4]))
16737 {
16738 rtx tmp = operands[5];
16739 operands[5] = operands[4];
16740 operands[4] = tmp;
16741 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
16742 }
16743 if (!rtx_equal_p (operands[0], operands[4]))
16744 abort ();
16745 if (const0_operand (operands[2], GET_MODE (operands[0])))
16746 {
16747 operands[7] = operands[3];
16748 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
16749 0));
16750 }
16751 else
16752 {

--- 9 unchanged lines hidden (view full) ---

16762 if (TARGET_64BIT)
16763 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
16764 else
16765 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
16766 DONE;
16767})
16768
16769(define_insn "allocate_stack_worker_1"
16791 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
16770 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
16771 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
16772 (clobber (match_dup 0))
16773 (clobber (reg:CC 17))]
16774 "!TARGET_64BIT && TARGET_STACK_PROBE"
16775 "call\t__alloca"
16776 [(set_attr "type" "multi")
16777 (set_attr "length" "5")])
16778
16779(define_insn "allocate_stack_worker_rex64"
16801 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] 3)
16780 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
16781 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
16782 (clobber (match_dup 0))
16783 (clobber (reg:CC 17))]
16784 "TARGET_64BIT && TARGET_STACK_PROBE"
16785 "call\t__alloca"
16786 [(set_attr "type" "multi")
16787 (set_attr "length" "5")])
16788

--- 20 unchanged lines hidden (view full) ---

16809 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
16810 DONE;
16811})
16812
16813(define_expand "builtin_setjmp_receiver"
16814 [(label_ref (match_operand 0 "" ""))]
16815 "!TARGET_64BIT && flag_pic"
16816{
16838 load_pic_register ();
16817 emit_insn (gen_set_got (pic_offset_table_rtx));
16818 DONE;
16819})
16820
16821;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
16822
16823(define_split
16824 [(set (match_operand 0 "register_operand" "")
16825 (match_operator 3 "promotable_binary_operator"
16826 [(match_operand 1 "register_operand" "")
16827 (match_operand 2 "aligned_operand" "")]))
16828 (clobber (reg:CC 17))]
16829 "! TARGET_PARTIAL_REG_STALL && reload_completed
16830 && ((GET_MODE (operands[0]) == HImode
16852 && (!optimize_size || GET_CODE (operands[2]) != CONST_INT
16831 && ((!optimize_size && !TARGET_FAST_PREFIX)
16832 || GET_CODE (operands[2]) != CONST_INT
16833 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
16834 || (GET_MODE (operands[0]) == QImode
16835 && (TARGET_PROMOTE_QImode || optimize_size)))"
16836 [(parallel [(set (match_dup 0)
16837 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16838 (clobber (reg:CC 17))])]
16839 "operands[0] = gen_lowpart (SImode, operands[0]);
16840 operands[1] = gen_lowpart (SImode, operands[1]);
16841 if (GET_CODE (operands[3]) != ASHIFT)
16842 operands[2] = gen_lowpart (SImode, operands[2]);
16843 PUT_MODE (operands[3], SImode);")
16844
16845; Promote the QImode tests, as i386 has encoding of the AND
16846; instruction with 32-bit sign-extended immediate and thus the
16847; instruction size is unchanged, except in the %eax case for
16848; which it is increased by one byte, hence the ! optimize_size.
16849(define_split
16850 [(set (reg 17)
16851 (compare (and (match_operand 1 "aligned_operand" "")
16852 (match_operand 2 "const_int_operand" ""))
16853 (const_int 0)))
16854 (set (match_operand 0 "register_operand" "")
16855 (and (match_dup 1) (match_dup 2)))]
16856 "! TARGET_PARTIAL_REG_STALL && reload_completed
16873 && ix86_match_ccmode (insn, CCNOmode)
16874 && (GET_MODE (operands[0]) == HImode
16875 || (GET_MODE (operands[0]) == QImode
16876 && (TARGET_PROMOTE_QImode || optimize_size)))"
16857 /* Ensure that the operand will remain sign-extended immediate. */
16858 && ix86_match_ccmode (insn, INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)
16859 && ! optimize_size
16860 && ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX)
16861 || (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))"
16862 [(parallel [(set (reg:CCNO 17)
16863 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
16864 (const_int 0)))
16865 (set (match_dup 0)
16866 (and:SI (match_dup 1) (match_dup 2)))])]
16867 "operands[2]
16883 = GEN_INT (trunc_int_for_mode (INTVAL (operands[2])
16884 & GET_MODE_MASK (GET_MODE (operands[0])),
16885 SImode));
16868 = gen_int_mode (INTVAL (operands[2])
16869 & GET_MODE_MASK (GET_MODE (operands[0])),
16870 SImode);
16871 operands[0] = gen_lowpart (SImode, operands[0]);
16872 operands[1] = gen_lowpart (SImode, operands[1]);")
16873
16874; Don't promote the QImode tests, as i386 doesn't have encoding of
16875; the TEST instruction with 32-bit sign-extended immediate and thus
16876; the instruction size would at least double, which is not what we
16877; want even with ! optimize_size.
16878(define_split
16879 [(set (reg 17)
16891 (compare (and (match_operand 0 "aligned_operand" "")
16892 (match_operand 1 "const_int_operand" ""))
16880 (compare (and (match_operand:HI 0 "aligned_operand" "")
16881 (match_operand:HI 1 "const_int_operand" ""))
16882 (const_int 0)))]
16883 "! TARGET_PARTIAL_REG_STALL && reload_completed
16895 && ix86_match_ccmode (insn, CCNOmode)
16896 && (GET_MODE (operands[0]) == HImode
16897 || (GET_MODE (operands[0]) == QImode
16898 && (TARGET_PROMOTE_QImode || optimize_size)))"
16884 /* Ensure that the operand will remain sign-extended immediate. */
16885 && ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)
16886 && ! TARGET_FAST_PREFIX
16887 && ! optimize_size"
16888 [(set (reg:CCNO 17)
16889 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
16890 (const_int 0)))]
16891 "operands[1]
16903 = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
16904 & GET_MODE_MASK (GET_MODE (operands[0])),
16905 SImode));
16892 = gen_int_mode (INTVAL (operands[1])
16893 & GET_MODE_MASK (GET_MODE (operands[0])),
16894 SImode);
16895 operands[0] = gen_lowpart (SImode, operands[0]);")
16896
16897(define_split
16898 [(set (match_operand 0 "register_operand" "")
16899 (neg (match_operand 1 "register_operand" "")))
16900 (clobber (reg:CC 17))]
16901 "! TARGET_PARTIAL_REG_STALL && reload_completed
16902 && (GET_MODE (operands[0]) == HImode

--- 233 unchanged lines hidden (view full) ---

17136
17137(define_peephole2
17138 [(set (reg 17)
17139 (compare (and:SI (match_operand:SI 0 "register_operand" "")
17140 (match_operand:SI 1 "immediate_operand" ""))
17141 (const_int 0)))]
17142 "ix86_match_ccmode (insn, CCNOmode)
17143 && (true_regnum (operands[0]) != 0
17155 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
17144 || (GET_CODE (operands[1]) == CONST_INT
17145 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
17146 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17147 [(parallel
17148 [(set (reg:CCNO 17)
17149 (compare:CCNO (and:SI (match_dup 0)
17150 (match_dup 1))
17151 (const_int 0)))
17152 (set (match_dup 0)
17153 (and:SI (match_dup 0) (match_dup 1)))])]

--- 206 unchanged lines hidden (view full) ---

17360 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
17361 (clobber (reg:CC 17))])]
17362 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17363
17364(define_peephole2
17365 [(set (match_operand:SI 0 "register_operand" "")
17366 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
17367 (match_operand:DI 2 "const_int_operand" "")) 0))]
17378 "exact_log2 (INTVAL (operands[1])) >= 0
17368 "exact_log2 (INTVAL (operands[2])) >= 0
17369 && REGNO (operands[0]) == REGNO (operands[1])
17370 && peep2_regno_dead_p (0, FLAGS_REG)"
17371 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17372 (clobber (reg:CC 17))])]
17373 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
17374
17375;; The ESP adjustments can be done by the push and pop instructions. Resulting
17376;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On

--- 461 unchanged lines hidden (view full) ---

17838 RET;
17839})
17840
17841 ;; Pentium III SIMD instructions.
17842
17843;; Moves for SSE/MMX regs.
17844
17845(define_insn "movv4sf_internal"
17856 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17857 (match_operand:V4SF 1 "nonimmediate_operand" "xm,x"))]
17846 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
17847 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
17848 "TARGET_SSE"
17849 ;; @@@ let's try to use movaps here.
17860 "movaps\t{%1, %0|%0, %1}"
17861 [(set_attr "type" "sse")])
17850 "@
17851 xorps\t%0, %0
17852 movaps\t{%1, %0|%0, %1}
17853 movaps\t{%1, %0|%0, %1}"
17854 [(set_attr "type" "ssemov")
17855 (set_attr "mode" "V4SF")])
17856
17857(define_insn "movv4si_internal"
17864 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
17865 (match_operand:V4SI 1 "nonimmediate_operand" "xm,x"))]
17858 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m")
17859 (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))]
17860 "TARGET_SSE"
17861 ;; @@@ let's try to use movaps here.
17868 "movaps\t{%1, %0|%0, %1}"
17869 [(set_attr "type" "sse")])
17862 "@
17863 xorps\t%0, %0
17864 movaps\t{%1, %0|%0, %1}
17865 movaps\t{%1, %0|%0, %1}"
17866 [(set_attr "type" "ssemov")
17867 (set_attr "mode" "V4SF")])
17868
17869(define_insn "movv2di_internal"
17870 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m")
17871 (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))]
17872 "TARGET_SSE"
17873 ;; @@@ let's try to use movaps here.
17874 "@
17875 pxor\t%0, %0
17876 movdqa\t{%1, %0|%0, %1}
17877 movdqa\t{%1, %0|%0, %1}"
17878 [(set_attr "type" "ssemov")
17879 (set_attr "mode" "V4SF")])
17880
17881(define_insn "movv8qi_internal"
17872 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
17873 (match_operand:V8QI 1 "nonimmediate_operand" "ym,y"))]
17874 "TARGET_MMX"
17875 "movq\t{%1, %0|%0, %1}"
17876 [(set_attr "type" "mmx")])
17882 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m")
17883 (match_operand:V8QI 1 "vector_move_operand" "C,ym,y"))]
17884 "TARGET_MMX
17885 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
17886 "@
17887 pxor\t%0, %0
17888 movq\t{%1, %0|%0, %1}
17889 movq\t{%1, %0|%0, %1}"
17890 [(set_attr "type" "mmxmov")
17891 (set_attr "mode" "DI")])
17892
17893(define_insn "movv4hi_internal"
17879 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
17880 (match_operand:V4HI 1 "nonimmediate_operand" "ym,y"))]
17881 "TARGET_MMX"
17882 "movq\t{%1, %0|%0, %1}"
17883 [(set_attr "type" "mmx")])
17894 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m")
17895 (match_operand:V4HI 1 "vector_move_operand" "C,ym,y"))]
17896 "TARGET_MMX
17897 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
17898 "@
17899 pxor\t%0, %0
17900 movq\t{%1, %0|%0, %1}
17901 movq\t{%1, %0|%0, %1}"
17902 [(set_attr "type" "mmxmov")
17903 (set_attr "mode" "DI")])
17904
17905(define_insn "movv2si_internal"
17886 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
17887 (match_operand:V2SI 1 "nonimmediate_operand" "ym,y"))]
17888 "TARGET_MMX"
17889 "movq\t{%1, %0|%0, %1}"
17890 [(set_attr "type" "mmx")])
17906 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m")
17907 (match_operand:V2SI 1 "vector_move_operand" "C,ym,y"))]
17908 "TARGET_MMX
17909 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
17910 "@
17911 pxor\t%0, %0
17912 movq\t{%1, %0|%0, %1}
17913 movq\t{%1, %0|%0, %1}"
17914 [(set_attr "type" "mmxcvt")
17915 (set_attr "mode" "DI")])
17916
17917(define_insn "movv2sf_internal"
17893 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,m")
17894 (match_operand:V2SF 1 "nonimmediate_operand" "ym,y"))]
17895 "TARGET_3DNOW"
17896 "movq\\t{%1, %0|%0, %1}"
17897 [(set_attr "type" "mmx")])
17918 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m")
17919 (match_operand:V2SF 1 "vector_move_operand" "C,ym,y"))]
17920 "TARGET_3DNOW
17921 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
17922 "@
17923 pxor\t%0, %0
17924 movq\t{%1, %0|%0, %1}
17925 movq\t{%1, %0|%0, %1}"
17926 [(set_attr "type" "mmxcvt")
17927 (set_attr "mode" "DI")])
17928
17929(define_expand "movti"
17900 [(set (match_operand:TI 0 "general_operand" "")
17901 (match_operand:TI 1 "general_operand" ""))]
17930 [(set (match_operand:TI 0 "nonimmediate_operand" "")
17931 (match_operand:TI 1 "nonimmediate_operand" ""))]
17932 "TARGET_SSE || TARGET_64BIT"
17933{
17934 if (TARGET_64BIT)
17935 ix86_expand_move (TImode, operands);
17936 else
17937 ix86_expand_vector_move (TImode, operands);
17938 DONE;
17939})
17940
17941(define_insn "movv2df_internal"
17942 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
17943 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
17944 "TARGET_SSE2
17945 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
17946 "@
17947 xorpd\t%0, %0
17948 movapd\t{%1, %0|%0, %1}
17949 movapd\t{%1, %0|%0, %1}"
17950 [(set_attr "type" "ssemov")
17951 (set_attr "mode" "V2DF")])
17952
17953(define_insn "movv8hi_internal"
17954 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m")
17955 (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))]
17956 "TARGET_SSE2
17957 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
17958 "@
17959 xorps\t%0, %0
17960 movaps\t{%1, %0|%0, %1}
17961 movaps\t{%1, %0|%0, %1}"
17962 [(set_attr "type" "ssemov")
17963 (set_attr "mode" "V4SF")])
17964
17965(define_insn "movv16qi_internal"
17966 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
17967 (match_operand:V16QI 1 "vector_move_operand" "C,xm,x"))]
17968 "TARGET_SSE2
17969 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
17970 "@
17971 xorps\t%0, %0
17972 movaps\t{%1, %0|%0, %1}
17973 movaps\t{%1, %0|%0, %1}"
17974 [(set_attr "type" "ssemov")
17975 (set_attr "mode" "V4SF")])
17976
17977(define_expand "movv2df"
17978 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
17979 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
17980 "TARGET_SSE2"
17981{
17982 ix86_expand_vector_move (V2DFmode, operands);
17983 DONE;
17984})
17985
17986(define_expand "movv8hi"
17987 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
17988 (match_operand:V8HI 1 "nonimmediate_operand" ""))]
17989 "TARGET_SSE2"
17990{
17991 ix86_expand_vector_move (V8HImode, operands);
17992 DONE;
17993})
17994
17995(define_expand "movv16qi"
17996 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
17997 (match_operand:V16QI 1 "nonimmediate_operand" ""))]
17998 "TARGET_SSE2"
17999{
18000 ix86_expand_vector_move (V16QImode, operands);
18001 DONE;
18002})
18003
18004(define_expand "movv4sf"
17912 [(set (match_operand:V4SF 0 "general_operand" "")
17913 (match_operand:V4SF 1 "general_operand" ""))]
18005 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
18006 (match_operand:V4SF 1 "nonimmediate_operand" ""))]
18007 "TARGET_SSE"
18008{
18009 ix86_expand_vector_move (V4SFmode, operands);
18010 DONE;
18011})
18012
18013(define_expand "movv4si"
17921 [(set (match_operand:V4SI 0 "general_operand" "")
17922 (match_operand:V4SI 1 "general_operand" ""))]
17923 "TARGET_MMX"
18014 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
18015 (match_operand:V4SI 1 "nonimmediate_operand" ""))]
18016 "TARGET_SSE"
18017{
18018 ix86_expand_vector_move (V4SImode, operands);
18019 DONE;
18020})
18021
18022(define_expand "movv2di"
18023 [(set (match_operand:V2DI 0 "nonimmediate_operand" "")
18024 (match_operand:V2DI 1 "nonimmediate_operand" ""))]
18025 "TARGET_SSE"
18026{
18027 ix86_expand_vector_move (V2DImode, operands);
18028 DONE;
18029})
18030
18031(define_expand "movv2si"
17930 [(set (match_operand:V2SI 0 "general_operand" "")
17931 (match_operand:V2SI 1 "general_operand" ""))]
18032 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
18033 (match_operand:V2SI 1 "nonimmediate_operand" ""))]
18034 "TARGET_MMX"
18035{
18036 ix86_expand_vector_move (V2SImode, operands);
18037 DONE;
18038})
18039
18040(define_expand "movv4hi"
17939 [(set (match_operand:V4HI 0 "general_operand" "")
17940 (match_operand:V4HI 1 "general_operand" ""))]
18041 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
18042 (match_operand:V4HI 1 "nonimmediate_operand" ""))]
18043 "TARGET_MMX"
18044{
18045 ix86_expand_vector_move (V4HImode, operands);
18046 DONE;
18047})
18048
18049(define_expand "movv8qi"
17948 [(set (match_operand:V8QI 0 "general_operand" "")
17949 (match_operand:V8QI 1 "general_operand" ""))]
18050 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
18051 (match_operand:V8QI 1 "nonimmediate_operand" ""))]
18052 "TARGET_MMX"
18053{
18054 ix86_expand_vector_move (V8QImode, operands);
18055 DONE;
18056})
18057
18058(define_expand "movv2sf"
17957 [(set (match_operand:V2SF 0 "general_operand" "")
17958 (match_operand:V2SF 1 "general_operand" ""))]
18059 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
18060 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
18061 "TARGET_3DNOW"
18062{
18063 ix86_expand_vector_move (V2SFmode, operands);
18064 DONE;
18065})
18066
18067(define_insn "*pushv2df"
18068 [(set (match_operand:V2DF 0 "push_operand" "=<")
18069 (match_operand:V2DF 1 "register_operand" "x"))]
18070 "TARGET_SSE"
18071 "#")
18072
18073(define_insn "*pushv2di"
18074 [(set (match_operand:V2DI 0 "push_operand" "=<")
18075 (match_operand:V2DI 1 "register_operand" "x"))]
18076 "TARGET_SSE2"
18077 "#")
18078
18079(define_insn "*pushv8hi"
18080 [(set (match_operand:V8HI 0 "push_operand" "=<")
18081 (match_operand:V8HI 1 "register_operand" "x"))]
18082 "TARGET_SSE2"
18083 "#")
18084
18085(define_insn "*pushv16qi"
18086 [(set (match_operand:V16QI 0 "push_operand" "=<")
18087 (match_operand:V16QI 1 "register_operand" "x"))]
18088 "TARGET_SSE2"
18089 "#")
18090
18091(define_insn "*pushv4sf"
18092 [(set (match_operand:V4SF 0 "push_operand" "=<")
18093 (match_operand:V4SF 1 "register_operand" "x"))]
18094 "TARGET_SSE"
18095 "#")
18096
18097(define_insn "*pushv4si"
18098 [(set (match_operand:V4SI 0 "push_operand" "=<")
18099 (match_operand:V4SI 1 "register_operand" "x"))]
18100 "TARGET_SSE2"
18101 "#")
18102
18103(define_insn "*pushv2si"
18104 [(set (match_operand:V2SI 0 "push_operand" "=<")
18105 (match_operand:V2SI 1 "register_operand" "y"))]
18106 "TARGET_MMX"
18107 "#")
18108
18109(define_insn "*pushv4hi"
18110 [(set (match_operand:V4HI 0 "push_operand" "=<")
18111 (match_operand:V4HI 1 "register_operand" "y"))]
18112 "TARGET_MMX"
18113 "#")
18114
18115(define_insn "*pushv8qi"
18116 [(set (match_operand:V8QI 0 "push_operand" "=<")
18117 (match_operand:V8QI 1 "register_operand" "y"))]
18118 "TARGET_MMX"
18119 "#")
18120
18121(define_insn "*pushv2sf"
18122 [(set (match_operand:V2SF 0 "push_operand" "=<")
18123 (match_operand:V2SF 1 "register_operand" "y"))]
18124 "TARGET_3DNOW"
18125 "#")
18126
18127(define_split
18128 [(set (match_operand 0 "push_operand" "")
18129 (match_operand 1 "register_operand" ""))]
18130 "!TARGET_64BIT && reload_completed
18131 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
18132 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 3)))
18133 (set (match_dup 2) (match_dup 1))]
18134 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
18135 stack_pointer_rtx);
18136 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
18137
18138(define_split
18139 [(set (match_operand 0 "push_operand" "")
18140 (match_operand 1 "register_operand" ""))]
18141 "TARGET_64BIT && reload_completed
18142 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
18143 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 3)))
18144 (set (match_dup 2) (match_dup 1))]
18145 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
18146 stack_pointer_rtx);
18147 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
18148
18149
18150(define_insn_and_split "*pushti"
18151 [(set (match_operand:TI 0 "push_operand" "=<")
18152 (match_operand:TI 1 "nonmemory_operand" "x"))]
18153 "TARGET_SSE"
18154 "#"
18155 ""
18156 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
18157 (set (mem:TI (reg:SI 7)) (match_dup 1))]
18158 ""
17974 [(set_attr "type" "sse")])
18159 [(set_attr "type" "multi")])
18160
18161(define_insn_and_split "*pushv2df"
18162 [(set (match_operand:V2DF 0 "push_operand" "=<")
18163 (match_operand:V2DF 1 "nonmemory_operand" "x"))]
18164 "TARGET_SSE2"
18165 "#"
18166 ""
18167 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
18168 (set (mem:V2DF (reg:SI 7)) (match_dup 1))]
18169 ""
18170 [(set_attr "type" "multi")])
18171
18172(define_insn_and_split "*pushv2di"
18173 [(set (match_operand:V2DI 0 "push_operand" "=<")
18174 (match_operand:V2DI 1 "nonmemory_operand" "x"))]
18175 "TARGET_SSE2"
18176 "#"
18177 ""
18178 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
18179 (set (mem:V2DI (reg:SI 7)) (match_dup 1))]
18180 ""
18181 [(set_attr "type" "multi")])
18182
18183(define_insn_and_split "*pushv8hi"
18184 [(set (match_operand:V8HI 0 "push_operand" "=<")
18185 (match_operand:V8HI 1 "nonmemory_operand" "x"))]
18186 "TARGET_SSE2"
18187 "#"
18188 ""
18189 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
18190 (set (mem:V8HI (reg:SI 7)) (match_dup 1))]
18191 ""
18192 [(set_attr "type" "multi")])
18193
18194(define_insn_and_split "*pushv16qi"
18195 [(set (match_operand:V16QI 0 "push_operand" "=<")
18196 (match_operand:V16QI 1 "nonmemory_operand" "x"))]
18197 "TARGET_SSE2"
18198 "#"
18199 ""
18200 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
18201 (set (mem:V16QI (reg:SI 7)) (match_dup 1))]
18202 ""
18203 [(set_attr "type" "multi")])
18204
18205(define_insn_and_split "*pushv4sf"
18206 [(set (match_operand:V4SF 0 "push_operand" "=<")
18207 (match_operand:V4SF 1 "nonmemory_operand" "x"))]
18208 "TARGET_SSE"
18209 "#"
18210 ""
18211 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
18212 (set (mem:V4SF (reg:SI 7)) (match_dup 1))]
18213 ""
17985 [(set_attr "type" "sse")])
18214 [(set_attr "type" "multi")])
18215
18216(define_insn_and_split "*pushv4si"
18217 [(set (match_operand:V4SI 0 "push_operand" "=<")
18218 (match_operand:V4SI 1 "nonmemory_operand" "x"))]
18219 "TARGET_SSE"
18220 "#"
18221 ""
18222 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
18223 (set (mem:V4SI (reg:SI 7)) (match_dup 1))]
18224 ""
17996 [(set_attr "type" "sse")])
18225 [(set_attr "type" "multi")])
18226
18227(define_insn_and_split "*pushv2si"
18228 [(set (match_operand:V2SI 0 "push_operand" "=<")
18229 (match_operand:V2SI 1 "nonmemory_operand" "y"))]
18230 "TARGET_MMX"
18231 "#"
18232 ""
18233 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))

--- 31 unchanged lines hidden (view full) ---

18265 ""
18266 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18267 (set (mem:V2SF (reg:SI 7)) (match_dup 1))]
18268 ""
18269 [(set_attr "type" "mmx")])
18270
18271(define_insn "movti_internal"
18272 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
18044 (match_operand:TI 1 "general_operand" "O,xm,x"))]
18045 "TARGET_SSE && !TARGET_64BIT"
18273 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
18274 "TARGET_SSE && !TARGET_64BIT
18275 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18276 "@
18277 xorps\t%0, %0
18278 movaps\t{%1, %0|%0, %1}
18279 movaps\t{%1, %0|%0, %1}"
18050 [(set_attr "type" "sse")])
18280 [(set_attr "type" "ssemov,ssemov,ssemov")
18281 (set_attr "mode" "V4SF")])
18282
18283(define_insn "*movti_rex64"
18284 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,mx,x")
18054 (match_operand:TI 1 "general_operand" "riFo,riF,O,x,m"))]
18285 (match_operand:TI 1 "general_operand" "riFo,riF,C,x,m"))]
18286 "TARGET_64BIT
18287 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18288 "@
18289 #
18290 #
18291 xorps\t%0, %0
18292 movaps\\t{%1, %0|%0, %1}
18293 movaps\\t{%1, %0|%0, %1}"
18063 [(set_attr "type" "*,*,sse,sse,sse")
18064 (set_attr "mode" "TI")])
18294 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
18295 (set_attr "mode" "V4SF")])
18296
18297(define_split
18298 [(set (match_operand:TI 0 "nonimmediate_operand" "")
18299 (match_operand:TI 1 "general_operand" ""))]
18300 "reload_completed && !SSE_REG_P (operands[0])
18301 && !SSE_REG_P (operands[1])"
18302 [(const_int 0)]
18303 "ix86_split_long_move (operands); DONE;")
18304
18305;; These two patterns are useful for specifying exactly whether to use
18306;; movaps or movups
18076(define_insn "sse_movaps"
18077 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18078 (unspec:V4SF
18079 [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")] 38))]
18307(define_expand "sse_movaps"
18308 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
18309 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
18310 UNSPEC_MOVA))]
18311 "TARGET_SSE"
18081 "@
18082 movaps\t{%1, %0|%0, %1}
18083 movaps\t{%1, %0|%0, %1}"
18084 [(set_attr "type" "sse")])
18312{
18313 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
18314 {
18315 rtx tmp = gen_reg_rtx (V4SFmode);
18316 emit_insn (gen_sse_movaps (tmp, operands[1]));
18317 emit_move_insn (operands[0], tmp);
18318 DONE;
18319 }
18320})
18321
18086(define_insn "sse_movups"
18322(define_insn "*sse_movaps_1"
18323 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18088 (unspec:V4SF
18089 [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")] 39))]
18324 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
18325 UNSPEC_MOVA))]
18326 "TARGET_SSE
18327 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18328 "movaps\t{%1, %0|%0, %1}"
18329 [(set_attr "type" "ssemov,ssemov")
18330 (set_attr "mode" "V4SF")])
18331
18332(define_expand "sse_movups"
18333 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
18334 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
18335 UNSPEC_MOVU))]
18336 "TARGET_SSE"
18091 "@
18092 movups\t{%1, %0|%0, %1}
18093 movups\t{%1, %0|%0, %1}"
18094 [(set_attr "type" "sse")])
18337{
18338 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
18339 {
18340 rtx tmp = gen_reg_rtx (V4SFmode);
18341 emit_insn (gen_sse_movups (tmp, operands[1]));
18342 emit_move_insn (operands[0], tmp);
18343 DONE;
18344 }
18345})
18346
18347(define_insn "*sse_movups_1"
18348 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18349 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
18350 UNSPEC_MOVU))]
18351 "TARGET_SSE
18352 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18353 "movups\t{%1, %0|%0, %1}"
18354 [(set_attr "type" "ssecvt,ssecvt")
18355 (set_attr "mode" "V4SF")])
18356
18357;; SSE Strange Moves.
18358
18359(define_insn "sse_movmskps"
18360 [(set (match_operand:SI 0 "register_operand" "=r")
18101 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
18361 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
18362 UNSPEC_MOVMSK))]
18363 "TARGET_SSE"
18364 "movmskps\t{%1, %0|%0, %1}"
18104 [(set_attr "type" "sse")])
18365 [(set_attr "type" "ssecvt")
18366 (set_attr "mode" "V4SF")])
18367
18368(define_insn "mmx_pmovmskb"
18369 [(set (match_operand:SI 0 "register_operand" "=r")
18108 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
18370 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
18371 UNSPEC_MOVMSK))]
18372 "TARGET_SSE || TARGET_3DNOW_A"
18373 "pmovmskb\t{%1, %0|%0, %1}"
18111 [(set_attr "type" "sse")])
18374 [(set_attr "type" "ssecvt")
18375 (set_attr "mode" "V4SF")])
18376
18377
18378(define_insn "mmx_maskmovq"
18379 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
18380 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
18116 (match_operand:V8QI 2 "register_operand" "y")] 32))]
18381 (match_operand:V8QI 2 "register_operand" "y")]
18382 UNSPEC_MASKMOV))]
18383 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
18384 ;; @@@ check ordering of operands in intel/nonintel syntax
18385 "maskmovq\t{%2, %1|%1, %2}"
18120 [(set_attr "type" "sse")])
18386 [(set_attr "type" "mmxcvt")
18387 (set_attr "mode" "DI")])
18388
18389(define_insn "mmx_maskmovq_rex"
18390 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
18391 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
18125 (match_operand:V8QI 2 "register_operand" "y")] 32))]
18392 (match_operand:V8QI 2 "register_operand" "y")]
18393 UNSPEC_MASKMOV))]
18394 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
18395 ;; @@@ check ordering of operands in intel/nonintel syntax
18396 "maskmovq\t{%2, %1|%1, %2}"
18129 [(set_attr "type" "sse")])
18397 [(set_attr "type" "mmxcvt")
18398 (set_attr "mode" "DI")])
18399
18400(define_insn "sse_movntv4sf"
18401 [(set (match_operand:V4SF 0 "memory_operand" "=m")
18133 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
18402 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
18403 UNSPEC_MOVNT))]
18404 "TARGET_SSE"
18405 "movntps\t{%1, %0|%0, %1}"
18136 [(set_attr "type" "sse")])
18406 [(set_attr "type" "ssemov")
18407 (set_attr "mode" "V4SF")])
18408
18409(define_insn "sse_movntdi"
18410 [(set (match_operand:DI 0 "memory_operand" "=m")
18140 (unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
18411 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
18412 UNSPEC_MOVNT))]
18413 "TARGET_SSE || TARGET_3DNOW_A"
18414 "movntq\t{%1, %0|%0, %1}"
18143 [(set_attr "type" "sse")])
18415 [(set_attr "type" "mmxmov")
18416 (set_attr "mode" "DI")])
18417
18418(define_insn "sse_movhlps"
18419 [(set (match_operand:V4SF 0 "register_operand" "=x")
18420 (vec_merge:V4SF
18421 (match_operand:V4SF 1 "register_operand" "0")
18422 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18423 (parallel [(const_int 2)
18424 (const_int 3)
18425 (const_int 0)
18426 (const_int 1)]))
18427 (const_int 3)))]
18428 "TARGET_SSE"
18429 "movhlps\t{%2, %0|%0, %2}"
18157 [(set_attr "type" "sse")])
18430 [(set_attr "type" "ssecvt")
18431 (set_attr "mode" "V4SF")])
18432
18433(define_insn "sse_movlhps"
18434 [(set (match_operand:V4SF 0 "register_operand" "=x")
18435 (vec_merge:V4SF
18436 (match_operand:V4SF 1 "register_operand" "0")
18437 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18438 (parallel [(const_int 2)
18439 (const_int 3)
18440 (const_int 0)
18441 (const_int 1)]))
18442 (const_int 12)))]
18443 "TARGET_SSE"
18444 "movlhps\t{%2, %0|%0, %2}"
18171 [(set_attr "type" "sse")])
18445 [(set_attr "type" "ssecvt")
18446 (set_attr "mode" "V4SF")])
18447
18448(define_insn "sse_movhps"
18449 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18450 (vec_merge:V4SF
18451 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
18452 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
18453 (const_int 12)))]
18454 "TARGET_SSE
18455 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
18456 "movhps\t{%2, %0|%0, %2}"
18182 [(set_attr "type" "sse")])
18457 [(set_attr "type" "ssecvt")
18458 (set_attr "mode" "V4SF")])
18459
18460(define_insn "sse_movlps"
18461 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18462 (vec_merge:V4SF
18463 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
18464 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
18465 (const_int 3)))]
18466 "TARGET_SSE
18467 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
18468 "movlps\t{%2, %0|%0, %2}"
18193 [(set_attr "type" "sse")])
18469 [(set_attr "type" "ssecvt")
18470 (set_attr "mode" "V4SF")])
18471
18195(define_insn "sse_loadss"
18472(define_expand "sse_loadss"
18473 [(match_operand:V4SF 0 "register_operand" "")
18474 (match_operand:SF 1 "memory_operand" "")]
18475 "TARGET_SSE"
18476{
18477 emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
18478 CONST0_RTX (V4SFmode)));
18479 DONE;
18480})
18481
18482(define_insn "sse_loadss_1"
18483 [(set (match_operand:V4SF 0 "register_operand" "=x")
18484 (vec_merge:V4SF
18198 (match_operand:V4SF 1 "memory_operand" "m")
18199 (vec_duplicate:V4SF (float:SF (const_int 0)))
18485 (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m"))
18486 (match_operand:V4SF 2 "const0_operand" "X")
18487 (const_int 1)))]
18488 "TARGET_SSE"
18489 "movss\t{%1, %0|%0, %1}"
18203 [(set_attr "type" "sse")])
18490 [(set_attr "type" "ssemov")
18491 (set_attr "mode" "SF")])
18492
18493(define_insn "sse_movss"
18494 [(set (match_operand:V4SF 0 "register_operand" "=x")
18495 (vec_merge:V4SF
18496 (match_operand:V4SF 1 "register_operand" "0")
18497 (match_operand:V4SF 2 "register_operand" "x")
18498 (const_int 1)))]
18499 "TARGET_SSE"
18500 "movss\t{%2, %0|%0, %2}"
18213 [(set_attr "type" "sse")])
18501 [(set_attr "type" "ssemov")
18502 (set_attr "mode" "SF")])
18503
18504(define_insn "sse_storess"
18505 [(set (match_operand:SF 0 "memory_operand" "=m")
18506 (vec_select:SF
18507 (match_operand:V4SF 1 "register_operand" "x")
18508 (parallel [(const_int 0)])))]
18509 "TARGET_SSE"
18510 "movss\t{%1, %0|%0, %1}"
18222 [(set_attr "type" "sse")])
18511 [(set_attr "type" "ssemov")
18512 (set_attr "mode" "SF")])
18513
18514(define_insn "sse_shufps"
18515 [(set (match_operand:V4SF 0 "register_operand" "=x")
18516 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
18517 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
18228 (match_operand:SI 3 "immediate_operand" "i")] 41))]
18518 (match_operand:SI 3 "immediate_operand" "i")]
18519 UNSPEC_SHUFFLE))]
18520 "TARGET_SSE"
18521 ;; @@@ check operand order for intel/nonintel syntax
18522 "shufps\t{%3, %2, %0|%0, %2, %3}"
18232 [(set_attr "type" "sse")])
18523 [(set_attr "type" "ssecvt")
18524 (set_attr "mode" "V4SF")])
18525
18526
18527;; SSE arithmetic
18528
18529(define_insn "addv4sf3"
18530 [(set (match_operand:V4SF 0 "register_operand" "=x")
18531 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18532 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18533 "TARGET_SSE"
18534 "addps\t{%2, %0|%0, %2}"
18243 [(set_attr "type" "sse")])
18535 [(set_attr "type" "sseadd")
18536 (set_attr "mode" "V4SF")])
18537
18538(define_insn "vmaddv4sf3"
18539 [(set (match_operand:V4SF 0 "register_operand" "=x")
18540 (vec_merge:V4SF
18541 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18542 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18543 (match_dup 1)
18544 (const_int 1)))]
18545 "TARGET_SSE"
18546 "addss\t{%2, %0|%0, %2}"
18254 [(set_attr "type" "sse")])
18547 [(set_attr "type" "sseadd")
18548 (set_attr "mode" "SF")])
18549
18550(define_insn "subv4sf3"
18551 [(set (match_operand:V4SF 0 "register_operand" "=x")
18552 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18553 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18554 "TARGET_SSE"
18555 "subps\t{%2, %0|%0, %2}"
18262 [(set_attr "type" "sse")])
18556 [(set_attr "type" "sseadd")
18557 (set_attr "mode" "V4SF")])
18558
18559(define_insn "vmsubv4sf3"
18560 [(set (match_operand:V4SF 0 "register_operand" "=x")
18561 (vec_merge:V4SF
18562 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18563 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18564 (match_dup 1)
18565 (const_int 1)))]
18566 "TARGET_SSE"
18567 "subss\t{%2, %0|%0, %2}"
18273 [(set_attr "type" "sse")])
18568 [(set_attr "type" "sseadd")
18569 (set_attr "mode" "SF")])
18570
18571(define_insn "mulv4sf3"
18572 [(set (match_operand:V4SF 0 "register_operand" "=x")
18573 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
18574 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18575 "TARGET_SSE"
18576 "mulps\t{%2, %0|%0, %2}"
18281 [(set_attr "type" "sse")])
18577 [(set_attr "type" "ssemul")
18578 (set_attr "mode" "V4SF")])
18579
18580(define_insn "vmmulv4sf3"
18581 [(set (match_operand:V4SF 0 "register_operand" "=x")
18582 (vec_merge:V4SF
18583 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
18584 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18585 (match_dup 1)
18586 (const_int 1)))]
18587 "TARGET_SSE"
18588 "mulss\t{%2, %0|%0, %2}"
18292 [(set_attr "type" "sse")])
18589 [(set_attr "type" "ssemul")
18590 (set_attr "mode" "SF")])
18591
18592(define_insn "divv4sf3"
18593 [(set (match_operand:V4SF 0 "register_operand" "=x")
18594 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
18595 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18596 "TARGET_SSE"
18597 "divps\t{%2, %0|%0, %2}"
18300 [(set_attr "type" "sse")])
18598 [(set_attr "type" "ssediv")
18599 (set_attr "mode" "V4SF")])
18600
18601(define_insn "vmdivv4sf3"
18602 [(set (match_operand:V4SF 0 "register_operand" "=x")
18603 (vec_merge:V4SF
18604 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
18605 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18606 (match_dup 1)
18607 (const_int 1)))]
18608 "TARGET_SSE"
18609 "divss\t{%2, %0|%0, %2}"
18311 [(set_attr "type" "sse")])
18610 [(set_attr "type" "ssediv")
18611 (set_attr "mode" "SF")])
18612
18613
18614;; SSE square root/reciprocal
18615
18616(define_insn "rcpv4sf2"
18617 [(set (match_operand:V4SF 0 "register_operand" "=x")
18618 (unspec:V4SF
18319 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 42))]
18619 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
18620 "TARGET_SSE"
18621 "rcpps\t{%1, %0|%0, %1}"
18322 [(set_attr "type" "sse")])
18622 [(set_attr "type" "sse")
18623 (set_attr "mode" "V4SF")])
18624
18625(define_insn "vmrcpv4sf2"
18626 [(set (match_operand:V4SF 0 "register_operand" "=x")
18627 (vec_merge:V4SF
18327 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 42)
18628 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
18629 UNSPEC_RCP)
18630 (match_operand:V4SF 2 "register_operand" "0")
18631 (const_int 1)))]
18632 "TARGET_SSE"
18633 "rcpss\t{%1, %0|%0, %1}"
18332 [(set_attr "type" "sse")])
18634 [(set_attr "type" "sse")
18635 (set_attr "mode" "SF")])
18636
18637(define_insn "rsqrtv4sf2"
18638 [(set (match_operand:V4SF 0 "register_operand" "=x")
18639 (unspec:V4SF
18337 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 43))]
18640 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
18641 "TARGET_SSE"
18642 "rsqrtps\t{%1, %0|%0, %1}"
18340 [(set_attr "type" "sse")])
18643 [(set_attr "type" "sse")
18644 (set_attr "mode" "V4SF")])
18645
18646(define_insn "vmrsqrtv4sf2"
18647 [(set (match_operand:V4SF 0 "register_operand" "=x")
18648 (vec_merge:V4SF
18345 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 43)
18649 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
18650 UNSPEC_RSQRT)
18651 (match_operand:V4SF 2 "register_operand" "0")
18652 (const_int 1)))]
18653 "TARGET_SSE"
18654 "rsqrtss\t{%1, %0|%0, %1}"
18350 [(set_attr "type" "sse")])
18655 [(set_attr "type" "sse")
18656 (set_attr "mode" "SF")])
18657
18658(define_insn "sqrtv4sf2"
18659 [(set (match_operand:V4SF 0 "register_operand" "=x")
18660 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
18661 "TARGET_SSE"
18662 "sqrtps\t{%1, %0|%0, %1}"
18357 [(set_attr "type" "sse")])
18663 [(set_attr "type" "sse")
18664 (set_attr "mode" "V4SF")])
18665
18666(define_insn "vmsqrtv4sf2"
18667 [(set (match_operand:V4SF 0 "register_operand" "=x")
18668 (vec_merge:V4SF
18669 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
18670 (match_operand:V4SF 2 "register_operand" "0")
18671 (const_int 1)))]
18672 "TARGET_SSE"
18673 "sqrtss\t{%1, %0|%0, %1}"
18367 [(set_attr "type" "sse")])
18674 [(set_attr "type" "sse")
18675 (set_attr "mode" "SF")])
18676
18677;; SSE logical operations.
18678
18679;; SSE defines logical operations on floating point values. This brings
18680;; interesting challenge to RTL representation where logicals are only valid
18681;; on integral types. We deal with this by representing the floating point
18682;; logical as logical on arguments casted to TImode as this is what hardware
18683;; really does. Unfortunately hardware requires the type information to be
18684;; present and thus we must avoid subregs from being simplified and elliminated
18685;; in later compilation phases.
18686;;
18687;; We have following variants from each instruction:
18688;; sse_andsf3 - the operation taking V4SF vector operands
18689;; and doing TImode cast on them
18690;; *sse_andsf3_memory - the operation taking one memory operand casted to
18691;; TImode, since backend insist on elliminating casts
18692;; on memory operands
18693;; sse_andti3_sf_1 - the operation taking SF scalar operands.
18694;; We can not accept memory operand here as instruction reads
18695;; whole scalar. This is generated only post reload by GCC
18696;; scalar float operations that expands to logicals (fabs)
18697;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
18698;; memory operand. Eventually combine can be able
18699;; to synthetize these using splitter.
18700;; sse2_anddf3, *sse2_anddf3_memory
18701;;
18702;;
18703;; These are not called andti3 etc. because we really really don't want
18704;; the compiler to widen DImode ands to TImode ands and then try to move
18705;; into DImode subregs of SSE registers, and them together, and move out
18706;; of DImode subregs again!
18707;; SSE1 single precision floating point logical operation
18708(define_expand "sse_andv4sf3"
18709 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
18710 (and:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
18711 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
18712 "TARGET_SSE"
18713 "")
18714
18376(define_insn "*sse_andti3_df_1"
18377 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18378 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18379 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18380 "TARGET_SSE2"
18381 "andpd\t{%2, %0|%0, %2}"
18382 [(set_attr "type" "sse")])
18715(define_insn "*sse_andv4sf3"
18716 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
18717 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18718 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18719 "TARGET_SSE
18720 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18721 "andps\t{%2, %0|%0, %2}"
18722 [(set_attr "type" "sselog")
18723 (set_attr "mode" "V4SF")])
18724
18384(define_insn "*sse_andti3_df_2"
18385 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18386 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18387 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18388 "TARGET_SSE2"
18389 "andpd\t{%2, %0|%0, %2}"
18390 [(set_attr "type" "sse")])
18391
18392(define_insn "*sse_andti3_sf_1"
18725(define_insn "*sse_andsf3"
18726 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18394 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18395 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18396 "TARGET_SSE"
18727 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18728 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18729 "TARGET_SSE
18730 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18731 "andps\t{%2, %0|%0, %2}"
18398 [(set_attr "type" "sse")])
18732 [(set_attr "type" "sselog")
18733 (set_attr "mode" "V4SF")])
18734
18400(define_insn "*sse_andti3_sf_2"
18735(define_expand "sse_nandv4sf3"
18736 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
18737 (and:TI (not:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0))
18738 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
18739 "TARGET_SSE"
18740 "")
18741
18742(define_insn "*sse_nandv4sf3"
18743 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
18744 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18745 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18746 "TARGET_SSE"
18747 "andnps\t{%2, %0|%0, %2}"
18748 [(set_attr "type" "sselog")
18749 (set_attr "mode" "V4SF")])
18750
18751(define_insn "*sse_nandsf3"
18752 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18402 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18403 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18753 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18754 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18755 "TARGET_SSE"
18405 "andps\t{%2, %0|%0, %2}"
18406 [(set_attr "type" "sse")])
18756 "andnps\t{%2, %0|%0, %2}"
18757 [(set_attr "type" "sselog")
18758 (set_attr "mode" "V4SF")])
18759
18408(define_insn "sse_andti3"
18409 [(set (match_operand:TI 0 "register_operand" "=x")
18410 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18760(define_expand "sse_iorv4sf3"
18761 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
18762 (ior:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
18763 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
18764 "TARGET_SSE"
18765 "")
18766
18767(define_insn "*sse_iorv4sf3"
18768 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
18769 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18770 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18412 "TARGET_SSE && !TARGET_SSE2
18771 "TARGET_SSE
18772 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18414 "andps\t{%2, %0|%0, %2}"
18415 [(set_attr "type" "sse")])
18773 "orps\t{%2, %0|%0, %2}"
18774 [(set_attr "type" "sselog")
18775 (set_attr "mode" "V4SF")])
18776
18417(define_insn "*sse_andti3_sse2"
18418 [(set (match_operand:TI 0 "register_operand" "=x")
18419 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18777(define_insn "*sse_iorsf3"
18778 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18779 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18780 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18421 "TARGET_SSE2
18781 "TARGET_SSE
18782 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18423 "pand\t{%2, %0|%0, %2}"
18424 [(set_attr "type" "sse")])
18783 "orps\t{%2, %0|%0, %2}"
18784 [(set_attr "type" "sselog")
18785 (set_attr "mode" "V4SF")])
18786
18426(define_insn "*sse_nandti3_df"
18427 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18428 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
18429 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18430 "TARGET_SSE2"
18431 "andnpd\t{%2, %0|%0, %2}"
18432 [(set_attr "type" "sse")])
18787(define_expand "sse_xorv4sf3"
18788 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
18789 (xor:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
18790 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
18791 "TARGET_SSE
18792 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18793 "")
18794
18434(define_insn "*sse_nandti3_sf"
18795(define_insn "*sse_xorv4sf3"
18796 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
18797 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18798 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18799 "TARGET_SSE
18800 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18801 "xorps\t{%2, %0|%0, %2}"
18802 [(set_attr "type" "sselog")
18803 (set_attr "mode" "V4SF")])
18804
18805(define_insn "*sse_xorsf3"
18806 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18436 (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
18807 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18808 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18438 "TARGET_SSE"
18439 "andnps\t{%2, %0|%0, %2}"
18440 [(set_attr "type" "sse")])
18809 "TARGET_SSE
18810 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18811 "xorps\t{%2, %0|%0, %2}"
18812 [(set_attr "type" "sselog")
18813 (set_attr "mode" "V4SF")])
18814
18442(define_insn "sse_nandti3"
18443 [(set (match_operand:TI 0 "register_operand" "=x")
18444 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18815;; SSE2 double precision floating point logical operation
18816
18817(define_expand "sse2_andv2df3"
18818 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
18819 (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
18820 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
18821 "TARGET_SSE2"
18822 "")
18823
18824(define_insn "*sse2_andv2df3"
18825 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
18826 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18827 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18446 "TARGET_SSE && !TARGET_SSE2"
18447 "andnps\t{%2, %0|%0, %2}"
18448 [(set_attr "type" "sse")])
18828 "TARGET_SSE2
18829 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18830 "andpd\t{%2, %0|%0, %2}"
18831 [(set_attr "type" "sselog")
18832 (set_attr "mode" "V2DF")])
18833
18450(define_insn "*sse_nandti3_sse2"
18451 [(set (match_operand:TI 0 "register_operand" "=x")
18452 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18834(define_insn "*sse2_andv2df3"
18835 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
18836 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18837 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18838 "TARGET_SSE2
18839 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18840 "andpd\t{%2, %0|%0, %2}"
18841 [(set_attr "type" "sselog")
18842 (set_attr "mode" "V2DF")])
18843
18844(define_expand "sse2_nandv2df3"
18845 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
18846 (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0))
18847 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
18848 "TARGET_SSE2"
18455 "pnand\t{%2, %0|%0, %2}"
18456 [(set_attr "type" "sse")])
18849 "")
18850
18458(define_insn "*sse_iorti3_df_1"
18459 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18460 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18461 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18851(define_insn "*sse2_nandv2df3"
18852 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
18853 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18854 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18855 "TARGET_SSE2"
18463 "orpd\t{%2, %0|%0, %2}"
18464 [(set_attr "type" "sse")])
18856 "andnpd\t{%2, %0|%0, %2}"
18857 [(set_attr "type" "sselog")
18858 (set_attr "mode" "V2DF")])
18859
18466(define_insn "*sse_iorti3_df_2"
18860(define_insn "*sse_nandti3_df"
18861 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18468 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18862 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18863 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18864 "TARGET_SSE2"
18471 "orpd\t{%2, %0|%0, %2}"
18472 [(set_attr "type" "sse")])
18865 "andnpd\t{%2, %0|%0, %2}"
18866 [(set_attr "type" "sselog")
18867 (set_attr "mode" "V2DF")])
18868
18474(define_insn "*sse_iorti3_sf_1"
18475 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18476 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18477 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18478 "TARGET_SSE"
18479 "orps\t{%2, %0|%0, %2}"
18480 [(set_attr "type" "sse")])
18869(define_expand "sse2_iorv2df3"
18870 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
18871 (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
18872 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
18873 "TARGET_SSE2"
18874 "")
18875
18482(define_insn "*sse_iorti3_sf_2"
18483 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18484 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18485 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18486 "TARGET_SSE"
18487 "orps\t{%2, %0|%0, %2}"
18488 [(set_attr "type" "sse")])
18489
18490(define_insn "sse_iorti3"
18491 [(set (match_operand:TI 0 "register_operand" "=x")
18876(define_insn "*sse2_iorv2df3"
18877 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
18878 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18879 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18494 "TARGET_SSE && !TARGET_SSE2
18880 "TARGET_SSE2
18881 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18496 "orps\t{%2, %0|%0, %2}"
18497 [(set_attr "type" "sse")])
18882 "orpd\t{%2, %0|%0, %2}"
18883 [(set_attr "type" "sselog")
18884 (set_attr "mode" "V2DF")])
18885
18499(define_insn "*sse_iorti3_sse2"
18500 [(set (match_operand:TI 0 "register_operand" "=x")
18886(define_insn "*sse2_iordf3"
18887 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
18888 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18889 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18890 "TARGET_SSE2
18891 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18505 "por\t{%2, %0|%0, %2}"
18506 [(set_attr "type" "sse")])
18892 "orpd\t{%2, %0|%0, %2}"
18893 [(set_attr "type" "sselog")
18894 (set_attr "mode" "V2DF")])
18895
18508(define_insn "*sse_xorti3_df_1"
18509 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18510 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18511 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18896(define_expand "sse2_xorv2df3"
18897 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
18898 (xor:TI (subreg:TI (match_operand:V2DF 1 "nonimmediate_operand" "") 0)
18899 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
18900 "TARGET_SSE2"
18901 "")
18902
18903(define_insn "*sse2_xorv2df3"
18904 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
18905 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18906 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18907 "TARGET_SSE2
18908 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18909 "xorpd\t{%2, %0|%0, %2}"
18514 [(set_attr "type" "sse")])
18910 [(set_attr "type" "sselog")
18911 (set_attr "mode" "V2DF")])
18912
18516(define_insn "*sse_xorti3_df_2"
18517 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18518 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18519 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18520 "TARGET_SSE2"
18913(define_insn "*sse2_xordf3"
18914 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
18915 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18916 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18917 "TARGET_SSE2
18918 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18919 "xorpd\t{%2, %0|%0, %2}"
18522 [(set_attr "type" "sse")])
18920 [(set_attr "type" "sselog")
18921 (set_attr "mode" "V2DF")])
18922
18524(define_insn "*sse_xorti3_sf_1"
18525 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18526 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18527 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18528 "TARGET_SSE"
18529 "xorps\t{%2, %0|%0, %2}"
18530 [(set_attr "type" "sse")])
18923;; SSE2 integral logicals. These patterns must always come after floating
18924;; point ones since we don't want compiler to use integer opcodes on floating
18925;; point SSE values to avoid matching of subregs in the match_operand.
18926(define_insn "*sse2_andti3"
18927 [(set (match_operand:TI 0 "register_operand" "=x")
18928 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18929 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18930 "TARGET_SSE2
18931 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18932 "pand\t{%2, %0|%0, %2}"
18933 [(set_attr "type" "sselog")
18934 (set_attr "mode" "TI")])
18935
18532(define_insn "*sse_xorti3_sf_2"
18533 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18534 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18936(define_insn "sse2_andv2di3"
18937 [(set (match_operand:V2DI 0 "register_operand" "=x")
18938 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
18939 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18940 "TARGET_SSE2
18941 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18942 "pand\t{%2, %0|%0, %2}"
18943 [(set_attr "type" "sselog")
18944 (set_attr "mode" "TI")])
18945
18946(define_insn "*sse2_nandti3"
18947 [(set (match_operand:TI 0 "register_operand" "=x")
18948 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18949 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18536 "TARGET_SSE"
18537 "xorps\t{%2, %0|%0, %2}"
18538 [(set_attr "type" "sse")])
18950 "TARGET_SSE2"
18951 "pandn\t{%2, %0|%0, %2}"
18952 [(set_attr "type" "sselog")
18953 (set_attr "mode" "TI")])
18954
18540(define_insn "sse_xorti3"
18955(define_insn "sse2_nandv2di3"
18956 [(set (match_operand:V2DI 0 "register_operand" "=x")
18957 (and:V2DI (not:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "0"))
18958 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18959 "TARGET_SSE2
18960 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18961 "pandn\t{%2, %0|%0, %2}"
18962 [(set_attr "type" "sselog")
18963 (set_attr "mode" "TI")])
18964
18965(define_insn "*sse2_iorti3"
18966 [(set (match_operand:TI 0 "register_operand" "=x")
18542 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18967 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18968 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18544 "TARGET_SSE && !TARGET_SSE2
18969 "TARGET_SSE2
18970 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18546 "xorps\t{%2, %0|%0, %2}"
18547 [(set_attr "type" "sse")])
18971 "por\t{%2, %0|%0, %2}"
18972 [(set_attr "type" "sselog")
18973 (set_attr "mode" "TI")])
18974
18549(define_insn "*sse_xorti3_sse2"
18975(define_insn "sse2_iorv2di3"
18976 [(set (match_operand:V2DI 0 "register_operand" "=x")
18977 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
18978 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18979 "TARGET_SSE2
18980 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18981 "por\t{%2, %0|%0, %2}"
18982 [(set_attr "type" "sselog")
18983 (set_attr "mode" "TI")])
18984
18985(define_insn "*sse2_xorti3"
18986 [(set (match_operand:TI 0 "register_operand" "=x")
18987 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18988 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18989 "TARGET_SSE2
18990 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18991 "pxor\t{%2, %0|%0, %2}"
18556 [(set_attr "type" "sse")])
18992 [(set_attr "type" "sselog")
18993 (set_attr "mode" "TI")])
18994
18995(define_insn "sse2_xorv2di3"
18996 [(set (match_operand:V2DI 0 "register_operand" "=x")
18997 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
18998 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18999 "TARGET_SSE2
19000 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19001 "pxor\t{%2, %0|%0, %2}"
19002 [(set_attr "type" "sselog")
19003 (set_attr "mode" "TI")])
19004
19005;; Use xor, but don't show input operands so they aren't live before
19006;; this insn.
19007(define_insn "sse_clrv4sf"
19008 [(set (match_operand:V4SF 0 "register_operand" "=x")
18562 (unspec:V4SF [(const_int 0)] 45))]
19009 (unspec:V4SF [(const_int 0)] UNSPEC_NOP))]
19010 "TARGET_SSE"
19011 "xorps\t{%0, %0|%0, %0}"
18565 [(set_attr "type" "sse")
18566 (set_attr "memory" "none")])
19012 [(set_attr "type" "sselog")
19013 (set_attr "memory" "none")
19014 (set_attr "mode" "V4SF")])
19015
19016;; Use xor, but don't show input operands so they aren't live before
19017;; this insn.
19018(define_insn "sse_clrv2df"
19019 [(set (match_operand:V2DF 0 "register_operand" "=x")
19020 (unspec:V2DF [(const_int 0)] UNSPEC_NOP))]
19021 "TARGET_SSE2"
19022 "xorpd\t{%0, %0|%0, %0}"
19023 [(set_attr "type" "sselog")
19024 (set_attr "memory" "none")
19025 (set_attr "mode" "V4SF")])
19026
19027;; SSE mask-generating compares
19028
19029(define_insn "maskcmpv4sf3"
19030 [(set (match_operand:V4SI 0 "register_operand" "=x")
19031 (match_operator:V4SI 3 "sse_comparison_operator"
19032 [(match_operand:V4SF 1 "register_operand" "0")
19033 (match_operand:V4SF 2 "register_operand" "x")]))]
19034 "TARGET_SSE"
19035 "cmp%D3ps\t{%2, %0|%0, %2}"
18577 [(set_attr "type" "sse")])
19036 [(set_attr "type" "ssecmp")
19037 (set_attr "mode" "V4SF")])
19038
19039(define_insn "maskncmpv4sf3"
19040 [(set (match_operand:V4SI 0 "register_operand" "=x")
19041 (not:V4SI
19042 (match_operator:V4SI 3 "sse_comparison_operator"
19043 [(match_operand:V4SF 1 "register_operand" "0")
19044 (match_operand:V4SF 2 "register_operand" "x")])))]
19045 "TARGET_SSE"
19046{
19047 if (GET_CODE (operands[3]) == UNORDERED)
19048 return "cmpordps\t{%2, %0|%0, %2}";
19049 else
19050 return "cmpn%D3ps\t{%2, %0|%0, %2}";
19051}
18592 [(set_attr "type" "sse")])
19052 [(set_attr "type" "ssecmp")
19053 (set_attr "mode" "V4SF")])
19054
19055(define_insn "vmmaskcmpv4sf3"
19056 [(set (match_operand:V4SI 0 "register_operand" "=x")
19057 (vec_merge:V4SI
19058 (match_operator:V4SI 3 "sse_comparison_operator"
19059 [(match_operand:V4SF 1 "register_operand" "0")
19060 (match_operand:V4SF 2 "register_operand" "x")])
18600 (match_dup 1)
19061 (subreg:V4SI (match_dup 1) 0)
19062 (const_int 1)))]
19063 "TARGET_SSE"
19064 "cmp%D3ss\t{%2, %0|%0, %2}"
18604 [(set_attr "type" "sse")])
19065 [(set_attr "type" "ssecmp")
19066 (set_attr "mode" "SF")])
19067
19068(define_insn "vmmaskncmpv4sf3"
19069 [(set (match_operand:V4SI 0 "register_operand" "=x")
19070 (vec_merge:V4SI
19071 (not:V4SI
19072 (match_operator:V4SI 3 "sse_comparison_operator"
19073 [(match_operand:V4SF 1 "register_operand" "0")
19074 (match_operand:V4SF 2 "register_operand" "x")]))
19075 (subreg:V4SI (match_dup 1) 0)
19076 (const_int 1)))]
19077 "TARGET_SSE"
19078{
19079 if (GET_CODE (operands[3]) == UNORDERED)
19080 return "cmpordss\t{%2, %0|%0, %2}";
19081 else
19082 return "cmpn%D3ss\t{%2, %0|%0, %2}";
19083}
18622 [(set_attr "type" "sse")])
19084 [(set_attr "type" "ssecmp")
19085 (set_attr "mode" "SF")])
19086
19087(define_insn "sse_comi"
19088 [(set (reg:CCFP 17)
18626 (match_operator:CCFP 2 "sse_comparison_operator"
18627 [(vec_select:SF
18628 (match_operand:V4SF 0 "register_operand" "x")
18629 (parallel [(const_int 0)]))
18630 (vec_select:SF
18631 (match_operand:V4SF 1 "register_operand" "x")
18632 (parallel [(const_int 0)]))]))]
19089 (compare:CCFP (vec_select:SF
19090 (match_operand:V4SF 0 "register_operand" "x")
19091 (parallel [(const_int 0)]))
19092 (vec_select:SF
19093 (match_operand:V4SF 1 "register_operand" "x")
19094 (parallel [(const_int 0)]))))]
19095 "TARGET_SSE"
19096 "comiss\t{%1, %0|%0, %1}"
18635 [(set_attr "type" "sse")])
19097 [(set_attr "type" "ssecmp")
19098 (set_attr "mode" "SF")])
19099
19100(define_insn "sse_ucomi"
19101 [(set (reg:CCFPU 17)
18639 (match_operator:CCFPU 2 "sse_comparison_operator"
18640 [(vec_select:SF
18641 (match_operand:V4SF 0 "register_operand" "x")
18642 (parallel [(const_int 0)]))
18643 (vec_select:SF
18644 (match_operand:V4SF 1 "register_operand" "x")
18645 (parallel [(const_int 0)]))]))]
19102 (compare:CCFPU (vec_select:SF
19103 (match_operand:V4SF 0 "register_operand" "x")
19104 (parallel [(const_int 0)]))
19105 (vec_select:SF
19106 (match_operand:V4SF 1 "register_operand" "x")
19107 (parallel [(const_int 0)]))))]
19108 "TARGET_SSE"
19109 "ucomiss\t{%1, %0|%0, %1}"
18648 [(set_attr "type" "sse")])
19110 [(set_attr "type" "ssecmp")
19111 (set_attr "mode" "SF")])
19112
19113
19114;; SSE unpack
19115
19116(define_insn "sse_unpckhps"
19117 [(set (match_operand:V4SF 0 "register_operand" "=x")
19118 (vec_merge:V4SF
19119 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")

--- 4 unchanged lines hidden (view full) ---

19124 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19125 (parallel [(const_int 0)
19126 (const_int 2)
19127 (const_int 1)
19128 (const_int 3)]))
19129 (const_int 5)))]
19130 "TARGET_SSE"
19131 "unpckhps\t{%2, %0|%0, %2}"
18669 [(set_attr "type" "sse")])
19132 [(set_attr "type" "ssecvt")
19133 (set_attr "mode" "V4SF")])
19134
19135(define_insn "sse_unpcklps"
19136 [(set (match_operand:V4SF 0 "register_operand" "=x")
19137 (vec_merge:V4SF
19138 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
19139 (parallel [(const_int 0)
19140 (const_int 2)
19141 (const_int 1)
19142 (const_int 3)]))
19143 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19144 (parallel [(const_int 2)
19145 (const_int 0)
19146 (const_int 3)
19147 (const_int 1)]))
19148 (const_int 5)))]
19149 "TARGET_SSE"
19150 "unpcklps\t{%2, %0|%0, %2}"
18687 [(set_attr "type" "sse")])
19151 [(set_attr "type" "ssecvt")
19152 (set_attr "mode" "V4SF")])
19153
19154
19155;; SSE min/max
19156
19157(define_insn "smaxv4sf3"
19158 [(set (match_operand:V4SF 0 "register_operand" "=x")
19159 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
19160 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19161 "TARGET_SSE"
19162 "maxps\t{%2, %0|%0, %2}"
18698 [(set_attr "type" "sse")])
19163 [(set_attr "type" "sse")
19164 (set_attr "mode" "V4SF")])
19165
19166(define_insn "vmsmaxv4sf3"
19167 [(set (match_operand:V4SF 0 "register_operand" "=x")
19168 (vec_merge:V4SF
19169 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
19170 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19171 (match_dup 1)
19172 (const_int 1)))]
19173 "TARGET_SSE"
19174 "maxss\t{%2, %0|%0, %2}"
18709 [(set_attr "type" "sse")])
19175 [(set_attr "type" "sse")
19176 (set_attr "mode" "SF")])
19177
19178(define_insn "sminv4sf3"
19179 [(set (match_operand:V4SF 0 "register_operand" "=x")
19180 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
19181 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19182 "TARGET_SSE"
19183 "minps\t{%2, %0|%0, %2}"
18717 [(set_attr "type" "sse")])
19184 [(set_attr "type" "sse")
19185 (set_attr "mode" "V4SF")])
19186
19187(define_insn "vmsminv4sf3"
19188 [(set (match_operand:V4SF 0 "register_operand" "=x")
19189 (vec_merge:V4SF
19190 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
19191 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19192 (match_dup 1)
19193 (const_int 1)))]
19194 "TARGET_SSE"
19195 "minss\t{%2, %0|%0, %2}"
18728 [(set_attr "type" "sse")])
19196 [(set_attr "type" "sse")
19197 (set_attr "mode" "SF")])
19198
18730
19199;; SSE <-> integer/MMX conversions
19200
19201(define_insn "cvtpi2ps"
19202 [(set (match_operand:V4SF 0 "register_operand" "=x")
19203 (vec_merge:V4SF
19204 (match_operand:V4SF 1 "register_operand" "0")
19205 (vec_duplicate:V4SF
19206 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
19207 (const_int 12)))]
19208 "TARGET_SSE"
19209 "cvtpi2ps\t{%2, %0|%0, %2}"
18742 [(set_attr "type" "sse")])
19210 [(set_attr "type" "ssecvt")
19211 (set_attr "mode" "V4SF")])
19212
19213(define_insn "cvtps2pi"
19214 [(set (match_operand:V2SI 0 "register_operand" "=y")
19215 (vec_select:V2SI
19216 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
19217 (parallel [(const_int 0) (const_int 1)])))]
19218 "TARGET_SSE"
19219 "cvtps2pi\t{%1, %0|%0, %1}"
18751 [(set_attr "type" "sse")])
19220 [(set_attr "type" "ssecvt")
19221 (set_attr "mode" "V4SF")])
19222
19223(define_insn "cvttps2pi"
19224 [(set (match_operand:V2SI 0 "register_operand" "=y")
19225 (vec_select:V2SI
18756 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 30)
19226 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19227 UNSPEC_FIX)
19228 (parallel [(const_int 0) (const_int 1)])))]
19229 "TARGET_SSE"
19230 "cvttps2pi\t{%1, %0|%0, %1}"
18760 [(set_attr "type" "sse")])
19231 [(set_attr "type" "ssecvt")
19232 (set_attr "mode" "SF")])
19233
19234(define_insn "cvtsi2ss"
19235 [(set (match_operand:V4SF 0 "register_operand" "=x")
19236 (vec_merge:V4SF
19237 (match_operand:V4SF 1 "register_operand" "0")
19238 (vec_duplicate:V4SF
19239 (float:SF (match_operand:SI 2 "nonimmediate_operand" "rm")))
19240 (const_int 14)))]
19241 "TARGET_SSE"
19242 "cvtsi2ss\t{%2, %0|%0, %2}"
18771 [(set_attr "type" "sse")])
19243 [(set_attr "type" "ssecvt")
19244 (set_attr "mode" "SF")])
19245
19246(define_insn "cvtsi2ssq"
19247 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
19248 (vec_merge:V4SF
19249 (match_operand:V4SF 1 "register_operand" "0,0")
19250 (vec_duplicate:V4SF
19251 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
19252 (const_int 14)))]
19253 "TARGET_SSE && TARGET_64BIT"
19254 "cvtsi2ssq\t{%2, %0|%0, %2}"
19255 [(set_attr "type" "ssecvt")
19256 (set_attr "athlon_decode" "vector,vector")
19257 (set_attr "mode" "SF")])
19258
19259(define_insn "cvtss2si"
19260 [(set (match_operand:SI 0 "register_operand" "=r")
19261 (vec_select:SI
19262 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
19263 (parallel [(const_int 0)])))]
19264 "TARGET_SSE"
19265 "cvtss2si\t{%1, %0|%0, %1}"
18780 [(set_attr "type" "sse")])
19266 [(set_attr "type" "ssecvt")
19267 (set_attr "mode" "SF")])
19268
19269(define_insn "cvtss2siq"
19270 [(set (match_operand:DI 0 "register_operand" "=r,r")
19271 (vec_select:DI
19272 (fix:V4DI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
19273 (parallel [(const_int 0)])))]
19274 "TARGET_SSE"
19275 "cvtss2siq\t{%1, %0|%0, %1}"
19276 [(set_attr "type" "ssecvt")
19277 (set_attr "athlon_decode" "vector,vector")
19278 (set_attr "mode" "SF")])
19279
19280(define_insn "cvttss2si"
19281 [(set (match_operand:SI 0 "register_operand" "=r")
19282 (vec_select:SI
18785 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 30)
19283 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19284 UNSPEC_FIX)
19285 (parallel [(const_int 0)])))]
19286 "TARGET_SSE"
19287 "cvttss2si\t{%1, %0|%0, %1}"
18789 [(set_attr "type" "sse")])
19288 [(set_attr "type" "ssecvt")
19289 (set_attr "mode" "SF")])
19290
19291(define_insn "cvttss2siq"
19292 [(set (match_operand:DI 0 "register_operand" "=r,r")
19293 (vec_select:DI
19294 (unspec:V4DI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
19295 UNSPEC_FIX)
19296 (parallel [(const_int 0)])))]
19297 "TARGET_SSE && TARGET_64BIT"
19298 "cvttss2siq\t{%1, %0|%0, %1}"
19299 [(set_attr "type" "ssecvt")
19300 (set_attr "mode" "SF")
19301 (set_attr "athlon_decode" "vector,vector")])
19302
19303
19304;; MMX insns
19305
19306;; MMX arithmetic
19307
19308(define_insn "addv8qi3"
19309 [(set (match_operand:V8QI 0 "register_operand" "=y")
18798 (plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19310 (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
19311 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19312 "TARGET_MMX"
19313 "paddb\t{%2, %0|%0, %2}"
18802 [(set_attr "type" "mmx")])
19314 [(set_attr "type" "mmxadd")
19315 (set_attr "mode" "DI")])
19316
19317(define_insn "addv4hi3"
19318 [(set (match_operand:V4HI 0 "register_operand" "=y")
18806 (plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19319 (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
19320 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19321 "TARGET_MMX"
19322 "paddw\t{%2, %0|%0, %2}"
18810 [(set_attr "type" "mmx")])
19323 [(set_attr "type" "mmxadd")
19324 (set_attr "mode" "DI")])
19325
19326(define_insn "addv2si3"
19327 [(set (match_operand:V2SI 0 "register_operand" "=y")
18814 (plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
19328 (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0")
19329 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
19330 "TARGET_MMX"
19331 "paddd\t{%2, %0|%0, %2}"
18818 [(set_attr "type" "mmx")])
19332 [(set_attr "type" "mmxadd")
19333 (set_attr "mode" "DI")])
19334
19335(define_insn "mmx_adddi3"
19336 [(set (match_operand:DI 0 "register_operand" "=y")
19337 (unspec:DI
19338 [(plus:DI (match_operand:DI 1 "register_operand" "%0")
19339 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19340 UNSPEC_NOP))]
19341 "TARGET_MMX"
19342 "paddq\t{%2, %0|%0, %2}"
19343 [(set_attr "type" "mmxadd")
19344 (set_attr "mode" "DI")])
19345
19346(define_insn "ssaddv8qi3"
19347 [(set (match_operand:V8QI 0 "register_operand" "=y")
18822 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19348 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
19349 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19350 "TARGET_MMX"
19351 "paddsb\t{%2, %0|%0, %2}"
18826 [(set_attr "type" "mmx")])
19352 [(set_attr "type" "mmxadd")
19353 (set_attr "mode" "DI")])
19354
19355(define_insn "ssaddv4hi3"
19356 [(set (match_operand:V4HI 0 "register_operand" "=y")
18830 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19357 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
19358 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19359 "TARGET_MMX"
19360 "paddsw\t{%2, %0|%0, %2}"
18834 [(set_attr "type" "mmx")])
19361 [(set_attr "type" "mmxadd")
19362 (set_attr "mode" "DI")])
19363
19364(define_insn "usaddv8qi3"
19365 [(set (match_operand:V8QI 0 "register_operand" "=y")
18838 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19366 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
19367 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19368 "TARGET_MMX"
19369 "paddusb\t{%2, %0|%0, %2}"
18842 [(set_attr "type" "mmx")])
19370 [(set_attr "type" "mmxadd")
19371 (set_attr "mode" "DI")])
19372
19373(define_insn "usaddv4hi3"
19374 [(set (match_operand:V4HI 0 "register_operand" "=y")
18846 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19375 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
19376 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19377 "TARGET_MMX"
19378 "paddusw\t{%2, %0|%0, %2}"
18850 [(set_attr "type" "mmx")])
19379 [(set_attr "type" "mmxadd")
19380 (set_attr "mode" "DI")])
19381
19382(define_insn "subv8qi3"
19383 [(set (match_operand:V8QI 0 "register_operand" "=y")
19384 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19385 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19386 "TARGET_MMX"
19387 "psubb\t{%2, %0|%0, %2}"
18858 [(set_attr "type" "mmx")])
19388 [(set_attr "type" "mmxadd")
19389 (set_attr "mode" "DI")])
19390
19391(define_insn "subv4hi3"
19392 [(set (match_operand:V4HI 0 "register_operand" "=y")
19393 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19394 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19395 "TARGET_MMX"
19396 "psubw\t{%2, %0|%0, %2}"
18866 [(set_attr "type" "mmx")])
19397 [(set_attr "type" "mmxadd")
19398 (set_attr "mode" "DI")])
19399
19400(define_insn "subv2si3"
19401 [(set (match_operand:V2SI 0 "register_operand" "=y")
19402 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
19403 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
19404 "TARGET_MMX"
19405 "psubd\t{%2, %0|%0, %2}"
18874 [(set_attr "type" "mmx")])
19406 [(set_attr "type" "mmxadd")
19407 (set_attr "mode" "DI")])
19408
19409(define_insn "mmx_subdi3"
19410 [(set (match_operand:DI 0 "register_operand" "=y")
19411 (unspec:DI
19412 [(minus:DI (match_operand:DI 1 "register_operand" "0")
19413 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19414 UNSPEC_NOP))]
19415 "TARGET_MMX"
19416 "psubq\t{%2, %0|%0, %2}"
19417 [(set_attr "type" "mmxadd")
19418 (set_attr "mode" "DI")])
19419
19420(define_insn "sssubv8qi3"
19421 [(set (match_operand:V8QI 0 "register_operand" "=y")
19422 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19423 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19424 "TARGET_MMX"
19425 "psubsb\t{%2, %0|%0, %2}"
18882 [(set_attr "type" "mmx")])
19426 [(set_attr "type" "mmxadd")
19427 (set_attr "mode" "DI")])
19428
19429(define_insn "sssubv4hi3"
19430 [(set (match_operand:V4HI 0 "register_operand" "=y")
19431 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19432 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19433 "TARGET_MMX"
19434 "psubsw\t{%2, %0|%0, %2}"
18890 [(set_attr "type" "mmx")])
19435 [(set_attr "type" "mmxadd")
19436 (set_attr "mode" "DI")])
19437
19438(define_insn "ussubv8qi3"
19439 [(set (match_operand:V8QI 0 "register_operand" "=y")
19440 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19441 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19442 "TARGET_MMX"
19443 "psubusb\t{%2, %0|%0, %2}"
18898 [(set_attr "type" "mmx")])
19444 [(set_attr "type" "mmxadd")
19445 (set_attr "mode" "DI")])
19446
19447(define_insn "ussubv4hi3"
19448 [(set (match_operand:V4HI 0 "register_operand" "=y")
19449 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19450 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19451 "TARGET_MMX"
19452 "psubusw\t{%2, %0|%0, %2}"
18906 [(set_attr "type" "mmx")])
19453 [(set_attr "type" "mmxadd")
19454 (set_attr "mode" "DI")])
19455
19456(define_insn "mulv4hi3"
19457 [(set (match_operand:V4HI 0 "register_operand" "=y")
19458 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
19459 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19460 "TARGET_MMX"
19461 "pmullw\t{%2, %0|%0, %2}"
18914 [(set_attr "type" "mmx")])
19462 [(set_attr "type" "mmxmul")
19463 (set_attr "mode" "DI")])
19464
19465(define_insn "smulv4hi3_highpart"
19466 [(set (match_operand:V4HI 0 "register_operand" "=y")
19467 (truncate:V4HI
19468 (lshiftrt:V4SI
19469 (mult:V4SI (sign_extend:V4SI
19470 (match_operand:V4HI 1 "register_operand" "0"))
19471 (sign_extend:V4SI
19472 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
19473 (const_int 16))))]
19474 "TARGET_MMX"
19475 "pmulhw\t{%2, %0|%0, %2}"
18927 [(set_attr "type" "mmx")])
19476 [(set_attr "type" "mmxmul")
19477 (set_attr "mode" "DI")])
19478
19479(define_insn "umulv4hi3_highpart"
19480 [(set (match_operand:V4HI 0 "register_operand" "=y")
19481 (truncate:V4HI
19482 (lshiftrt:V4SI
19483 (mult:V4SI (zero_extend:V4SI
19484 (match_operand:V4HI 1 "register_operand" "0"))
19485 (zero_extend:V4SI
19486 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
19487 (const_int 16))))]
19488 "TARGET_SSE || TARGET_3DNOW_A"
19489 "pmulhuw\t{%2, %0|%0, %2}"
18940 [(set_attr "type" "mmx")])
19490 [(set_attr "type" "mmxmul")
19491 (set_attr "mode" "DI")])
19492
19493(define_insn "mmx_pmaddwd"
19494 [(set (match_operand:V2SI 0 "register_operand" "=y")
19495 (plus:V2SI
19496 (mult:V2SI
19497 (sign_extend:V2SI
19498 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
19499 (parallel [(const_int 0) (const_int 2)])))

--- 4 unchanged lines hidden (view full) ---

19504 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
19505 (parallel [(const_int 1)
19506 (const_int 3)])))
19507 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
19508 (parallel [(const_int 1)
19509 (const_int 3)]))))))]
19510 "TARGET_MMX"
19511 "pmaddwd\t{%2, %0|%0, %2}"
18961 [(set_attr "type" "mmx")])
19512 [(set_attr "type" "mmxmul")
19513 (set_attr "mode" "DI")])
19514
19515
19516;; MMX logical operations
19517;; Note we don't want to declare these as regular iordi3 insns to prevent
19518;; normal code that also wants to use the FPU from getting broken.
19519;; The UNSPECs are there to prevent the combiner from getting overly clever.
19520(define_insn "mmx_iordi3"
19521 [(set (match_operand:DI 0 "register_operand" "=y")
19522 (unspec:DI
18971 [(ior:DI (match_operand:DI 1 "register_operand" "0")
18972 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
19523 [(ior:DI (match_operand:DI 1 "register_operand" "%0")
19524 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19525 UNSPEC_NOP))]
19526 "TARGET_MMX"
19527 "por\t{%2, %0|%0, %2}"
18975 [(set_attr "type" "mmx")])
19528 [(set_attr "type" "mmxadd")
19529 (set_attr "mode" "DI")])
19530
19531(define_insn "mmx_xordi3"
19532 [(set (match_operand:DI 0 "register_operand" "=y")
19533 (unspec:DI
18980 [(xor:DI (match_operand:DI 1 "register_operand" "0")
18981 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
19534 [(xor:DI (match_operand:DI 1 "register_operand" "%0")
19535 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19536 UNSPEC_NOP))]
19537 "TARGET_MMX"
19538 "pxor\t{%2, %0|%0, %2}"
18984 [(set_attr "type" "mmx")
19539 [(set_attr "type" "mmxadd")
19540 (set_attr "mode" "DI")
19541 (set_attr "memory" "none")])
19542
19543;; Same as pxor, but don't show input operands so that we don't think
19544;; they are live.
19545(define_insn "mmx_clrdi"
19546 [(set (match_operand:DI 0 "register_operand" "=y")
18991 (unspec:DI [(const_int 0)] 45))]
19547 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
19548 "TARGET_MMX"
19549 "pxor\t{%0, %0|%0, %0}"
18994 [(set_attr "type" "mmx")
19550 [(set_attr "type" "mmxadd")
19551 (set_attr "mode" "DI")
19552 (set_attr "memory" "none")])
19553
19554(define_insn "mmx_anddi3"
19555 [(set (match_operand:DI 0 "register_operand" "=y")
19556 (unspec:DI
19000 [(and:DI (match_operand:DI 1 "register_operand" "0")
19001 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
19557 [(and:DI (match_operand:DI 1 "register_operand" "%0")
19558 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19559 UNSPEC_NOP))]
19560 "TARGET_MMX"
19561 "pand\t{%2, %0|%0, %2}"
19004 [(set_attr "type" "mmx")])
19562 [(set_attr "type" "mmxadd")
19563 (set_attr "mode" "DI")])
19564
19565(define_insn "mmx_nanddi3"
19566 [(set (match_operand:DI 0 "register_operand" "=y")
19567 (unspec:DI
19568 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
19010 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
19569 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19570 UNSPEC_NOP))]
19571 "TARGET_MMX"
19572 "pandn\t{%2, %0|%0, %2}"
19013 [(set_attr "type" "mmx")])
19573 [(set_attr "type" "mmxadd")
19574 (set_attr "mode" "DI")])
19575
19576
19577;; MMX unsigned averages/sum of absolute differences
19578
19579(define_insn "mmx_uavgv8qi3"
19580 [(set (match_operand:V8QI 0 "register_operand" "=y")
19581 (ashiftrt:V8QI
19582 (plus:V8QI (plus:V8QI

--- 5 unchanged lines hidden (view full) ---

19588 (const_int 1)
19589 (const_int 1)
19590 (const_int 1)
19591 (const_int 1)
19592 (const_int 1)]))
19593 (const_int 1)))]
19594 "TARGET_SSE || TARGET_3DNOW_A"
19595 "pavgb\t{%2, %0|%0, %2}"
19035 [(set_attr "type" "sse")])
19596 [(set_attr "type" "mmxshft")
19597 (set_attr "mode" "DI")])
19598
19599(define_insn "mmx_uavgv4hi3"
19600 [(set (match_operand:V4HI 0 "register_operand" "=y")
19601 (ashiftrt:V4HI
19602 (plus:V4HI (plus:V4HI
19603 (match_operand:V4HI 1 "register_operand" "0")
19604 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
19605 (const_vector:V4HI [(const_int 1)
19606 (const_int 1)
19607 (const_int 1)
19608 (const_int 1)]))
19609 (const_int 1)))]
19610 "TARGET_SSE || TARGET_3DNOW_A"
19611 "pavgw\t{%2, %0|%0, %2}"
19050 [(set_attr "type" "sse")])
19612 [(set_attr "type" "mmxshft")
19613 (set_attr "mode" "DI")])
19614
19615(define_insn "mmx_psadbw"
19053 [(set (match_operand:V8QI 0 "register_operand" "=y")
19054 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19055 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))))]
19616 [(set (match_operand:DI 0 "register_operand" "=y")
19617 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
19618 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
19619 UNSPEC_PSADBW))]
19620 "TARGET_SSE || TARGET_3DNOW_A"
19621 "psadbw\t{%2, %0|%0, %2}"
19058 [(set_attr "type" "sse")])
19622 [(set_attr "type" "mmxshft")
19623 (set_attr "mode" "DI")])
19624
19625
19626;; MMX insert/extract/shuffle
19627
19628(define_insn "mmx_pinsrw"
19629 [(set (match_operand:V4HI 0 "register_operand" "=y")
19630 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
19631 (vec_duplicate:V4HI
19632 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
19633 (match_operand:SI 3 "immediate_operand" "i")))]
19634 "TARGET_SSE || TARGET_3DNOW_A"
19635 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
19071 [(set_attr "type" "sse")])
19636 [(set_attr "type" "mmxcvt")
19637 (set_attr "mode" "DI")])
19638
19639(define_insn "mmx_pextrw"
19640 [(set (match_operand:SI 0 "register_operand" "=r")
19641 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
19642 (parallel
19643 [(match_operand:SI 2 "immediate_operand" "i")]))))]
19644 "TARGET_SSE || TARGET_3DNOW_A"
19645 "pextrw\t{%2, %1, %0|%0, %1, %2}"
19080 [(set_attr "type" "sse")])
19646 [(set_attr "type" "mmxcvt")
19647 (set_attr "mode" "DI")])
19648
19649(define_insn "mmx_pshufw"
19650 [(set (match_operand:V4HI 0 "register_operand" "=y")
19651 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
19085 (match_operand:SI 2 "immediate_operand" "i")] 41))]
19652 (match_operand:SI 2 "immediate_operand" "i")]
19653 UNSPEC_SHUFFLE))]
19654 "TARGET_SSE || TARGET_3DNOW_A"
19655 "pshufw\t{%2, %1, %0|%0, %1, %2}"
19088 [(set_attr "type" "sse")])
19656 [(set_attr "type" "mmxcvt")
19657 (set_attr "mode" "DI")])
19658
19659
19660;; MMX mask-generating comparisons
19661
19662(define_insn "eqv8qi3"
19663 [(set (match_operand:V8QI 0 "register_operand" "=y")
19664 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
19665 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19666 "TARGET_MMX"
19667 "pcmpeqb\t{%2, %0|%0, %2}"
19099 [(set_attr "type" "mmx")])
19668 [(set_attr "type" "mmxcmp")
19669 (set_attr "mode" "DI")])
19670
19671(define_insn "eqv4hi3"
19672 [(set (match_operand:V4HI 0 "register_operand" "=y")
19673 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
19674 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19675 "TARGET_MMX"
19676 "pcmpeqw\t{%2, %0|%0, %2}"
19107 [(set_attr "type" "mmx")])
19677 [(set_attr "type" "mmxcmp")
19678 (set_attr "mode" "DI")])
19679
19680(define_insn "eqv2si3"
19681 [(set (match_operand:V2SI 0 "register_operand" "=y")
19682 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
19683 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
19684 "TARGET_MMX"
19685 "pcmpeqd\t{%2, %0|%0, %2}"
19115 [(set_attr "type" "mmx")])
19686 [(set_attr "type" "mmxcmp")
19687 (set_attr "mode" "DI")])
19688
19689(define_insn "gtv8qi3"
19690 [(set (match_operand:V8QI 0 "register_operand" "=y")
19691 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
19692 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19693 "TARGET_MMX"
19694 "pcmpgtb\t{%2, %0|%0, %2}"
19123 [(set_attr "type" "mmx")])
19695 [(set_attr "type" "mmxcmp")
19696 (set_attr "mode" "DI")])
19697
19698(define_insn "gtv4hi3"
19699 [(set (match_operand:V4HI 0 "register_operand" "=y")
19700 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
19701 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19702 "TARGET_MMX"
19703 "pcmpgtw\t{%2, %0|%0, %2}"
19131 [(set_attr "type" "mmx")])
19704 [(set_attr "type" "mmxcmp")
19705 (set_attr "mode" "DI")])
19706
19707(define_insn "gtv2si3"
19708 [(set (match_operand:V2SI 0 "register_operand" "=y")
19709 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
19710 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
19711 "TARGET_MMX"
19712 "pcmpgtd\t{%2, %0|%0, %2}"
19139 [(set_attr "type" "mmx")])
19713 [(set_attr "type" "mmxcmp")
19714 (set_attr "mode" "DI")])
19715
19716
19717;; MMX max/min insns
19718
19719(define_insn "umaxv8qi3"
19720 [(set (match_operand:V8QI 0 "register_operand" "=y")
19721 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
19722 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19723 "TARGET_SSE || TARGET_3DNOW_A"
19724 "pmaxub\t{%2, %0|%0, %2}"
19150 [(set_attr "type" "sse")])
19725 [(set_attr "type" "mmxadd")
19726 (set_attr "mode" "DI")])
19727
19728(define_insn "smaxv4hi3"
19729 [(set (match_operand:V4HI 0 "register_operand" "=y")
19730 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
19731 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19732 "TARGET_SSE || TARGET_3DNOW_A"
19733 "pmaxsw\t{%2, %0|%0, %2}"
19158 [(set_attr "type" "sse")])
19734 [(set_attr "type" "mmxadd")
19735 (set_attr "mode" "DI")])
19736
19737(define_insn "uminv8qi3"
19738 [(set (match_operand:V8QI 0 "register_operand" "=y")
19739 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
19740 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19741 "TARGET_SSE || TARGET_3DNOW_A"
19742 "pminub\t{%2, %0|%0, %2}"
19166 [(set_attr "type" "sse")])
19743 [(set_attr "type" "mmxadd")
19744 (set_attr "mode" "DI")])
19745
19746(define_insn "sminv4hi3"
19747 [(set (match_operand:V4HI 0 "register_operand" "=y")
19748 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
19749 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19750 "TARGET_SSE || TARGET_3DNOW_A"
19751 "pminsw\t{%2, %0|%0, %2}"
19174 [(set_attr "type" "sse")])
19752 [(set_attr "type" "mmxadd")
19753 (set_attr "mode" "DI")])
19754
19755
19756;; MMX shifts
19757
19758(define_insn "ashrv4hi3"
19759 [(set (match_operand:V4HI 0 "register_operand" "=y")
19760 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
19761 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19762 "TARGET_MMX"
19763 "psraw\t{%2, %0|%0, %2}"
19185 [(set_attr "type" "mmx")])
19764 [(set_attr "type" "mmxshft")
19765 (set_attr "mode" "DI")])
19766
19767(define_insn "ashrv2si3"
19768 [(set (match_operand:V2SI 0 "register_operand" "=y")
19769 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
19770 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19771 "TARGET_MMX"
19772 "psrad\t{%2, %0|%0, %2}"
19193 [(set_attr "type" "mmx")])
19773 [(set_attr "type" "mmxshft")
19774 (set_attr "mode" "DI")])
19775
19776(define_insn "lshrv4hi3"
19777 [(set (match_operand:V4HI 0 "register_operand" "=y")
19778 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
19779 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19780 "TARGET_MMX"
19781 "psrlw\t{%2, %0|%0, %2}"
19201 [(set_attr "type" "mmx")])
19782 [(set_attr "type" "mmxshft")
19783 (set_attr "mode" "DI")])
19784
19785(define_insn "lshrv2si3"
19786 [(set (match_operand:V2SI 0 "register_operand" "=y")
19787 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
19788 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19789 "TARGET_MMX"
19790 "psrld\t{%2, %0|%0, %2}"
19209 [(set_attr "type" "mmx")])
19791 [(set_attr "type" "mmxshft")
19792 (set_attr "mode" "DI")])
19793
19794;; See logical MMX insns.
19795(define_insn "mmx_lshrdi3"
19796 [(set (match_operand:DI 0 "register_operand" "=y")
19797 (unspec:DI
19798 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
19216 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
19799 (match_operand:DI 2 "nonmemory_operand" "yi"))]
19800 UNSPEC_NOP))]
19801 "TARGET_MMX"
19802 "psrlq\t{%2, %0|%0, %2}"
19219 [(set_attr "type" "mmx")])
19803 [(set_attr "type" "mmxshft")
19804 (set_attr "mode" "DI")])
19805
19806(define_insn "ashlv4hi3"
19807 [(set (match_operand:V4HI 0 "register_operand" "=y")
19808 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
19809 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19810 "TARGET_MMX"
19811 "psllw\t{%2, %0|%0, %2}"
19227 [(set_attr "type" "mmx")])
19812 [(set_attr "type" "mmxshft")
19813 (set_attr "mode" "DI")])
19814
19815(define_insn "ashlv2si3"
19816 [(set (match_operand:V2SI 0 "register_operand" "=y")
19817 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
19818 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19819 "TARGET_MMX"
19820 "pslld\t{%2, %0|%0, %2}"
19235 [(set_attr "type" "mmx")])
19821 [(set_attr "type" "mmxshft")
19822 (set_attr "mode" "DI")])
19823
19824;; See logical MMX insns.
19825(define_insn "mmx_ashldi3"
19826 [(set (match_operand:DI 0 "register_operand" "=y")
19827 (unspec:DI
19828 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
19242 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
19829 (match_operand:DI 2 "nonmemory_operand" "yi"))]
19830 UNSPEC_NOP))]
19831 "TARGET_MMX"
19832 "psllq\t{%2, %0|%0, %2}"
19245 [(set_attr "type" "mmx")])
19833 [(set_attr "type" "mmxshft")
19834 (set_attr "mode" "DI")])
19835
19836
19837;; MMX pack/unpack insns.
19838
19839(define_insn "mmx_packsswb"
19840 [(set (match_operand:V8QI 0 "register_operand" "=y")
19841 (vec_concat:V8QI
19842 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
19843 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
19844 "TARGET_MMX"
19845 "packsswb\t{%2, %0|%0, %2}"
19257 [(set_attr "type" "mmx")])
19846 [(set_attr "type" "mmxshft")
19847 (set_attr "mode" "DI")])
19848
19849(define_insn "mmx_packssdw"
19850 [(set (match_operand:V4HI 0 "register_operand" "=y")
19851 (vec_concat:V4HI
19852 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
19853 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
19854 "TARGET_MMX"
19855 "packssdw\t{%2, %0|%0, %2}"
19266 [(set_attr "type" "mmx")])
19856 [(set_attr "type" "mmxshft")
19857 (set_attr "mode" "DI")])
19858
19859(define_insn "mmx_packuswb"
19860 [(set (match_operand:V8QI 0 "register_operand" "=y")
19861 (vec_concat:V8QI
19862 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
19863 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
19864 "TARGET_MMX"
19865 "packuswb\t{%2, %0|%0, %2}"
19275 [(set_attr "type" "mmx")])
19866 [(set_attr "type" "mmxshft")
19867 (set_attr "mode" "DI")])
19868
19869(define_insn "mmx_punpckhbw"
19870 [(set (match_operand:V8QI 0 "register_operand" "=y")
19871 (vec_merge:V8QI
19872 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
19873 (parallel [(const_int 4)
19874 (const_int 0)
19875 (const_int 5)

--- 9 unchanged lines hidden (view full) ---

19885 (const_int 5)
19886 (const_int 2)
19887 (const_int 6)
19888 (const_int 3)
19889 (const_int 7)]))
19890 (const_int 85)))]
19891 "TARGET_MMX"
19892 "punpckhbw\t{%2, %0|%0, %2}"
19301 [(set_attr "type" "mmx")])
19893 [(set_attr "type" "mmxcvt")
19894 (set_attr "mode" "DI")])
19895
19896(define_insn "mmx_punpckhwd"
19897 [(set (match_operand:V4HI 0 "register_operand" "=y")
19898 (vec_merge:V4HI
19899 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19900 (parallel [(const_int 0)
19901 (const_int 2)
19902 (const_int 1)
19903 (const_int 3)]))
19904 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19905 (parallel [(const_int 2)
19906 (const_int 0)
19907 (const_int 3)
19908 (const_int 1)]))
19909 (const_int 5)))]
19910 "TARGET_MMX"
19911 "punpckhwd\t{%2, %0|%0, %2}"
19319 [(set_attr "type" "mmx")])
19912 [(set_attr "type" "mmxcvt")
19913 (set_attr "mode" "DI")])
19914
19915(define_insn "mmx_punpckhdq"
19916 [(set (match_operand:V2SI 0 "register_operand" "=y")
19917 (vec_merge:V2SI
19324 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19325 (parallel [(const_int 0)
19326 (const_int 1)]))
19918 (match_operand:V2SI 1 "register_operand" "0")
19919 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19920 (parallel [(const_int 1)
19921 (const_int 0)]))
19922 (const_int 1)))]
19923 "TARGET_MMX"
19924 "punpckhdq\t{%2, %0|%0, %2}"
19333 [(set_attr "type" "mmx")])
19925 [(set_attr "type" "mmxcvt")
19926 (set_attr "mode" "DI")])
19927
19928(define_insn "mmx_punpcklbw"
19929 [(set (match_operand:V8QI 0 "register_operand" "=y")
19930 (vec_merge:V8QI
19931 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
19932 (parallel [(const_int 0)
19933 (const_int 4)
19934 (const_int 1)

--- 9 unchanged lines hidden (view full) ---

19944 (const_int 1)
19945 (const_int 6)
19946 (const_int 2)
19947 (const_int 7)
19948 (const_int 3)]))
19949 (const_int 85)))]
19950 "TARGET_MMX"
19951 "punpcklbw\t{%2, %0|%0, %2}"
19359 [(set_attr "type" "mmx")])
19952 [(set_attr "type" "mmxcvt")
19953 (set_attr "mode" "DI")])
19954
19955(define_insn "mmx_punpcklwd"
19956 [(set (match_operand:V4HI 0 "register_operand" "=y")
19957 (vec_merge:V4HI
19958 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19959 (parallel [(const_int 2)
19960 (const_int 0)
19961 (const_int 3)
19962 (const_int 1)]))
19963 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19964 (parallel [(const_int 0)
19965 (const_int 2)
19966 (const_int 1)
19967 (const_int 3)]))
19968 (const_int 5)))]
19969 "TARGET_MMX"
19970 "punpcklwd\t{%2, %0|%0, %2}"
19377 [(set_attr "type" "mmx")])
19971 [(set_attr "type" "mmxcvt")
19972 (set_attr "mode" "DI")])
19973
19974(define_insn "mmx_punpckldq"
19975 [(set (match_operand:V2SI 0 "register_operand" "=y")
19976 (vec_merge:V2SI
19977 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19978 (parallel [(const_int 1)
19979 (const_int 0)]))
19385 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19386 (parallel [(const_int 0)
19387 (const_int 1)]))
19980 (match_operand:V2SI 2 "register_operand" "y")
19981 (const_int 1)))]
19982 "TARGET_MMX"
19983 "punpckldq\t{%2, %0|%0, %2}"
19391 [(set_attr "type" "mmx")])
19984 [(set_attr "type" "mmxcvt")
19985 (set_attr "mode" "DI")])
19986
19987
19988;; Miscellaneous stuff
19989
19990(define_insn "emms"
19397 [(unspec_volatile [(const_int 0)] 31)
19991 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
19992 (clobber (reg:XF 8))
19993 (clobber (reg:XF 9))
19994 (clobber (reg:XF 10))
19995 (clobber (reg:XF 11))
19996 (clobber (reg:XF 12))
19997 (clobber (reg:XF 13))
19998 (clobber (reg:XF 14))
19999 (clobber (reg:XF 15))

--- 6 unchanged lines hidden (view full) ---

20006 (clobber (reg:DI 35))
20007 (clobber (reg:DI 36))]
20008 "TARGET_MMX"
20009 "emms"
20010 [(set_attr "type" "mmx")
20011 (set_attr "memory" "unknown")])
20012
20013(define_insn "ldmxcsr"
19420 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 37)]
19421 "TARGET_MMX"
20014 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
20015 UNSPECV_LDMXCSR)]
20016 "TARGET_SSE"
20017 "ldmxcsr\t%0"
19423 [(set_attr "type" "mmx")
20018 [(set_attr "type" "sse")
20019 (set_attr "memory" "load")])
20020
20021(define_insn "stmxcsr"
20022 [(set (match_operand:SI 0 "memory_operand" "=m")
19428 (unspec_volatile:SI [(const_int 0)] 40))]
19429 "TARGET_MMX"
20023 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
20024 "TARGET_SSE"
20025 "stmxcsr\t%0"
19431 [(set_attr "type" "mmx")
20026 [(set_attr "type" "sse")
20027 (set_attr "memory" "store")])
20028
20029(define_expand "sfence"
20030 [(set (match_dup 0)
19436 (unspec:BLK [(match_dup 0)] 44))]
20031 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
20032 "TARGET_SSE || TARGET_3DNOW_A"
20033{
20034 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
20035 MEM_VOLATILE_P (operands[0]) = 1;
20036})
20037
20038(define_insn "*sfence_insn"
20039 [(set (match_operand:BLK 0 "" "")
19445 (unspec:BLK [(match_dup 0)] 44))]
20040 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
20041 "TARGET_SSE || TARGET_3DNOW_A"
20042 "sfence"
20043 [(set_attr "type" "sse")
20044 (set_attr "memory" "unknown")])
20045
20046(define_expand "sse_prologue_save"
20047 [(parallel [(set (match_operand:BLK 0 "" "")
20048 (unspec:BLK [(reg:DI 21)
20049 (reg:DI 22)
20050 (reg:DI 23)
20051 (reg:DI 24)
20052 (reg:DI 25)
20053 (reg:DI 26)
20054 (reg:DI 27)
19460 (reg:DI 28)] 13))
20055 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
20056 (use (match_operand:DI 1 "register_operand" ""))
20057 (use (match_operand:DI 2 "immediate_operand" ""))
20058 (use (label_ref:DI (match_operand 3 "" "")))])]
20059 "TARGET_64BIT"
20060 "")
20061
20062(define_insn "*sse_prologue_save_insn"
20063 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
20064 (match_operand:DI 4 "const_int_operand" "n")))
20065 (unspec:BLK [(reg:DI 21)
20066 (reg:DI 22)
20067 (reg:DI 23)
20068 (reg:DI 24)
20069 (reg:DI 25)
20070 (reg:DI 26)
20071 (reg:DI 27)
19477 (reg:DI 28)] 13))
20072 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
20073 (use (match_operand:DI 1 "register_operand" "r"))
20074 (use (match_operand:DI 2 "const_int_operand" "i"))
20075 (use (label_ref:DI (match_operand 3 "" "X")))]
20076 "TARGET_64BIT
20077 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
20078 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
20079 "*
20080{

--- 26 unchanged lines hidden (view full) ---

20107;; 3Dnow! instructions
20108
20109(define_insn "addv2sf3"
20110 [(set (match_operand:V2SF 0 "register_operand" "=y")
20111 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
20112 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20113 "TARGET_3DNOW"
20114 "pfadd\\t{%2, %0|%0, %2}"
19520 [(set_attr "type" "mmx")])
20115 [(set_attr "type" "mmxadd")
20116 (set_attr "mode" "V2SF")])
20117
20118(define_insn "subv2sf3"
20119 [(set (match_operand:V2SF 0 "register_operand" "=y")
20120 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
20121 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20122 "TARGET_3DNOW"
20123 "pfsub\\t{%2, %0|%0, %2}"
19528 [(set_attr "type" "mmx")])
20124 [(set_attr "type" "mmxadd")
20125 (set_attr "mode" "V2SF")])
20126
20127(define_insn "subrv2sf3"
20128 [(set (match_operand:V2SF 0 "register_operand" "=y")
20129 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
20130 (match_operand:V2SF 1 "register_operand" "0")))]
20131 "TARGET_3DNOW"
20132 "pfsubr\\t{%2, %0|%0, %2}"
19536 [(set_attr "type" "mmx")])
20133 [(set_attr "type" "mmxadd")
20134 (set_attr "mode" "V2SF")])
20135
20136(define_insn "gtv2sf3"
20137 [(set (match_operand:V2SI 0 "register_operand" "=y")
20138 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
20139 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20140 "TARGET_3DNOW"
20141 "pfcmpgt\\t{%2, %0|%0, %2}"
19544 [(set_attr "type" "mmx")])
20142 [(set_attr "type" "mmxcmp")
20143 (set_attr "mode" "V2SF")])
20144
20145(define_insn "gev2sf3"
20146 [(set (match_operand:V2SI 0 "register_operand" "=y")
20147 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
20148 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20149 "TARGET_3DNOW"
20150 "pfcmpge\\t{%2, %0|%0, %2}"
19552 [(set_attr "type" "mmx")])
20151 [(set_attr "type" "mmxcmp")
20152 (set_attr "mode" "V2SF")])
20153
20154(define_insn "eqv2sf3"
20155 [(set (match_operand:V2SI 0 "register_operand" "=y")
20156 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
20157 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20158 "TARGET_3DNOW"
20159 "pfcmpeq\\t{%2, %0|%0, %2}"
19560 [(set_attr "type" "mmx")])
20160 [(set_attr "type" "mmxcmp")
20161 (set_attr "mode" "V2SF")])
20162
20163(define_insn "pfmaxv2sf3"
20164 [(set (match_operand:V2SF 0 "register_operand" "=y")
20165 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
20166 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20167 "TARGET_3DNOW"
20168 "pfmax\\t{%2, %0|%0, %2}"
19568 [(set_attr "type" "mmx")])
20169 [(set_attr "type" "mmxadd")
20170 (set_attr "mode" "V2SF")])
20171
20172(define_insn "pfminv2sf3"
20173 [(set (match_operand:V2SF 0 "register_operand" "=y")
20174 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
20175 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20176 "TARGET_3DNOW"
20177 "pfmin\\t{%2, %0|%0, %2}"
19576 [(set_attr "type" "mmx")])
20178 [(set_attr "type" "mmxadd")
20179 (set_attr "mode" "V2SF")])
20180
20181(define_insn "mulv2sf3"
20182 [(set (match_operand:V2SF 0 "register_operand" "=y")
20183 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
20184 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20185 "TARGET_3DNOW"
20186 "pfmul\\t{%2, %0|%0, %2}"
19584 [(set_attr "type" "mmx")])
20187 [(set_attr "type" "mmxmul")
20188 (set_attr "mode" "V2SF")])
20189
20190(define_insn "femms"
19587 [(unspec_volatile [(const_int 0)] 46)
20191 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
20192 (clobber (reg:XF 8))
20193 (clobber (reg:XF 9))
20194 (clobber (reg:XF 10))
20195 (clobber (reg:XF 11))
20196 (clobber (reg:XF 12))
20197 (clobber (reg:XF 13))
20198 (clobber (reg:XF 14))
20199 (clobber (reg:XF 15))
20200 (clobber (reg:DI 29))
20201 (clobber (reg:DI 30))
20202 (clobber (reg:DI 31))
20203 (clobber (reg:DI 32))
20204 (clobber (reg:DI 33))
20205 (clobber (reg:DI 34))
20206 (clobber (reg:DI 35))
20207 (clobber (reg:DI 36))]
20208 "TARGET_3DNOW"
20209 "femms"
19606 [(set_attr "type" "mmx")])
20210 [(set_attr "type" "mmx")
20211 (set_attr "memory" "none")])
20212
20213(define_insn "pf2id"
20214 [(set (match_operand:V2SI 0 "register_operand" "=y")
20215 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
20216 "TARGET_3DNOW"
20217 "pf2id\\t{%1, %0|%0, %1}"
19613 [(set_attr "type" "mmx")])
20218 [(set_attr "type" "mmxcvt")
20219 (set_attr "mode" "V2SF")])
20220
20221(define_insn "pf2iw"
20222 [(set (match_operand:V2SI 0 "register_operand" "=y")
20223 (sign_extend:V2SI
20224 (ss_truncate:V2HI
20225 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
20226 "TARGET_3DNOW_A"
20227 "pf2iw\\t{%1, %0|%0, %1}"
19622 [(set_attr "type" "mmx")])
20228 [(set_attr "type" "mmxcvt")
20229 (set_attr "mode" "V2SF")])
20230
20231(define_insn "pfacc"
20232 [(set (match_operand:V2SF 0 "register_operand" "=y")
20233 (vec_concat:V2SF
20234 (plus:SF
20235 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
20236 (parallel [(const_int 0)]))
20237 (vec_select:SF (match_dup 1)
20238 (parallel [(const_int 1)])))
20239 (plus:SF
20240 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
20241 (parallel [(const_int 0)]))
20242 (vec_select:SF (match_dup 2)
20243 (parallel [(const_int 1)])))))]
20244 "TARGET_3DNOW"
20245 "pfacc\\t{%2, %0|%0, %2}"
19639 [(set_attr "type" "mmx")])
20246 [(set_attr "type" "mmxadd")
20247 (set_attr "mode" "V2SF")])
20248
20249(define_insn "pfnacc"
20250 [(set (match_operand:V2SF 0 "register_operand" "=y")
20251 (vec_concat:V2SF
20252 (minus:SF
20253 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
20254 (parallel [(const_int 0)]))
20255 (vec_select:SF (match_dup 1)
20256 (parallel [(const_int 1)])))
20257 (minus:SF
20258 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
20259 (parallel [(const_int 0)]))
20260 (vec_select:SF (match_dup 2)
20261 (parallel [(const_int 1)])))))]
20262 "TARGET_3DNOW_A"
20263 "pfnacc\\t{%2, %0|%0, %2}"
19656 [(set_attr "type" "mmx")])
20264 [(set_attr "type" "mmxadd")
20265 (set_attr "mode" "V2SF")])
20266
20267(define_insn "pfpnacc"
20268 [(set (match_operand:V2SF 0 "register_operand" "=y")
20269 (vec_concat:V2SF
20270 (minus:SF
20271 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
20272 (parallel [(const_int 0)]))
20273 (vec_select:SF (match_dup 1)
20274 (parallel [(const_int 1)])))
20275 (plus:SF
20276 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
20277 (parallel [(const_int 0)]))
20278 (vec_select:SF (match_dup 2)
20279 (parallel [(const_int 1)])))))]
20280 "TARGET_3DNOW_A"
20281 "pfpnacc\\t{%2, %0|%0, %2}"
19673 [(set_attr "type" "mmx")])
20282 [(set_attr "type" "mmxadd")
20283 (set_attr "mode" "V2SF")])
20284
20285(define_insn "pi2fw"
20286 [(set (match_operand:V2SF 0 "register_operand" "=y")
20287 (float:V2SF
20288 (vec_concat:V2SI
20289 (sign_extend:SI
20290 (truncate:HI
20291 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
20292 (parallel [(const_int 0)]))))
20293 (sign_extend:SI
20294 (truncate:HI
20295 (vec_select:SI (match_dup 1)
20296 (parallel [(const_int 1)])))))))]
20297 "TARGET_3DNOW_A"
20298 "pi2fw\\t{%1, %0|%0, %1}"
19689 [(set_attr "type" "mmx")])
20299 [(set_attr "type" "mmxcvt")
20300 (set_attr "mode" "V2SF")])
20301
20302(define_insn "floatv2si2"
20303 [(set (match_operand:V2SF 0 "register_operand" "=y")
20304 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
20305 "TARGET_3DNOW"
20306 "pi2fd\\t{%1, %0|%0, %1}"
19696 [(set_attr "type" "mmx")])
20307 [(set_attr "type" "mmxcvt")
20308 (set_attr "mode" "V2SF")])
20309
20310;; This insn is identical to pavgb in operation, but the opcode is
20311;; different. To avoid accidentally matching pavgb, use an unspec.
20312
20313(define_insn "pavgusb"
20314 [(set (match_operand:V8QI 0 "register_operand" "=y")
20315 (unspec:V8QI
20316 [(match_operand:V8QI 1 "register_operand" "0")
19705 (match_operand:V8QI 2 "nonimmediate_operand" "ym")] 49))]
20317 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
20318 UNSPEC_PAVGUSB))]
20319 "TARGET_3DNOW"
20320 "pavgusb\\t{%2, %0|%0, %2}"
19708 [(set_attr "type" "mmx")])
20321 [(set_attr "type" "mmxshft")
20322 (set_attr "mode" "TI")])
20323
20324;; 3DNow reciprical and sqrt
20325
20326(define_insn "pfrcpv2sf2"
20327 [(set (match_operand:V2SF 0 "register_operand" "=y")
19714 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 50))]
20328 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
20329 UNSPEC_PFRCP))]
20330 "TARGET_3DNOW"
20331 "pfrcp\\t{%1, %0|%0, %1}"
19717 [(set_attr "type" "mmx")])
20332 [(set_attr "type" "mmx")
20333 (set_attr "mode" "TI")])
20334
20335(define_insn "pfrcpit1v2sf3"
20336 [(set (match_operand:V2SF 0 "register_operand" "=y")
20337 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19722 (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 51))]
20338 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
20339 UNSPEC_PFRCPIT1))]
20340 "TARGET_3DNOW"
20341 "pfrcpit1\\t{%2, %0|%0, %2}"
19725 [(set_attr "type" "mmx")])
20342 [(set_attr "type" "mmx")
20343 (set_attr "mode" "TI")])
20344
20345(define_insn "pfrcpit2v2sf3"
20346 [(set (match_operand:V2SF 0 "register_operand" "=y")
20347 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19730 (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 52))]
20348 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
20349 UNSPEC_PFRCPIT2))]
20350 "TARGET_3DNOW"
20351 "pfrcpit2\\t{%2, %0|%0, %2}"
19733 [(set_attr "type" "mmx")])
20352 [(set_attr "type" "mmx")
20353 (set_attr "mode" "TI")])
20354
20355(define_insn "pfrsqrtv2sf2"
20356 [(set (match_operand:V2SF 0 "register_operand" "=y")
19737 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 53))]
20357 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
20358 UNSPEC_PFRSQRT))]
20359 "TARGET_3DNOW"
19739 "pfrsqrt\\t{%1, %0|%0, %1}"
19740 [(set_attr "type" "mmx")])
20360 "pfrsqrt\\t{%1, %0|%0, %1}"
20361 [(set_attr "type" "mmx")
20362 (set_attr "mode" "TI")])
20363
20364(define_insn "pfrsqit1v2sf3"
20365 [(set (match_operand:V2SF 0 "register_operand" "=y")
20366 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19745 (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 54))]
20367 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
20368 UNSPEC_PFRSQIT1))]
20369 "TARGET_3DNOW"
20370 "pfrsqit1\\t{%2, %0|%0, %2}"
19748 [(set_attr "type" "mmx")])
20371 [(set_attr "type" "mmx")
20372 (set_attr "mode" "TI")])
20373
20374(define_insn "pmulhrwv4hi3"
20375 [(set (match_operand:V4HI 0 "register_operand" "=y")
20376 (truncate:V4HI
20377 (lshiftrt:V4SI
20378 (plus:V4SI
20379 (mult:V4SI
20380 (sign_extend:V4SI
20381 (match_operand:V4HI 1 "register_operand" "0"))
20382 (sign_extend:V4SI
20383 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20384 (const_vector:V4SI [(const_int 32768)
20385 (const_int 32768)
20386 (const_int 32768)
20387 (const_int 32768)]))
20388 (const_int 16))))]
20389 "TARGET_3DNOW"
20390 "pmulhrw\\t{%2, %0|%0, %2}"
19767 [(set_attr "type" "mmx")])
20391 [(set_attr "type" "mmxmul")
20392 (set_attr "mode" "TI")])
20393
20394(define_insn "pswapdv2si2"
20395 [(set (match_operand:V2SI 0 "register_operand" "=y")
20396 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
20397 (parallel [(const_int 1) (const_int 0)])))]
20398 "TARGET_3DNOW_A"
20399 "pswapd\\t{%1, %0|%0, %1}"
19775 [(set_attr "type" "mmx")])
20400 [(set_attr "type" "mmxcvt")
20401 (set_attr "mode" "TI")])
20402
20403(define_insn "pswapdv2sf2"
20404 [(set (match_operand:V2SF 0 "register_operand" "=y")
20405 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
20406 (parallel [(const_int 1) (const_int 0)])))]
20407 "TARGET_3DNOW_A"
20408 "pswapd\\t{%1, %0|%0, %1}"
19783 [(set_attr "type" "mmx")])
20409 [(set_attr "type" "mmxcvt")
20410 (set_attr "mode" "TI")])
20411
20412(define_expand "prefetch"
20413 [(prefetch (match_operand 0 "address_operand" "")
20414 (match_operand:SI 1 "const_int_operand" "")
20415 (match_operand:SI 2 "const_int_operand" ""))]
20416 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
20417{
20418 int rw = INTVAL (operands[1]);

--- 46 unchanged lines hidden (view full) ---

20465 };
20466
20467 int locality = INTVAL (operands[1]);
20468 if (locality < 0 || locality > 3)
20469 abort ();
20470
20471 return patterns[locality];
20472}
19846 [(set_attr "type" "sse")])
20473 [(set_attr "type" "sse")
20474 (set_attr "memory" "none")])
20475
20476(define_insn "*prefetch_3dnow"
20477 [(prefetch (match_operand:SI 0 "address_operand" "p")
20478 (match_operand:SI 1 "const_int_operand" "n")
20479 (const_int 3))]
20480 "TARGET_3DNOW && !TARGET_64BIT"
20481{
20482 if (INTVAL (operands[1]) == 0)

--- 10 unchanged lines hidden (view full) ---

20493 (const_int 3))]
20494 "TARGET_3DNOW && TARGET_64BIT"
20495{
20496 if (INTVAL (operands[1]) == 0)
20497 return "prefetch\t%a0";
20498 else
20499 return "prefetchw\t%a0";
20500}
19873 [(set_attr "type" "mmx")])
20501 [(set_attr "type" "mmx")
20502 (set_attr "memory" "none")])
20503
20504;; SSE2 support
20505
20506(define_insn "addv2df3"
20507 [(set (match_operand:V2DF 0 "register_operand" "=x")
20508 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
20509 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20510 "TARGET_SSE2"
20511 "addpd\t{%2, %0|%0, %2}"
20512 [(set_attr "type" "sseadd")
20513 (set_attr "mode" "V2DF")])
20514
20515(define_insn "vmaddv2df3"
20516 [(set (match_operand:V2DF 0 "register_operand" "=x")
20517 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
20518 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20519 (match_dup 1)
20520 (const_int 1)))]
20521 "TARGET_SSE2"
20522 "addsd\t{%2, %0|%0, %2}"
20523 [(set_attr "type" "sseadd")
20524 (set_attr "mode" "DF")])
20525
20526(define_insn "subv2df3"
20527 [(set (match_operand:V2DF 0 "register_operand" "=x")
20528 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
20529 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20530 "TARGET_SSE2"
20531 "subpd\t{%2, %0|%0, %2}"
20532 [(set_attr "type" "sseadd")
20533 (set_attr "mode" "V2DF")])
20534
20535(define_insn "vmsubv2df3"
20536 [(set (match_operand:V2DF 0 "register_operand" "=x")
20537 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
20538 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20539 (match_dup 1)
20540 (const_int 1)))]
20541 "TARGET_SSE2"
20542 "subsd\t{%2, %0|%0, %2}"
20543 [(set_attr "type" "sseadd")
20544 (set_attr "mode" "DF")])
20545
20546(define_insn "mulv2df3"
20547 [(set (match_operand:V2DF 0 "register_operand" "=x")
20548 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
20549 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20550 "TARGET_SSE2"
20551 "mulpd\t{%2, %0|%0, %2}"
20552 [(set_attr "type" "ssemul")
20553 (set_attr "mode" "V2DF")])
20554
20555(define_insn "vmmulv2df3"
20556 [(set (match_operand:V2DF 0 "register_operand" "=x")
20557 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
20558 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20559 (match_dup 1)
20560 (const_int 1)))]
20561 "TARGET_SSE2"
20562 "mulsd\t{%2, %0|%0, %2}"
20563 [(set_attr "type" "ssemul")
20564 (set_attr "mode" "DF")])
20565
20566(define_insn "divv2df3"
20567 [(set (match_operand:V2DF 0 "register_operand" "=x")
20568 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
20569 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20570 "TARGET_SSE2"
20571 "divpd\t{%2, %0|%0, %2}"
20572 [(set_attr "type" "ssediv")
20573 (set_attr "mode" "V2DF")])
20574
20575(define_insn "vmdivv2df3"
20576 [(set (match_operand:V2DF 0 "register_operand" "=x")
20577 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
20578 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20579 (match_dup 1)
20580 (const_int 1)))]
20581 "TARGET_SSE2"
20582 "divsd\t{%2, %0|%0, %2}"
20583 [(set_attr "type" "ssediv")
20584 (set_attr "mode" "DF")])
20585
20586;; SSE min/max
20587
20588(define_insn "smaxv2df3"
20589 [(set (match_operand:V2DF 0 "register_operand" "=x")
20590 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
20591 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20592 "TARGET_SSE2"
20593 "maxpd\t{%2, %0|%0, %2}"
20594 [(set_attr "type" "sseadd")
20595 (set_attr "mode" "V2DF")])
20596
20597(define_insn "vmsmaxv2df3"
20598 [(set (match_operand:V2DF 0 "register_operand" "=x")
20599 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
20600 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20601 (match_dup 1)
20602 (const_int 1)))]
20603 "TARGET_SSE2"
20604 "maxsd\t{%2, %0|%0, %2}"
20605 [(set_attr "type" "sseadd")
20606 (set_attr "mode" "DF")])
20607
20608(define_insn "sminv2df3"
20609 [(set (match_operand:V2DF 0 "register_operand" "=x")
20610 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
20611 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20612 "TARGET_SSE2"
20613 "minpd\t{%2, %0|%0, %2}"
20614 [(set_attr "type" "sseadd")
20615 (set_attr "mode" "V2DF")])
20616
20617(define_insn "vmsminv2df3"
20618 [(set (match_operand:V2DF 0 "register_operand" "=x")
20619 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
20620 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20621 (match_dup 1)
20622 (const_int 1)))]
20623 "TARGET_SSE2"
20624 "minsd\t{%2, %0|%0, %2}"
20625 [(set_attr "type" "sseadd")
20626 (set_attr "mode" "DF")])
20627;; SSE2 square root. There doesn't appear to be an extension for the
20628;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
20629
20630(define_insn "sqrtv2df2"
20631 [(set (match_operand:V2DF 0 "register_operand" "=x")
20632 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
20633 "TARGET_SSE2"
20634 "sqrtpd\t{%1, %0|%0, %1}"
20635 [(set_attr "type" "sse")
20636 (set_attr "mode" "V2DF")])
20637
20638(define_insn "vmsqrtv2df2"
20639 [(set (match_operand:V2DF 0 "register_operand" "=x")
20640 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
20641 (match_operand:V2DF 2 "register_operand" "0")
20642 (const_int 1)))]
20643 "TARGET_SSE2"
20644 "sqrtsd\t{%1, %0|%0, %1}"
20645 [(set_attr "type" "sse")
20646 (set_attr "mode" "SF")])
20647
20648;; SSE mask-generating compares
20649
20650(define_insn "maskcmpv2df3"
20651 [(set (match_operand:V2DI 0 "register_operand" "=x")
20652 (match_operator:V2DI 3 "sse_comparison_operator"
20653 [(match_operand:V2DF 1 "register_operand" "0")
20654 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
20655 "TARGET_SSE2"
20656 "cmp%D3pd\t{%2, %0|%0, %2}"
20657 [(set_attr "type" "ssecmp")
20658 (set_attr "mode" "V2DF")])
20659
20660(define_insn "maskncmpv2df3"
20661 [(set (match_operand:V2DI 0 "register_operand" "=x")
20662 (not:V2DI
20663 (match_operator:V2DI 3 "sse_comparison_operator"
20664 [(match_operand:V2DF 1 "register_operand" "0")
20665 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
20666 "TARGET_SSE2"
20667{
20668 if (GET_CODE (operands[3]) == UNORDERED)
20669 return "cmpordps\t{%2, %0|%0, %2}";
20670 else
20671 return "cmpn%D3pd\t{%2, %0|%0, %2}";
20672}
20673 [(set_attr "type" "ssecmp")
20674 (set_attr "mode" "V2DF")])
20675
20676(define_insn "vmmaskcmpv2df3"
20677 [(set (match_operand:V2DI 0 "register_operand" "=x")
20678 (vec_merge:V2DI
20679 (match_operator:V2DI 3 "sse_comparison_operator"
20680 [(match_operand:V2DF 1 "register_operand" "0")
20681 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
20682 (subreg:V2DI (match_dup 1) 0)
20683 (const_int 1)))]
20684 "TARGET_SSE2"
20685 "cmp%D3sd\t{%2, %0|%0, %2}"
20686 [(set_attr "type" "ssecmp")
20687 (set_attr "mode" "DF")])
20688
20689(define_insn "vmmaskncmpv2df3"
20690 [(set (match_operand:V2DI 0 "register_operand" "=x")
20691 (vec_merge:V2DI
20692 (not:V2DI
20693 (match_operator:V2DI 3 "sse_comparison_operator"
20694 [(match_operand:V2DF 1 "register_operand" "0")
20695 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
20696 (subreg:V2DI (match_dup 1) 0)
20697 (const_int 1)))]
20698 "TARGET_SSE2"
20699{
20700 if (GET_CODE (operands[3]) == UNORDERED)
20701 return "cmpordsd\t{%2, %0|%0, %2}";
20702 else
20703 return "cmpn%D3sd\t{%2, %0|%0, %2}";
20704}
20705 [(set_attr "type" "ssecmp")
20706 (set_attr "mode" "DF")])
20707
20708(define_insn "sse2_comi"
20709 [(set (reg:CCFP 17)
20710 (compare:CCFP (vec_select:DF
20711 (match_operand:V2DF 0 "register_operand" "x")
20712 (parallel [(const_int 0)]))
20713 (vec_select:DF
20714 (match_operand:V2DF 1 "register_operand" "x")
20715 (parallel [(const_int 0)]))))]
20716 "TARGET_SSE2"
20717 "comisd\t{%1, %0|%0, %1}"
20718 [(set_attr "type" "ssecmp")
20719 (set_attr "mode" "DF")])
20720
20721(define_insn "sse2_ucomi"
20722 [(set (reg:CCFPU 17)
20723 (compare:CCFPU (vec_select:DF
20724 (match_operand:V2DF 0 "register_operand" "x")
20725 (parallel [(const_int 0)]))
20726 (vec_select:DF
20727 (match_operand:V2DF 1 "register_operand" "x")
20728 (parallel [(const_int 0)]))))]
20729 "TARGET_SSE2"
20730 "ucomisd\t{%1, %0|%0, %1}"
20731 [(set_attr "type" "ssecmp")
20732 (set_attr "mode" "DF")])
20733
20734;; SSE Strange Moves.
20735
20736(define_insn "sse2_movmskpd"
20737 [(set (match_operand:SI 0 "register_operand" "=r")
20738 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
20739 UNSPEC_MOVMSK))]
20740 "TARGET_SSE2"
20741 "movmskpd\t{%1, %0|%0, %1}"
20742 [(set_attr "type" "ssecvt")
20743 (set_attr "mode" "V2DF")])
20744
20745(define_insn "sse2_pmovmskb"
20746 [(set (match_operand:SI 0 "register_operand" "=r")
20747 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
20748 UNSPEC_MOVMSK))]
20749 "TARGET_SSE2"
20750 "pmovmskb\t{%1, %0|%0, %1}"
20751 [(set_attr "type" "ssecvt")
20752 (set_attr "mode" "V2DF")])
20753
20754(define_insn "sse2_maskmovdqu"
20755 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
20756 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
20757 (match_operand:V16QI 2 "register_operand" "x")]
20758 UNSPEC_MASKMOV))]
20759 "TARGET_SSE2"
20760 ;; @@@ check ordering of operands in intel/nonintel syntax
20761 "maskmovdqu\t{%2, %1|%1, %2}"
20762 [(set_attr "type" "ssecvt")
20763 (set_attr "mode" "TI")])
20764
20765(define_insn "sse2_maskmovdqu_rex64"
20766 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
20767 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
20768 (match_operand:V16QI 2 "register_operand" "x")]
20769 UNSPEC_MASKMOV))]
20770 "TARGET_SSE2"
20771 ;; @@@ check ordering of operands in intel/nonintel syntax
20772 "maskmovdqu\t{%2, %1|%1, %2}"
20773 [(set_attr "type" "ssecvt")
20774 (set_attr "mode" "TI")])
20775
20776(define_insn "sse2_movntv2df"
20777 [(set (match_operand:V2DF 0 "memory_operand" "=m")
20778 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
20779 UNSPEC_MOVNT))]
20780 "TARGET_SSE2"
20781 "movntpd\t{%1, %0|%0, %1}"
20782 [(set_attr "type" "ssecvt")
20783 (set_attr "mode" "V2DF")])
20784
20785(define_insn "sse2_movntv2di"
20786 [(set (match_operand:V2DI 0 "memory_operand" "=m")
20787 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
20788 UNSPEC_MOVNT))]
20789 "TARGET_SSE2"
20790 "movntdq\t{%1, %0|%0, %1}"
20791 [(set_attr "type" "ssecvt")
20792 (set_attr "mode" "TI")])
20793
20794(define_insn "sse2_movntsi"
20795 [(set (match_operand:SI 0 "memory_operand" "=m")
20796 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
20797 UNSPEC_MOVNT))]
20798 "TARGET_SSE2"
20799 "movnti\t{%1, %0|%0, %1}"
20800 [(set_attr "type" "ssecvt")
20801 (set_attr "mode" "V2DF")])
20802
20803;; SSE <-> integer/MMX conversions
20804
20805;; Conversions between SI and SF
20806
20807(define_insn "cvtdq2ps"
20808 [(set (match_operand:V4SF 0 "register_operand" "=x")
20809 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
20810 "TARGET_SSE2"
20811 "cvtdq2ps\t{%1, %0|%0, %1}"
20812 [(set_attr "type" "ssecvt")
20813 (set_attr "mode" "V2DF")])
20814
20815(define_insn "cvtps2dq"
20816 [(set (match_operand:V4SI 0 "register_operand" "=x")
20817 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
20818 "TARGET_SSE2"
20819 "cvtps2dq\t{%1, %0|%0, %1}"
20820 [(set_attr "type" "ssecvt")
20821 (set_attr "mode" "TI")])
20822
20823(define_insn "cvttps2dq"
20824 [(set (match_operand:V4SI 0 "register_operand" "=x")
20825 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20826 UNSPEC_FIX))]
20827 "TARGET_SSE2"
20828 "cvttps2dq\t{%1, %0|%0, %1}"
20829 [(set_attr "type" "ssecvt")
20830 (set_attr "mode" "TI")])
20831
20832;; Conversions between SI and DF
20833
20834(define_insn "cvtdq2pd"
20835 [(set (match_operand:V2DF 0 "register_operand" "=x")
20836 (float:V2DF (vec_select:V2SI
20837 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
20838 (parallel
20839 [(const_int 0)
20840 (const_int 1)]))))]
20841 "TARGET_SSE2"
20842 "cvtdq2pd\t{%1, %0|%0, %1}"
20843 [(set_attr "type" "ssecvt")
20844 (set_attr "mode" "V2DF")])
20845
20846(define_insn "cvtpd2dq"
20847 [(set (match_operand:V4SI 0 "register_operand" "=x")
20848 (vec_concat:V4SI
20849 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
20850 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
20851 "TARGET_SSE2"
20852 "cvtpd2dq\t{%1, %0|%0, %1}"
20853 [(set_attr "type" "ssecvt")
20854 (set_attr "mode" "TI")])
20855
20856(define_insn "cvttpd2dq"
20857 [(set (match_operand:V4SI 0 "register_operand" "=x")
20858 (vec_concat:V4SI
20859 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
20860 UNSPEC_FIX)
20861 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
20862 "TARGET_SSE2"
20863 "cvttpd2dq\t{%1, %0|%0, %1}"
20864 [(set_attr "type" "ssecvt")
20865 (set_attr "mode" "TI")])
20866
20867(define_insn "cvtpd2pi"
20868 [(set (match_operand:V2SI 0 "register_operand" "=y")
20869 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
20870 "TARGET_SSE2"
20871 "cvtpd2pi\t{%1, %0|%0, %1}"
20872 [(set_attr "type" "ssecvt")
20873 (set_attr "mode" "TI")])
20874
20875(define_insn "cvttpd2pi"
20876 [(set (match_operand:V2SI 0 "register_operand" "=y")
20877 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
20878 UNSPEC_FIX))]
20879 "TARGET_SSE2"
20880 "cvttpd2pi\t{%1, %0|%0, %1}"
20881 [(set_attr "type" "ssecvt")
20882 (set_attr "mode" "TI")])
20883
20884(define_insn "cvtpi2pd"
20885 [(set (match_operand:V2DF 0 "register_operand" "=x")
20886 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
20887 "TARGET_SSE2"
20888 "cvtpi2pd\t{%1, %0|%0, %1}"
20889 [(set_attr "type" "ssecvt")
20890 (set_attr "mode" "TI")])
20891
20892;; Conversions between SI and DF
20893
20894(define_insn "cvtsd2si"
20895 [(set (match_operand:SI 0 "register_operand" "=r")
20896 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "xm")
20897 (parallel [(const_int 0)]))))]
20898 "TARGET_SSE2"
20899 "cvtsd2si\t{%1, %0|%0, %1}"
20900 [(set_attr "type" "ssecvt")
20901 (set_attr "mode" "SI")])
20902
20903(define_insn "cvtsd2siq"
20904 [(set (match_operand:DI 0 "register_operand" "=r")
20905 (fix:DI (vec_select:DF (match_operand:V2DF 1 "register_operand" "xm")
20906 (parallel [(const_int 0)]))))]
20907 "TARGET_SSE2 && TARGET_64BIT"
20908 "cvtsd2siq\t{%1, %0|%0, %1}"
20909 [(set_attr "type" "ssecvt")
20910 (set_attr "mode" "SI")])
20911
20912(define_insn "cvttsd2si"
20913 [(set (match_operand:SI 0 "register_operand" "=r")
20914 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "xm")
20915 (parallel [(const_int 0)]))] UNSPEC_FIX))]
20916 "TARGET_SSE2"
20917 "cvttsd2si\t{%1, %0|%0, %1}"
20918 [(set_attr "type" "ssecvt")
20919 (set_attr "mode" "SI")])
20920
20921(define_insn "cvttsd2siq"
20922 [(set (match_operand:DI 0 "register_operand" "=r,r")
20923 (unspec:DI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
20924 (parallel [(const_int 0)]))] UNSPEC_FIX))]
20925 "TARGET_SSE2 && TARGET_64BIT"
20926 "cvttsd2siq\t{%1, %0|%0, %1}"
20927 [(set_attr "type" "ssecvt")
20928 (set_attr "mode" "DI")
20929 (set_attr "athlon_decode" "vector,vector")])
20930
20931(define_insn "cvtsi2sd"
20932 [(set (match_operand:V2DF 0 "register_operand" "=x")
20933 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
20934 (vec_duplicate:V2DF
20935 (float:DF
20936 (match_operand:SI 2 "nonimmediate_operand" "rm")))
20937 (const_int 2)))]
20938 "TARGET_SSE2"
20939 "cvtsi2sd\t{%2, %0|%0, %2}"
20940 [(set_attr "type" "ssecvt")
20941 (set_attr "mode" "DF")])
20942
20943(define_insn "cvtsi2sdq"
20944 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
20945 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
20946 (vec_duplicate:V2DF
20947 (float:DF
20948 (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
20949 (const_int 2)))]
20950 "TARGET_SSE2 && TARGET_64BIT"
20951 "cvtsi2sdq\t{%2, %0|%0, %2}"
20952 [(set_attr "type" "ssecvt")
20953 (set_attr "mode" "DF")
20954 (set_attr "athlon_decode" "vector,direct")])
20955
20956;; Conversions between SF and DF
20957
20958(define_insn "cvtsd2ss"
20959 [(set (match_operand:V4SF 0 "register_operand" "=x")
20960 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
20961 (vec_duplicate:V4SF
20962 (float_truncate:V2SF
20963 (match_operand:V2DF 2 "register_operand" "xm")))
20964 (const_int 14)))]
20965 "TARGET_SSE2"
20966 "cvtsd2ss\t{%2, %0|%0, %2}"
20967 [(set_attr "type" "ssecvt")
20968 (set_attr "mode" "SF")])
20969
20970(define_insn "cvtss2sd"
20971 [(set (match_operand:V2DF 0 "register_operand" "=x")
20972 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
20973 (float_extend:V2DF
20974 (vec_select:V2SF
20975 (match_operand:V4SF 2 "register_operand" "xm")
20976 (parallel [(const_int 0)
20977 (const_int 1)])))
20978 (const_int 2)))]
20979 "TARGET_SSE2"
20980 "cvtss2sd\t{%2, %0|%0, %2}"
20981 [(set_attr "type" "ssecvt")
20982 (set_attr "mode" "DF")])
20983
20984(define_insn "cvtpd2ps"
20985 [(set (match_operand:V4SF 0 "register_operand" "=x")
20986 (subreg:V4SF
20987 (vec_concat:V4SI
20988 (subreg:V2SI (float_truncate:V2SF
20989 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
20990 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
20991 "TARGET_SSE2"
20992 "cvtpd2ps\t{%1, %0|%0, %1}"
20993 [(set_attr "type" "ssecvt")
20994 (set_attr "mode" "V4SF")])
20995
20996(define_insn "cvtps2pd"
20997 [(set (match_operand:V2DF 0 "register_operand" "=x")
20998 (float_extend:V2DF
20999 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
21000 (parallel [(const_int 0)
21001 (const_int 1)]))))]
21002 "TARGET_SSE2"
21003 "cvtps2pd\t{%1, %0|%0, %1}"
21004 [(set_attr "type" "ssecvt")
21005 (set_attr "mode" "V2DF")])
21006
21007;; SSE2 variants of MMX insns
21008
21009;; MMX arithmetic
21010
21011(define_insn "addv16qi3"
21012 [(set (match_operand:V16QI 0 "register_operand" "=x")
21013 (plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
21014 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21015 "TARGET_SSE2"
21016 "paddb\t{%2, %0|%0, %2}"
21017 [(set_attr "type" "sseiadd")
21018 (set_attr "mode" "TI")])
21019
21020(define_insn "addv8hi3"
21021 [(set (match_operand:V8HI 0 "register_operand" "=x")
21022 (plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
21023 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21024 "TARGET_SSE2"
21025 "paddw\t{%2, %0|%0, %2}"
21026 [(set_attr "type" "sseiadd")
21027 (set_attr "mode" "TI")])
21028
21029(define_insn "addv4si3"
21030 [(set (match_operand:V4SI 0 "register_operand" "=x")
21031 (plus:V4SI (match_operand:V4SI 1 "register_operand" "%0")
21032 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
21033 "TARGET_SSE2"
21034 "paddd\t{%2, %0|%0, %2}"
21035 [(set_attr "type" "sseiadd")
21036 (set_attr "mode" "TI")])
21037
21038(define_insn "addv2di3"
21039 [(set (match_operand:V2DI 0 "register_operand" "=x")
21040 (plus:V2DI (match_operand:V2DI 1 "register_operand" "%0")
21041 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21042 "TARGET_SSE2"
21043 "paddq\t{%2, %0|%0, %2}"
21044 [(set_attr "type" "sseiadd")
21045 (set_attr "mode" "TI")])
21046
21047(define_insn "ssaddv16qi3"
21048 [(set (match_operand:V16QI 0 "register_operand" "=x")
21049 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
21050 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21051 "TARGET_SSE2"
21052 "paddsb\t{%2, %0|%0, %2}"
21053 [(set_attr "type" "sseiadd")
21054 (set_attr "mode" "TI")])
21055
21056(define_insn "ssaddv8hi3"
21057 [(set (match_operand:V8HI 0 "register_operand" "=x")
21058 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
21059 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21060 "TARGET_SSE2"
21061 "paddsw\t{%2, %0|%0, %2}"
21062 [(set_attr "type" "sseiadd")
21063 (set_attr "mode" "TI")])
21064
21065(define_insn "usaddv16qi3"
21066 [(set (match_operand:V16QI 0 "register_operand" "=x")
21067 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
21068 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21069 "TARGET_SSE2"
21070 "paddusb\t{%2, %0|%0, %2}"
21071 [(set_attr "type" "sseiadd")
21072 (set_attr "mode" "TI")])
21073
21074(define_insn "usaddv8hi3"
21075 [(set (match_operand:V8HI 0 "register_operand" "=x")
21076 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
21077 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21078 "TARGET_SSE2"
21079 "paddusw\t{%2, %0|%0, %2}"
21080 [(set_attr "type" "sseiadd")
21081 (set_attr "mode" "TI")])
21082
21083(define_insn "subv16qi3"
21084 [(set (match_operand:V16QI 0 "register_operand" "=x")
21085 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21086 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21087 "TARGET_SSE2"
21088 "psubb\t{%2, %0|%0, %2}"
21089 [(set_attr "type" "sseiadd")
21090 (set_attr "mode" "TI")])
21091
21092(define_insn "subv8hi3"
21093 [(set (match_operand:V8HI 0 "register_operand" "=x")
21094 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21095 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21096 "TARGET_SSE2"
21097 "psubw\t{%2, %0|%0, %2}"
21098 [(set_attr "type" "sseiadd")
21099 (set_attr "mode" "TI")])
21100
21101(define_insn "subv4si3"
21102 [(set (match_operand:V4SI 0 "register_operand" "=x")
21103 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
21104 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
21105 "TARGET_SSE2"
21106 "psubd\t{%2, %0|%0, %2}"
21107 [(set_attr "type" "sseiadd")
21108 (set_attr "mode" "TI")])
21109
21110(define_insn "subv2di3"
21111 [(set (match_operand:V2DI 0 "register_operand" "=x")
21112 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
21113 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21114 "TARGET_SSE2"
21115 "psubq\t{%2, %0|%0, %2}"
21116 [(set_attr "type" "sseiadd")
21117 (set_attr "mode" "TI")])
21118
21119(define_insn "sssubv16qi3"
21120 [(set (match_operand:V16QI 0 "register_operand" "=x")
21121 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21122 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21123 "TARGET_SSE2"
21124 "psubsb\t{%2, %0|%0, %2}"
21125 [(set_attr "type" "sseiadd")
21126 (set_attr "mode" "TI")])
21127
21128(define_insn "sssubv8hi3"
21129 [(set (match_operand:V8HI 0 "register_operand" "=x")
21130 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21131 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21132 "TARGET_SSE2"
21133 "psubsw\t{%2, %0|%0, %2}"
21134 [(set_attr "type" "sseiadd")
21135 (set_attr "mode" "TI")])
21136
21137(define_insn "ussubv16qi3"
21138 [(set (match_operand:V16QI 0 "register_operand" "=x")
21139 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21140 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21141 "TARGET_SSE2"
21142 "psubusb\t{%2, %0|%0, %2}"
21143 [(set_attr "type" "sseiadd")
21144 (set_attr "mode" "TI")])
21145
21146(define_insn "ussubv8hi3"
21147 [(set (match_operand:V8HI 0 "register_operand" "=x")
21148 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21149 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21150 "TARGET_SSE2"
21151 "psubusw\t{%2, %0|%0, %2}"
21152 [(set_attr "type" "sseiadd")
21153 (set_attr "mode" "TI")])
21154
21155(define_insn "mulv8hi3"
21156 [(set (match_operand:V8HI 0 "register_operand" "=x")
21157 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
21158 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21159 "TARGET_SSE2"
21160 "pmullw\t{%2, %0|%0, %2}"
21161 [(set_attr "type" "sseimul")
21162 (set_attr "mode" "TI")])
21163
21164(define_insn "smulv8hi3_highpart"
21165 [(set (match_operand:V8HI 0 "register_operand" "=x")
21166 (truncate:V8HI
21167 (lshiftrt:V8SI
21168 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
21169 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
21170 (const_int 16))))]
21171 "TARGET_SSE2"
21172 "pmulhw\t{%2, %0|%0, %2}"
21173 [(set_attr "type" "sseimul")
21174 (set_attr "mode" "TI")])
21175
21176(define_insn "umulv8hi3_highpart"
21177 [(set (match_operand:V8HI 0 "register_operand" "=x")
21178 (truncate:V8HI
21179 (lshiftrt:V8SI
21180 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
21181 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
21182 (const_int 16))))]
21183 "TARGET_SSE2"
21184 "pmulhuw\t{%2, %0|%0, %2}"
21185 [(set_attr "type" "sseimul")
21186 (set_attr "mode" "TI")])
21187
21188(define_insn "sse2_umulsidi3"
21189 [(set (match_operand:DI 0 "register_operand" "=y")
21190 (mult:DI (zero_extend:DI (vec_select:SI
21191 (match_operand:V2SI 1 "register_operand" "0")
21192 (parallel [(const_int 0)])))
21193 (zero_extend:DI (vec_select:SI
21194 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
21195 (parallel [(const_int 0)])))))]
21196 "TARGET_SSE2"
21197 "pmuludq\t{%2, %0|%0, %2}"
21198 [(set_attr "type" "sseimul")
21199 (set_attr "mode" "TI")])
21200
21201(define_insn "sse2_umulv2siv2di3"
21202 [(set (match_operand:V2DI 0 "register_operand" "=x")
21203 (mult:V2DI (zero_extend:V2DI
21204 (vec_select:V2SI
21205 (match_operand:V4SI 1 "register_operand" "0")
21206 (parallel [(const_int 0) (const_int 2)])))
21207 (zero_extend:V2DI
21208 (vec_select:V2SI
21209 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
21210 (parallel [(const_int 0) (const_int 2)])))))]
21211 "TARGET_SSE2"
21212 "pmuludq\t{%2, %0|%0, %2}"
21213 [(set_attr "type" "sseimul")
21214 (set_attr "mode" "TI")])
21215
21216(define_insn "sse2_pmaddwd"
21217 [(set (match_operand:V4SI 0 "register_operand" "=x")
21218 (plus:V4SI
21219 (mult:V4SI
21220 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
21221 (parallel [(const_int 0)
21222 (const_int 2)
21223 (const_int 4)
21224 (const_int 6)])))
21225 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
21226 (parallel [(const_int 0)
21227 (const_int 2)
21228 (const_int 4)
21229 (const_int 6)]))))
21230 (mult:V4SI
21231 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
21232 (parallel [(const_int 1)
21233 (const_int 3)
21234 (const_int 5)
21235 (const_int 7)])))
21236 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
21237 (parallel [(const_int 1)
21238 (const_int 3)
21239 (const_int 5)
21240 (const_int 7)]))))))]
21241 "TARGET_SSE2"
21242 "pmaddwd\t{%2, %0|%0, %2}"
21243 [(set_attr "type" "sseiadd")
21244 (set_attr "mode" "TI")])
21245
21246;; Same as pxor, but don't show input operands so that we don't think
21247;; they are live.
21248(define_insn "sse2_clrti"
21249 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
21250 "TARGET_SSE2"
21251 "pxor\t{%0, %0|%0, %0}"
21252 [(set_attr "type" "sseiadd")
21253 (set_attr "memory" "none")
21254 (set_attr "mode" "TI")])
21255
21256;; MMX unsigned averages/sum of absolute differences
21257
21258(define_insn "sse2_uavgv16qi3"
21259 [(set (match_operand:V16QI 0 "register_operand" "=x")
21260 (ashiftrt:V16QI
21261 (plus:V16QI (plus:V16QI
21262 (match_operand:V16QI 1 "register_operand" "0")
21263 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
21264 (const_vector:V16QI [(const_int 1) (const_int 1)
21265 (const_int 1) (const_int 1)
21266 (const_int 1) (const_int 1)
21267 (const_int 1) (const_int 1)
21268 (const_int 1) (const_int 1)
21269 (const_int 1) (const_int 1)
21270 (const_int 1) (const_int 1)
21271 (const_int 1) (const_int 1)]))
21272 (const_int 1)))]
21273 "TARGET_SSE2"
21274 "pavgb\t{%2, %0|%0, %2}"
21275 [(set_attr "type" "sseiadd")
21276 (set_attr "mode" "TI")])
21277
21278(define_insn "sse2_uavgv8hi3"
21279 [(set (match_operand:V8HI 0 "register_operand" "=x")
21280 (ashiftrt:V8HI
21281 (plus:V8HI (plus:V8HI
21282 (match_operand:V8HI 1 "register_operand" "0")
21283 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
21284 (const_vector:V8HI [(const_int 1) (const_int 1)
21285 (const_int 1) (const_int 1)
21286 (const_int 1) (const_int 1)
21287 (const_int 1) (const_int 1)]))
21288 (const_int 1)))]
21289 "TARGET_SSE2"
21290 "pavgw\t{%2, %0|%0, %2}"
21291 [(set_attr "type" "sseiadd")
21292 (set_attr "mode" "TI")])
21293
21294;; @@@ this isn't the right representation.
21295(define_insn "sse2_psadbw"
21296 [(set (match_operand:V2DI 0 "register_operand" "=x")
21297 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
21298 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
21299 UNSPEC_PSADBW))]
21300 "TARGET_SSE2"
21301 "psadbw\t{%2, %0|%0, %2}"
21302 [(set_attr "type" "sseiadd")
21303 (set_attr "mode" "TI")])
21304
21305
21306;; MMX insert/extract/shuffle
21307
21308(define_insn "sse2_pinsrw"
21309 [(set (match_operand:V8HI 0 "register_operand" "=x")
21310 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
21311 (vec_duplicate:V8HI
21312 (truncate:HI
21313 (match_operand:SI 2 "nonimmediate_operand" "rm")))
21314 (match_operand:SI 3 "immediate_operand" "i")))]
21315 "TARGET_SSE2"
21316 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
21317 [(set_attr "type" "ssecvt")
21318 (set_attr "mode" "TI")])
21319
21320(define_insn "sse2_pextrw"
21321 [(set (match_operand:SI 0 "register_operand" "=r")
21322 (zero_extend:SI
21323 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
21324 (parallel
21325 [(match_operand:SI 2 "immediate_operand" "i")]))))]
21326 "TARGET_SSE2"
21327 "pextrw\t{%2, %1, %0|%0, %1, %2}"
21328 [(set_attr "type" "ssecvt")
21329 (set_attr "mode" "TI")])
21330
21331(define_insn "sse2_pshufd"
21332 [(set (match_operand:V4SI 0 "register_operand" "=x")
21333 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
21334 (match_operand:SI 2 "immediate_operand" "i")]
21335 UNSPEC_SHUFFLE))]
21336 "TARGET_SSE2"
21337 "pshufd\t{%2, %1, %0|%0, %1, %2}"
21338 [(set_attr "type" "ssecvt")
21339 (set_attr "mode" "TI")])
21340
21341(define_insn "sse2_pshuflw"
21342 [(set (match_operand:V8HI 0 "register_operand" "=x")
21343 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
21344 (match_operand:SI 2 "immediate_operand" "i")]
21345 UNSPEC_PSHUFLW))]
21346 "TARGET_SSE2"
21347 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
21348 [(set_attr "type" "ssecvt")
21349 (set_attr "mode" "TI")])
21350
21351(define_insn "sse2_pshufhw"
21352 [(set (match_operand:V8HI 0 "register_operand" "=x")
21353 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
21354 (match_operand:SI 2 "immediate_operand" "i")]
21355 UNSPEC_PSHUFHW))]
21356 "TARGET_SSE2"
21357 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
21358 [(set_attr "type" "ssecvt")
21359 (set_attr "mode" "TI")])
21360
21361;; MMX mask-generating comparisons
21362
21363(define_insn "eqv16qi3"
21364 [(set (match_operand:V16QI 0 "register_operand" "=x")
21365 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
21366 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21367 "TARGET_SSE2"
21368 "pcmpeqb\t{%2, %0|%0, %2}"
21369 [(set_attr "type" "ssecmp")
21370 (set_attr "mode" "TI")])
21371
21372(define_insn "eqv8hi3"
21373 [(set (match_operand:V8HI 0 "register_operand" "=x")
21374 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
21375 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21376 "TARGET_SSE2"
21377 "pcmpeqw\t{%2, %0|%0, %2}"
21378 [(set_attr "type" "ssecmp")
21379 (set_attr "mode" "TI")])
21380
21381(define_insn "eqv4si3"
21382 [(set (match_operand:V4SI 0 "register_operand" "=x")
21383 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
21384 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
21385 "TARGET_SSE2"
21386 "pcmpeqd\t{%2, %0|%0, %2}"
21387 [(set_attr "type" "ssecmp")
21388 (set_attr "mode" "TI")])
21389
21390(define_insn "gtv16qi3"
21391 [(set (match_operand:V16QI 0 "register_operand" "=x")
21392 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
21393 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21394 "TARGET_SSE2"
21395 "pcmpgtb\t{%2, %0|%0, %2}"
21396 [(set_attr "type" "ssecmp")
21397 (set_attr "mode" "TI")])
21398
21399(define_insn "gtv8hi3"
21400 [(set (match_operand:V8HI 0 "register_operand" "=x")
21401 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
21402 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21403 "TARGET_SSE2"
21404 "pcmpgtw\t{%2, %0|%0, %2}"
21405 [(set_attr "type" "ssecmp")
21406 (set_attr "mode" "TI")])
21407
21408(define_insn "gtv4si3"
21409 [(set (match_operand:V4SI 0 "register_operand" "=x")
21410 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21411 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
21412 "TARGET_SSE2"
21413 "pcmpgtd\t{%2, %0|%0, %2}"
21414 [(set_attr "type" "ssecmp")
21415 (set_attr "mode" "TI")])
21416
21417
21418;; MMX max/min insns
21419
21420(define_insn "umaxv16qi3"
21421 [(set (match_operand:V16QI 0 "register_operand" "=x")
21422 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
21423 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21424 "TARGET_SSE2"
21425 "pmaxub\t{%2, %0|%0, %2}"
21426 [(set_attr "type" "sseiadd")
21427 (set_attr "mode" "TI")])
21428
21429(define_insn "smaxv8hi3"
21430 [(set (match_operand:V8HI 0 "register_operand" "=x")
21431 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
21432 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21433 "TARGET_SSE2"
21434 "pmaxsw\t{%2, %0|%0, %2}"
21435 [(set_attr "type" "sseiadd")
21436 (set_attr "mode" "TI")])
21437
21438(define_insn "uminv16qi3"
21439 [(set (match_operand:V16QI 0 "register_operand" "=x")
21440 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
21441 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21442 "TARGET_SSE2"
21443 "pminub\t{%2, %0|%0, %2}"
21444 [(set_attr "type" "sseiadd")
21445 (set_attr "mode" "TI")])
21446
21447(define_insn "sminv8hi3"
21448 [(set (match_operand:V8HI 0 "register_operand" "=x")
21449 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
21450 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21451 "TARGET_SSE2"
21452 "pminsw\t{%2, %0|%0, %2}"
21453 [(set_attr "type" "sseiadd")
21454 (set_attr "mode" "TI")])
21455
21456
21457;; MMX shifts
21458
21459(define_insn "ashrv8hi3"
21460 [(set (match_operand:V8HI 0 "register_operand" "=x")
21461 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
21462 (match_operand:TI 2 "nonmemory_operand" "xi")))]
21463 "TARGET_SSE2"
21464 "psraw\t{%2, %0|%0, %2}"
21465 [(set_attr "type" "sseishft")
21466 (set_attr "mode" "TI")])
21467
21468(define_insn "ashrv4si3"
21469 [(set (match_operand:V4SI 0 "register_operand" "=x")
21470 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21471 (match_operand:TI 2 "nonmemory_operand" "xi")))]
21472 "TARGET_SSE2"
21473 "psrad\t{%2, %0|%0, %2}"
21474 [(set_attr "type" "sseishft")
21475 (set_attr "mode" "TI")])
21476
21477(define_insn "lshrv8hi3"
21478 [(set (match_operand:V8HI 0 "register_operand" "=x")
21479 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
21480 (match_operand:TI 2 "nonmemory_operand" "xi")))]
21481 "TARGET_SSE2"
21482 "psrlw\t{%2, %0|%0, %2}"
21483 [(set_attr "type" "sseishft")
21484 (set_attr "mode" "TI")])
21485
21486(define_insn "lshrv4si3"
21487 [(set (match_operand:V4SI 0 "register_operand" "=x")
21488 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21489 (match_operand:TI 2 "nonmemory_operand" "xi")))]
21490 "TARGET_SSE2"
21491 "psrld\t{%2, %0|%0, %2}"
21492 [(set_attr "type" "sseishft")
21493 (set_attr "mode" "TI")])
21494
21495(define_insn "lshrv2di3"
21496 [(set (match_operand:V2DI 0 "register_operand" "=x")
21497 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
21498 (match_operand:TI 2 "nonmemory_operand" "xi")))]
21499 "TARGET_SSE2"
21500 "psrlq\t{%2, %0|%0, %2}"
21501 [(set_attr "type" "sseishft")
21502 (set_attr "mode" "TI")])
21503
21504(define_insn "ashlv8hi3"
21505 [(set (match_operand:V8HI 0 "register_operand" "=x")
21506 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
21507 (match_operand:TI 2 "nonmemory_operand" "xi")))]
21508 "TARGET_SSE2"
21509 "psllw\t{%2, %0|%0, %2}"
21510 [(set_attr "type" "sseishft")
21511 (set_attr "mode" "TI")])
21512
21513(define_insn "ashlv4si3"
21514 [(set (match_operand:V4SI 0 "register_operand" "=x")
21515 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
21516 (match_operand:TI 2 "nonmemory_operand" "xi")))]
21517 "TARGET_SSE2"
21518 "pslld\t{%2, %0|%0, %2}"
21519 [(set_attr "type" "sseishft")
21520 (set_attr "mode" "TI")])
21521
21522(define_insn "ashlv2di3"
21523 [(set (match_operand:V2DI 0 "register_operand" "=x")
21524 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
21525 (match_operand:TI 2 "nonmemory_operand" "xi")))]
21526 "TARGET_SSE2"
21527 "psllq\t{%2, %0|%0, %2}"
21528 [(set_attr "type" "sseishft")
21529 (set_attr "mode" "TI")])
21530
21531(define_insn "ashrv8hi3_ti"
21532 [(set (match_operand:V8HI 0 "register_operand" "=x")
21533 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
21534 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21535 "TARGET_SSE2"
21536 "psraw\t{%2, %0|%0, %2}"
21537 [(set_attr "type" "sseishft")
21538 (set_attr "mode" "TI")])
21539
21540(define_insn "ashrv4si3_ti"
21541 [(set (match_operand:V4SI 0 "register_operand" "=x")
21542 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21543 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21544 "TARGET_SSE2"
21545 "psrad\t{%2, %0|%0, %2}"
21546 [(set_attr "type" "sseishft")
21547 (set_attr "mode" "TI")])
21548
21549(define_insn "lshrv8hi3_ti"
21550 [(set (match_operand:V8HI 0 "register_operand" "=x")
21551 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
21552 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21553 "TARGET_SSE2"
21554 "psrlw\t{%2, %0|%0, %2}"
21555 [(set_attr "type" "sseishft")
21556 (set_attr "mode" "TI")])
21557
21558(define_insn "lshrv4si3_ti"
21559 [(set (match_operand:V4SI 0 "register_operand" "=x")
21560 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21561 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21562 "TARGET_SSE2"
21563 "psrld\t{%2, %0|%0, %2}"
21564 [(set_attr "type" "sseishft")
21565 (set_attr "mode" "TI")])
21566
21567(define_insn "lshrv2di3_ti"
21568 [(set (match_operand:V2DI 0 "register_operand" "=x")
21569 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
21570 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21571 "TARGET_SSE2"
21572 "psrlq\t{%2, %0|%0, %2}"
21573 [(set_attr "type" "sseishft")
21574 (set_attr "mode" "TI")])
21575
21576(define_insn "ashlv8hi3_ti"
21577 [(set (match_operand:V8HI 0 "register_operand" "=x")
21578 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
21579 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21580 "TARGET_SSE2"
21581 "psllw\t{%2, %0|%0, %2}"
21582 [(set_attr "type" "sseishft")
21583 (set_attr "mode" "TI")])
21584
21585(define_insn "ashlv4si3_ti"
21586 [(set (match_operand:V4SI 0 "register_operand" "=x")
21587 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
21588 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21589 "TARGET_SSE2"
21590 "pslld\t{%2, %0|%0, %2}"
21591 [(set_attr "type" "sseishft")
21592 (set_attr "mode" "TI")])
21593
21594(define_insn "ashlv2di3_ti"
21595 [(set (match_operand:V2DI 0 "register_operand" "=x")
21596 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
21597 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21598 "TARGET_SSE2"
21599 "psllq\t{%2, %0|%0, %2}"
21600 [(set_attr "type" "sseishft")
21601 (set_attr "mode" "TI")])
21602
21603;; See logical MMX insns for the reason for the unspec. Strictly speaking
21604;; we wouldn't need here it since we never generate TImode arithmetic.
21605
21606;; There has to be some kind of prize for the weirdest new instruction...
21607(define_insn "sse2_ashlti3"
21608 [(set (match_operand:TI 0 "register_operand" "=x")
21609 (unspec:TI
21610 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
21611 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
21612 (const_int 8)))] UNSPEC_NOP))]
21613 "TARGET_SSE2"
21614 "pslldq\t{%2, %0|%0, %2}"
21615 [(set_attr "type" "sseishft")
21616 (set_attr "mode" "TI")])
21617
21618(define_insn "sse2_lshrti3"
21619 [(set (match_operand:TI 0 "register_operand" "=x")
21620 (unspec:TI
21621 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
21622 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
21623 (const_int 8)))] UNSPEC_NOP))]
21624 "TARGET_SSE2"
21625 "psrldq\t{%2, %0|%0, %2}"
21626 [(set_attr "type" "sseishft")
21627 (set_attr "mode" "TI")])
21628
21629;; SSE unpack
21630
21631(define_insn "sse2_unpckhpd"
21632 [(set (match_operand:V2DF 0 "register_operand" "=x")
21633 (vec_concat:V2DF
21634 (vec_select:V2DF (match_operand:V2DF 1 "register_operand" "0")
21635 (parallel [(const_int 1)]))
21636 (vec_select:V2DF (match_operand:V2DF 2 "register_operand" "x")
21637 (parallel [(const_int 0)]))))]
21638 "TARGET_SSE2"
21639 "unpckhpd\t{%2, %0|%0, %2}"
21640 [(set_attr "type" "ssecvt")
21641 (set_attr "mode" "TI")])
21642
21643(define_insn "sse2_unpcklpd"
21644 [(set (match_operand:V2DF 0 "register_operand" "=x")
21645 (vec_concat:V2DF
21646 (vec_select:V2DF (match_operand:V2DF 1 "register_operand" "0")
21647 (parallel [(const_int 0)]))
21648 (vec_select:V2DF (match_operand:V2DF 2 "register_operand" "x")
21649 (parallel [(const_int 1)]))))]
21650 "TARGET_SSE2"
21651 "unpcklpd\t{%2, %0|%0, %2}"
21652 [(set_attr "type" "ssecvt")
21653 (set_attr "mode" "TI")])
21654
21655;; MMX pack/unpack insns.
21656
21657(define_insn "sse2_packsswb"
21658 [(set (match_operand:V16QI 0 "register_operand" "=x")
21659 (vec_concat:V16QI
21660 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
21661 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
21662 "TARGET_SSE2"
21663 "packsswb\t{%2, %0|%0, %2}"
21664 [(set_attr "type" "ssecvt")
21665 (set_attr "mode" "TI")])
21666
21667(define_insn "sse2_packssdw"
21668 [(set (match_operand:V8HI 0 "register_operand" "=x")
21669 (vec_concat:V8HI
21670 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
21671 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
21672 "TARGET_SSE2"
21673 "packssdw\t{%2, %0|%0, %2}"
21674 [(set_attr "type" "ssecvt")
21675 (set_attr "mode" "TI")])
21676
21677(define_insn "sse2_packuswb"
21678 [(set (match_operand:V16QI 0 "register_operand" "=x")
21679 (vec_concat:V16QI
21680 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
21681 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
21682 "TARGET_SSE2"
21683 "packuswb\t{%2, %0|%0, %2}"
21684 [(set_attr "type" "ssecvt")
21685 (set_attr "mode" "TI")])
21686
21687(define_insn "sse2_punpckhbw"
21688 [(set (match_operand:V16QI 0 "register_operand" "=x")
21689 (vec_merge:V16QI
21690 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
21691 (parallel [(const_int 8) (const_int 0)
21692 (const_int 9) (const_int 1)
21693 (const_int 10) (const_int 2)
21694 (const_int 11) (const_int 3)
21695 (const_int 12) (const_int 4)
21696 (const_int 13) (const_int 5)
21697 (const_int 14) (const_int 6)
21698 (const_int 15) (const_int 7)]))
21699 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
21700 (parallel [(const_int 0) (const_int 8)
21701 (const_int 1) (const_int 9)
21702 (const_int 2) (const_int 10)
21703 (const_int 3) (const_int 11)
21704 (const_int 4) (const_int 12)
21705 (const_int 5) (const_int 13)
21706 (const_int 6) (const_int 14)
21707 (const_int 7) (const_int 15)]))
21708 (const_int 21845)))]
21709 "TARGET_SSE2"
21710 "punpckhbw\t{%2, %0|%0, %2}"
21711 [(set_attr "type" "ssecvt")
21712 (set_attr "mode" "TI")])
21713
21714(define_insn "sse2_punpckhwd"
21715 [(set (match_operand:V8HI 0 "register_operand" "=x")
21716 (vec_merge:V8HI
21717 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
21718 (parallel [(const_int 4) (const_int 0)
21719 (const_int 5) (const_int 1)
21720 (const_int 6) (const_int 2)
21721 (const_int 7) (const_int 3)]))
21722 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
21723 (parallel [(const_int 0) (const_int 4)
21724 (const_int 1) (const_int 5)
21725 (const_int 2) (const_int 6)
21726 (const_int 3) (const_int 7)]))
21727 (const_int 85)))]
21728 "TARGET_SSE2"
21729 "punpckhwd\t{%2, %0|%0, %2}"
21730 [(set_attr "type" "ssecvt")
21731 (set_attr "mode" "TI")])
21732
21733(define_insn "sse2_punpckhdq"
21734 [(set (match_operand:V4SI 0 "register_operand" "=x")
21735 (vec_merge:V4SI
21736 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
21737 (parallel [(const_int 2) (const_int 0)
21738 (const_int 3) (const_int 1)]))
21739 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
21740 (parallel [(const_int 0) (const_int 2)
21741 (const_int 1) (const_int 3)]))
21742 (const_int 5)))]
21743 "TARGET_SSE2"
21744 "punpckhdq\t{%2, %0|%0, %2}"
21745 [(set_attr "type" "ssecvt")
21746 (set_attr "mode" "TI")])
21747
21748(define_insn "sse2_punpcklbw"
21749 [(set (match_operand:V16QI 0 "register_operand" "=x")
21750 (vec_merge:V16QI
21751 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
21752 (parallel [(const_int 0) (const_int 8)
21753 (const_int 1) (const_int 9)
21754 (const_int 2) (const_int 10)
21755 (const_int 3) (const_int 11)
21756 (const_int 4) (const_int 12)
21757 (const_int 5) (const_int 13)
21758 (const_int 6) (const_int 14)
21759 (const_int 7) (const_int 15)]))
21760 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
21761 (parallel [(const_int 8) (const_int 0)
21762 (const_int 9) (const_int 1)
21763 (const_int 10) (const_int 2)
21764 (const_int 11) (const_int 3)
21765 (const_int 12) (const_int 4)
21766 (const_int 13) (const_int 5)
21767 (const_int 14) (const_int 6)
21768 (const_int 15) (const_int 7)]))
21769 (const_int 21845)))]
21770 "TARGET_SSE2"
21771 "punpcklbw\t{%2, %0|%0, %2}"
21772 [(set_attr "type" "ssecvt")
21773 (set_attr "mode" "TI")])
21774
21775(define_insn "sse2_punpcklwd"
21776 [(set (match_operand:V8HI 0 "register_operand" "=x")
21777 (vec_merge:V8HI
21778 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
21779 (parallel [(const_int 0) (const_int 4)
21780 (const_int 1) (const_int 5)
21781 (const_int 2) (const_int 6)
21782 (const_int 3) (const_int 7)]))
21783 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
21784 (parallel [(const_int 4) (const_int 0)
21785 (const_int 5) (const_int 1)
21786 (const_int 6) (const_int 2)
21787 (const_int 7) (const_int 3)]))
21788 (const_int 85)))]
21789 "TARGET_SSE2"
21790 "punpcklwd\t{%2, %0|%0, %2}"
21791 [(set_attr "type" "ssecvt")
21792 (set_attr "mode" "TI")])
21793
21794(define_insn "sse2_punpckldq"
21795 [(set (match_operand:V4SI 0 "register_operand" "=x")
21796 (vec_merge:V4SI
21797 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
21798 (parallel [(const_int 0) (const_int 2)
21799 (const_int 1) (const_int 3)]))
21800 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
21801 (parallel [(const_int 2) (const_int 0)
21802 (const_int 3) (const_int 1)]))
21803 (const_int 5)))]
21804 "TARGET_SSE2"
21805 "punpckldq\t{%2, %0|%0, %2}"
21806 [(set_attr "type" "ssecvt")
21807 (set_attr "mode" "TI")])
21808
21809(define_insn "sse2_punpcklqdq"
21810 [(set (match_operand:V2DI 0 "register_operand" "=x")
21811 (vec_merge:V2DI
21812 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
21813 (parallel [(const_int 1)
21814 (const_int 0)]))
21815 (match_operand:V2DI 1 "register_operand" "0")
21816 (const_int 1)))]
21817 "TARGET_SSE2"
21818 "punpcklqdq\t{%2, %0|%0, %2}"
21819 [(set_attr "type" "ssecvt")
21820 (set_attr "mode" "TI")])
21821
21822(define_insn "sse2_punpckhqdq"
21823 [(set (match_operand:V2DI 0 "register_operand" "=x")
21824 (vec_merge:V2DI
21825 (match_operand:V2DI 1 "register_operand" "0")
21826 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
21827 (parallel [(const_int 1)
21828 (const_int 0)]))
21829 (const_int 1)))]
21830 "TARGET_SSE2"
21831 "punpckhqdq\t{%2, %0|%0, %2}"
21832 [(set_attr "type" "ssecvt")
21833 (set_attr "mode" "TI")])
21834
21835;; SSE2 moves
21836
21837(define_insn "sse2_movapd"
21838 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
21839 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
21840 UNSPEC_MOVA))]
21841 "TARGET_SSE2
21842 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
21843 "movapd\t{%1, %0|%0, %1}"
21844 [(set_attr "type" "ssemov")
21845 (set_attr "mode" "V2DF")])
21846
21847(define_insn "sse2_movupd"
21848 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
21849 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
21850 UNSPEC_MOVU))]
21851 "TARGET_SSE2
21852 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
21853 "movupd\t{%1, %0|%0, %1}"
21854 [(set_attr "type" "ssecvt")
21855 (set_attr "mode" "V2DF")])
21856
21857(define_insn "sse2_movdqa"
21858 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
21859 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
21860 UNSPEC_MOVA))]
21861 "TARGET_SSE2
21862 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
21863 "movdqa\t{%1, %0|%0, %1}"
21864 [(set_attr "type" "ssemov")
21865 (set_attr "mode" "TI")])
21866
21867(define_insn "sse2_movdqu"
21868 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
21869 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
21870 UNSPEC_MOVU))]
21871 "TARGET_SSE2
21872 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
21873 "movdqu\t{%1, %0|%0, %1}"
21874 [(set_attr "type" "ssecvt")
21875 (set_attr "mode" "TI")])
21876
21877(define_insn "sse2_movdq2q"
21878 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y")
21879 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x")
21880 (parallel [(const_int 0)])))]
21881 "TARGET_SSE2 && !TARGET_64BIT"
21882 "@
21883 movq\t{%1, %0|%0, %1}
21884 movdq2q\t{%1, %0|%0, %1}"
21885 [(set_attr "type" "ssecvt")
21886 (set_attr "mode" "TI")])
21887
21888(define_insn "sse2_movdq2q_rex64"
21889 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y,r")
21890 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x,x")
21891 (parallel [(const_int 0)])))]
21892 "TARGET_SSE2 && TARGET_64BIT"
21893 "@
21894 movq\t{%1, %0|%0, %1}
21895 movdq2q\t{%1, %0|%0, %1}
21896 movd\t{%1, %0|%0, %1}"
21897 [(set_attr "type" "ssecvt")
21898 (set_attr "mode" "TI")])
21899
21900(define_insn "sse2_movq2dq"
21901 [(set (match_operand:V2DI 0 "register_operand" "=x,?x")
21902 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y")
21903 (const_int 0)))]
21904 "TARGET_SSE2 && !TARGET_64BIT"
21905 "@
21906 movq\t{%1, %0|%0, %1}
21907 movq2dq\t{%1, %0|%0, %1}"
21908 [(set_attr "type" "ssecvt,ssemov")
21909 (set_attr "mode" "TI")])
21910
21911(define_insn "sse2_movq2dq_rex64"
21912 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x")
21913 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y,r")
21914 (const_int 0)))]
21915 "TARGET_SSE2 && TARGET_64BIT"
21916 "@
21917 movq\t{%1, %0|%0, %1}
21918 movq2dq\t{%1, %0|%0, %1}
21919 movd\t{%1, %0|%0, %1}"
21920 [(set_attr "type" "ssecvt,ssemov,ssecvt")
21921 (set_attr "mode" "TI")])
21922
21923(define_insn "sse2_movq"
21924 [(set (match_operand:V2DI 0 "register_operand" "=x")
21925 (vec_concat:V2DI (vec_select:DI
21926 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
21927 (parallel [(const_int 0)]))
21928 (const_int 0)))]
21929 "TARGET_SSE2"
21930 "movq\t{%1, %0|%0, %1}"
21931 [(set_attr "type" "ssemov")
21932 (set_attr "mode" "TI")])
21933
21934(define_insn "sse2_loadd"
21935 [(set (match_operand:V4SI 0 "register_operand" "=x")
21936 (vec_merge:V4SI
21937 (vec_duplicate:V4SI (match_operand:SI 1 "nonimmediate_operand" "mr"))
21938 (const_vector:V4SI [(const_int 0)
21939 (const_int 0)
21940 (const_int 0)
21941 (const_int 0)])
21942 (const_int 1)))]
21943 "TARGET_SSE2"
21944 "movd\t{%1, %0|%0, %1}"
21945 [(set_attr "type" "ssemov")
21946 (set_attr "mode" "TI")])
21947
21948(define_insn "sse2_stored"
21949 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
21950 (vec_select:SI
21951 (match_operand:V4SI 1 "register_operand" "x")
21952 (parallel [(const_int 0)])))]
21953 "TARGET_SSE2"
21954 "movd\t{%1, %0|%0, %1}"
21955 [(set_attr "type" "ssemov")
21956 (set_attr "mode" "TI")])
21957
21958(define_insn "sse2_movhpd"
21959 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
21960 (vec_merge:V2DF
21961 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
21962 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
21963 (const_int 2)))]
21964 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
21965 "movhpd\t{%2, %0|%0, %2}"
21966 [(set_attr "type" "ssecvt")
21967 (set_attr "mode" "V2DF")])
21968
21969(define_insn "sse2_movlpd"
21970 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
21971 (vec_merge:V2DF
21972 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
21973 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
21974 (const_int 1)))]
21975 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
21976 "movlpd\t{%2, %0|%0, %2}"
21977 [(set_attr "type" "ssecvt")
21978 (set_attr "mode" "V2DF")])
21979
21980(define_expand "sse2_loadsd"
21981 [(match_operand:V2DF 0 "register_operand" "")
21982 (match_operand:DF 1 "memory_operand" "")]
21983 "TARGET_SSE2"
21984{
21985 emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
21986 CONST0_RTX (V2DFmode)));
21987 DONE;
21988})
21989
21990(define_insn "sse2_loadsd_1"
21991 [(set (match_operand:V2DF 0 "register_operand" "=x")
21992 (vec_merge:V2DF
21993 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m"))
21994 (match_operand:V2DF 2 "const0_operand" "X")
21995 (const_int 1)))]
21996 "TARGET_SSE2"
21997 "movsd\t{%1, %0|%0, %1}"
21998 [(set_attr "type" "ssecvt")
21999 (set_attr "mode" "DF")])
22000
22001(define_insn "sse2_movsd"
22002 [(set (match_operand:V2DF 0 "register_operand" "=x")
22003 (vec_merge:V2DF
22004 (match_operand:V2DF 1 "register_operand" "0")
22005 (match_operand:V2DF 2 "register_operand" "x")
22006 (const_int 1)))]
22007 "TARGET_SSE2"
22008 "movsd\t{%2, %0|%0, %2}"
22009 [(set_attr "type" "ssecvt")
22010 (set_attr "mode" "DF")])
22011
22012(define_insn "sse2_storesd"
22013 [(set (match_operand:DF 0 "memory_operand" "=m")
22014 (vec_select:DF
22015 (match_operand:V2DF 1 "register_operand" "x")
22016 (parallel [(const_int 0)])))]
22017 "TARGET_SSE2"
22018 "movsd\t{%1, %0|%0, %1}"
22019 [(set_attr "type" "ssecvt")
22020 (set_attr "mode" "DF")])
22021
22022(define_insn "sse2_shufpd"
22023 [(set (match_operand:V2DF 0 "register_operand" "=x")
22024 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
22025 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
22026 (match_operand:SI 3 "immediate_operand" "i")]
22027 UNSPEC_SHUFFLE))]
22028 "TARGET_SSE2"
22029 ;; @@@ check operand order for intel/nonintel syntax
22030 "shufpd\t{%3, %2, %0|%0, %2, %3}"
22031 [(set_attr "type" "ssecvt")
22032 (set_attr "mode" "V2DF")])
22033
22034(define_insn "sse2_clflush"
22035 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
22036 UNSPECV_CLFLUSH)]
22037 "TARGET_SSE2"
22038 "clflush %0"
22039 [(set_attr "type" "sse")
22040 (set_attr "memory" "unknown")])
22041
22042(define_expand "sse2_mfence"
22043 [(set (match_dup 0)
22044 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
22045 "TARGET_SSE2"
22046{
22047 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
22048 MEM_VOLATILE_P (operands[0]) = 1;
22049})
22050
22051(define_insn "*mfence_insn"
22052 [(set (match_operand:BLK 0 "" "")
22053 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
22054 "TARGET_SSE2"
22055 "mfence"
22056 [(set_attr "type" "sse")
22057 (set_attr "memory" "unknown")])
22058
22059(define_expand "sse2_lfence"
22060 [(set (match_dup 0)
22061 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
22062 "TARGET_SSE2"
22063{
22064 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
22065 MEM_VOLATILE_P (operands[0]) = 1;
22066})
22067
22068(define_insn "*lfence_insn"
22069 [(set (match_operand:BLK 0 "" "")
22070 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
22071 "TARGET_SSE2"
22072 "lfence"
22073 [(set_attr "type" "sse")
22074 (set_attr "memory" "unknown")])