155a156,161
>
> ; For SSE4A support
> (UNSPEC_EXTRQI 130)
> (UNSPEC_EXTRQ 131)
> (UNSPEC_INSERTQI 132)
> (UNSPEC_INSERTQ 133)
195c201,202
< (define_attr "cpu" "i386,i486,pentium,pentiumpro,geode,k6,athlon,pentium4,k8,nocona,core2,generic32,generic64"
---
> (define_attr "cpu" "i386,i486,pentium,pentiumpro,geode,k6,athlon,pentium4,k8,
> nocona,core2,generic32,generic64,amdfam10"
206c213
< str,cld,
---
> str,bitmanip,cld,
209c216
< sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
---
> sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,sseins,
223c230
< sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
---
> sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,sseins")
233c240,241
< (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
---
> (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave,
> bitmanip")
287c295
< (ior (eq_attr "type" "imovx,setcc,icmov")
---
> (ior (eq_attr "type" "imovx,setcc,icmov,bitmanip")
416c424
< imov,imovx,icmp,test,
---
> imov,imovx,icmp,test,bitmanip,
970a979
> (set_attr "amdfam10_decode" "direct")
974c983
<
---
> ;; comi*, ucomi*, fcomi*, ficomi*,fucomi* (i387 instructions set condition codes)
988c997,998
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "direct")])
1003c1013,1014
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "direct")])
1022c1033,1034
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "direct")])
1037c1049,1050
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "direct")])
1052c1065,1066
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "direct")])
1071c1085,1086
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "direct")])
1277c1292,1293
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "double")])
1394c1410,1411
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "double")])
1395a1413
> ;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10
1568c1586,1587
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "vector")])
1569a1589
> ;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10
2123c2143,2144
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "double")])
4153c4174,4175
< (set_attr "athlon_decode" "double,vector")])
---
> (set_attr "athlon_decode" "double,vector")
> (set_attr "amdfam10_decode" "double,double")])
4162c4184,4185
< (set_attr "athlon_decode" "double,vector")])
---
> (set_attr "athlon_decode" "double,vector")
> (set_attr "amdfam10_decode" "double,double")])
4171c4194,4195
< (set_attr "athlon_decode" "double,vector")])
---
> (set_attr "athlon_decode" "double,vector")
> (set_attr "amdfam10_decode" "double,double")])
4180c4204,4205
< (set_attr "athlon_decode" "double,vector")])
---
> (set_attr "athlon_decode" "double,vector")
> (set_attr "amdfam10_decode" "double,double")])
4441c4466,4467
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "vector")])
4491a4518
> (set_attr "amdfam10_decode" "*,*,vector,double")
4501a4529
> (set_attr "amdfam10_decode" "vector,double")
4534a4563
> (set_attr "amdfam10_decode" "*,*,vector,double")
4544a4574
> (set_attr "amdfam10_decode" "vector,double")
4602a4633
> (set_attr "amdfam10_decode" "*,*,vector,double")
4612a4644
> (set_attr "amdfam10_decode" "vector,double")
4645a4678
> (set_attr "amdfam10_decode" "*,*,vector,double")
4655a4689
> (set_attr "amdfam10_decode" "vector,double")
6862a6897,6904
> ;; On AMDFAM10
> ;; IMUL reg64, reg64, imm8 Direct
> ;; IMUL reg64, mem64, imm8 VectorPath
> ;; IMUL reg64, reg64, imm32 Direct
> ;; IMUL reg64, mem64, imm32 VectorPath
> ;; IMUL reg64, reg64 Direct
> ;; IMUL reg64, mem64 Direct
>
6884a6927,6931
> (set (attr "amdfam10_decode")
> (cond [(and (eq_attr "alternative" "0,1")
> (match_operand 1 "memory_operand" ""))
> (const_string "vector")]
> (const_string "direct")))
6894a6942,6949
> ;; On AMDFAM10
> ;; IMUL reg32, reg32, imm8 Direct
> ;; IMUL reg32, mem32, imm8 VectorPath
> ;; IMUL reg32, reg32, imm32 Direct
> ;; IMUL reg32, mem32, imm32 VectorPath
> ;; IMUL reg32, reg32 Direct
> ;; IMUL reg32, mem32 Direct
>
6915a6971,6975
> (set (attr "amdfam10_decode")
> (cond [(and (eq_attr "alternative" "0,1")
> (match_operand 1 "memory_operand" ""))
> (const_string "vector")]
> (const_string "direct")))
6940a7001,7005
> (set (attr "amdfam10_decode")
> (cond [(and (eq_attr "alternative" "0,1")
> (match_operand 1 "memory_operand" ""))
> (const_string "vector")]
> (const_string "direct")))
6950a7016,7022
> ;; On AMDFAM10
> ;; IMUL reg16, reg16, imm8 VectorPath
> ;; IMUL reg16, mem16, imm8 VectorPath
> ;; IMUL reg16, reg16, imm16 VectorPath
> ;; IMUL reg16, mem16, imm16 VectorPath
> ;; IMUL reg16, reg16 Direct
> ;; IMUL reg16, mem16 Direct
6968a7041,7044
> (set (attr "amdfam10_decode")
> (cond [(eq_attr "alternative" "0,1")
> (const_string "vector")]
> (const_string "direct")))
6978a7055,7058
> ;;On AMDFAM10
> ;; MUL reg8 Direct
> ;; MUL mem8 Direct
>
6992a7073
> (set_attr "amdfam10_decode" "direct")
7018a7100
> (set_attr "amdfam10_decode" "direct")
7042a7125
> (set_attr "amdfam10_decode" "direct")
7068a7152
> (set_attr "amdfam10_decode" "double")
7095a7180
> (set_attr "amdfam10_decode" "double")
7121a7207
> (set_attr "amdfam10_decode" "double")
7147a7234
> (set_attr "amdfam10_decode" "double")
7183a7271
> (set_attr "amdfam10_decode" "double")
7218a7307
> (set_attr "amdfam10_decode" "double")
7240a7330
> (set_attr "amdfam10_decode" "double")
7275a7366
> (set_attr "amdfam10_decode" "double")
7309a7401
> (set_attr "amdfam10_decode" "double")
7330a7423
> (set_attr "amdfam10_decode" "double")
10312c10405,10406
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "vector")])
10527c10621,10622
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "vector")])
11287c11382,11383
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "vector")])
14561c14657,14663
< "")
---
> {
> if (TARGET_ABM)
> {
> emit_insn (gen_clzsi2_abm (operands[0], operands[1]));
> DONE;
> }
> })
14562a14665,14674
> (define_insn "clzsi2_abm"
> [(set (match_operand:SI 0 "register_operand" "=r")
> (clz:SI (match_operand:SI 1 "nonimmediate_operand" "")))
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_ABM"
> "lzcnt{l}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "SI")])
>
14570c14682,14683
< [(set_attr "prefix_0f" "1")])
---
> [(set_attr "prefix_0f" "1")
> (set_attr "mode" "SI")])
14571a14685,14720
> (define_insn "popcountsi2"
> [(set (match_operand:SI 0 "register_operand" "=r")
> (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "")))
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_POPCNT"
> "popcnt{l}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "SI")])
>
> (define_insn "*popcountsi2_cmp"
> [(set (reg FLAGS_REG)
> (compare
> (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))
> (const_int 0)))
> (set (match_operand:SI 0 "register_operand" "=r")
> (popcount:SI (match_dup 1)))]
> "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
> "popcnt{l}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "SI")])
>
> (define_insn "*popcountsi2_cmp_zext"
> [(set (reg FLAGS_REG)
> (compare
> (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))
> (const_int 0)))
> (set (match_operand:DI 0 "register_operand" "=r")
> (zero_extend:DI(popcount:SI (match_dup 1))))]
> "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
> "popcnt{l}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "SI")])
>
14582c14731,14737
< "")
---
> {
> if (TARGET_ABM)
> {
> emit_insn (gen_clzdi2_abm (operands[0], operands[1]));
> DONE;
> }
> })
14583a14739,14748
> (define_insn "clzdi2_abm"
> [(set (match_operand:DI 0 "register_operand" "=r")
> (clz:DI (match_operand:DI 1 "nonimmediate_operand" "")))
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_64BIT && TARGET_ABM"
> "lzcnt{q}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "DI")])
>
14591c14756,14841
< [(set_attr "prefix_0f" "1")])
---
> [(set_attr "prefix_0f" "1")
> (set_attr "mode" "DI")])
>
> (define_insn "popcountdi2"
> [(set (match_operand:DI 0 "register_operand" "=r")
> (popcount:DI (match_operand:DI 1 "nonimmediate_operand" "")))
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_64BIT && TARGET_POPCNT"
> "popcnt{q}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "DI")])
>
> (define_insn "*popcountdi2_cmp"
> [(set (reg FLAGS_REG)
> (compare
> (popcount:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))
> (const_int 0)))
> (set (match_operand:DI 0 "register_operand" "=r")
> (popcount:DI (match_dup 1)))]
> "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
> "popcnt{q}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "DI")])
>
> (define_expand "clzhi2"
> [(parallel
> [(set (match_operand:HI 0 "register_operand" "")
> (minus:HI (const_int 15)
> (clz:HI (match_operand:HI 1 "nonimmediate_operand" ""))))
> (clobber (reg:CC FLAGS_REG))])
> (parallel
> [(set (match_dup 0) (xor:HI (match_dup 0) (const_int 15)))
> (clobber (reg:CC FLAGS_REG))])]
> ""
> {
> if (TARGET_ABM)
> {
> emit_insn (gen_clzhi2_abm (operands[0], operands[1]));
> DONE;
> }
> })
>
> (define_insn "clzhi2_abm"
> [(set (match_operand:HI 0 "register_operand" "=r")
> (clz:HI (match_operand:HI 1 "nonimmediate_operand" "")))
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_ABM"
> "lzcnt{w}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "HI")])
>
> (define_insn "*bsrhi"
> [(set (match_operand:HI 0 "register_operand" "=r")
> (minus:HI (const_int 15)
> (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))))
> (clobber (reg:CC FLAGS_REG))]
> ""
> "bsr{w}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_0f" "1")
> (set_attr "mode" "HI")])
>
> (define_insn "popcounthi2"
> [(set (match_operand:HI 0 "register_operand" "=r")
> (popcount:HI (match_operand:HI 1 "nonimmediate_operand" "")))
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_POPCNT"
> "popcnt{w}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "HI")])
>
> (define_insn "*popcounthi2_cmp"
> [(set (reg FLAGS_REG)
> (compare
> (popcount:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))
> (const_int 0)))
> (set (match_operand:HI 0 "register_operand" "=r")
> (popcount:HI (match_dup 1)))]
> "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
> "popcnt{w}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "HI")])
15497c15747,15748
< (set_attr "athlon_decode" "direct,*")])
---
> (set_attr "athlon_decode" "direct,*")
> (set_attr "amdfam10_decode" "direct,*")])
15506c15757,15758
< (set_attr "athlon_decode" "*")])
---
> (set_attr "athlon_decode" "*")
> (set_attr "amdfam10_decode" "*")])
15515c15767,15768
< (set_attr "athlon_decode" "direct")])
---
> (set_attr "athlon_decode" "direct")
> (set_attr "amdfam10_decode" "direct")])
15535c15788,15789
< (set_attr "athlon_decode" "direct,*")])
---
> (set_attr "athlon_decode" "direct,*")
> (set_attr "amdfam10_decode" "direct,*")])
15544c15798,15799
< (set_attr "athlon_decode" "*")])
---
> (set_attr "athlon_decode" "*")
> (set_attr "amdfam10_decode" "*")])
15553c15808,15809
< (set_attr "athlon_decode" "direct")])
---
> (set_attr "athlon_decode" "direct")
> (set_attr "amdfam10_decode" "direct")])
15564c15820,15821
< (set_attr "athlon_decode" "direct")])
---
> (set_attr "athlon_decode" "direct")
> (set_attr "amdfam10_decode" "direct")])
15573c15830,15831
< (set_attr "athlon_decode" "direct")])
---
> (set_attr "athlon_decode" "direct")
> (set_attr "amdfam10_decode" "direct")])
15583c15841,15842
< (set_attr "athlon_decode" "direct")])
---
> (set_attr "athlon_decode" "direct")
> (set_attr "amdfam10_decode" "direct")])
15593c15852,15853
< (set_attr "athlon_decode" "direct")])
---
> (set_attr "athlon_decode" "direct")
> (set_attr "amdfam10_decode" "direct")])
20394c20654
< "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
---
> "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
20407c20667
< "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
---
> "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
20421c20681
< "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
---
> "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
20438c20698
< "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
---
> "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
20454c20714
< "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
---
> "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
20470c20730
< "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size"
---
> "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size"
>
> ; For SSE4A support
> (UNSPEC_EXTRQI 130)
> (UNSPEC_EXTRQ 131)
> (UNSPEC_INSERTQI 132)
> (UNSPEC_INSERTQ 133)
195c201,202
< (define_attr "cpu" "i386,i486,pentium,pentiumpro,geode,k6,athlon,pentium4,k8,nocona,core2,generic32,generic64"
---
> (define_attr "cpu" "i386,i486,pentium,pentiumpro,geode,k6,athlon,pentium4,k8,
> nocona,core2,generic32,generic64,amdfam10"
206c213
< str,cld,
---
> str,bitmanip,cld,
209c216
< sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
---
> sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,sseins,
223c230
< sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
---
> sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,sseins")
233c240,241
< (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
---
> (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave,
> bitmanip")
287c295
< (ior (eq_attr "type" "imovx,setcc,icmov")
---
> (ior (eq_attr "type" "imovx,setcc,icmov,bitmanip")
416c424
< imov,imovx,icmp,test,
---
> imov,imovx,icmp,test,bitmanip,
970a979
> (set_attr "amdfam10_decode" "direct")
974c983
<
---
> ;; comi*, ucomi*, fcomi*, ficomi*,fucomi* (i387 instructions set condition codes)
988c997,998
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "direct")])
1003c1013,1014
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "direct")])
1022c1033,1034
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "direct")])
1037c1049,1050
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "direct")])
1052c1065,1066
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "direct")])
1071c1085,1086
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "direct")])
1277c1292,1293
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "double")])
1394c1410,1411
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "double")])
1395a1413
> ;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10
1568c1586,1587
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "vector")])
1569a1589
> ;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10
2123c2143,2144
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "double")])
4153c4174,4175
< (set_attr "athlon_decode" "double,vector")])
---
> (set_attr "athlon_decode" "double,vector")
> (set_attr "amdfam10_decode" "double,double")])
4162c4184,4185
< (set_attr "athlon_decode" "double,vector")])
---
> (set_attr "athlon_decode" "double,vector")
> (set_attr "amdfam10_decode" "double,double")])
4171c4194,4195
< (set_attr "athlon_decode" "double,vector")])
---
> (set_attr "athlon_decode" "double,vector")
> (set_attr "amdfam10_decode" "double,double")])
4180c4204,4205
< (set_attr "athlon_decode" "double,vector")])
---
> (set_attr "athlon_decode" "double,vector")
> (set_attr "amdfam10_decode" "double,double")])
4441c4466,4467
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "vector")])
4491a4518
> (set_attr "amdfam10_decode" "*,*,vector,double")
4501a4529
> (set_attr "amdfam10_decode" "vector,double")
4534a4563
> (set_attr "amdfam10_decode" "*,*,vector,double")
4544a4574
> (set_attr "amdfam10_decode" "vector,double")
4602a4633
> (set_attr "amdfam10_decode" "*,*,vector,double")
4612a4644
> (set_attr "amdfam10_decode" "vector,double")
4645a4678
> (set_attr "amdfam10_decode" "*,*,vector,double")
4655a4689
> (set_attr "amdfam10_decode" "vector,double")
6862a6897,6904
> ;; On AMDFAM10
> ;; IMUL reg64, reg64, imm8 Direct
> ;; IMUL reg64, mem64, imm8 VectorPath
> ;; IMUL reg64, reg64, imm32 Direct
> ;; IMUL reg64, mem64, imm32 VectorPath
> ;; IMUL reg64, reg64 Direct
> ;; IMUL reg64, mem64 Direct
>
6884a6927,6931
> (set (attr "amdfam10_decode")
> (cond [(and (eq_attr "alternative" "0,1")
> (match_operand 1 "memory_operand" ""))
> (const_string "vector")]
> (const_string "direct")))
6894a6942,6949
> ;; On AMDFAM10
> ;; IMUL reg32, reg32, imm8 Direct
> ;; IMUL reg32, mem32, imm8 VectorPath
> ;; IMUL reg32, reg32, imm32 Direct
> ;; IMUL reg32, mem32, imm32 VectorPath
> ;; IMUL reg32, reg32 Direct
> ;; IMUL reg32, mem32 Direct
>
6915a6971,6975
> (set (attr "amdfam10_decode")
> (cond [(and (eq_attr "alternative" "0,1")
> (match_operand 1 "memory_operand" ""))
> (const_string "vector")]
> (const_string "direct")))
6940a7001,7005
> (set (attr "amdfam10_decode")
> (cond [(and (eq_attr "alternative" "0,1")
> (match_operand 1 "memory_operand" ""))
> (const_string "vector")]
> (const_string "direct")))
6950a7016,7022
> ;; On AMDFAM10
> ;; IMUL reg16, reg16, imm8 VectorPath
> ;; IMUL reg16, mem16, imm8 VectorPath
> ;; IMUL reg16, reg16, imm16 VectorPath
> ;; IMUL reg16, mem16, imm16 VectorPath
> ;; IMUL reg16, reg16 Direct
> ;; IMUL reg16, mem16 Direct
6968a7041,7044
> (set (attr "amdfam10_decode")
> (cond [(eq_attr "alternative" "0,1")
> (const_string "vector")]
> (const_string "direct")))
6978a7055,7058
> ;;On AMDFAM10
> ;; MUL reg8 Direct
> ;; MUL mem8 Direct
>
6992a7073
> (set_attr "amdfam10_decode" "direct")
7018a7100
> (set_attr "amdfam10_decode" "direct")
7042a7125
> (set_attr "amdfam10_decode" "direct")
7068a7152
> (set_attr "amdfam10_decode" "double")
7095a7180
> (set_attr "amdfam10_decode" "double")
7121a7207
> (set_attr "amdfam10_decode" "double")
7147a7234
> (set_attr "amdfam10_decode" "double")
7183a7271
> (set_attr "amdfam10_decode" "double")
7218a7307
> (set_attr "amdfam10_decode" "double")
7240a7330
> (set_attr "amdfam10_decode" "double")
7275a7366
> (set_attr "amdfam10_decode" "double")
7309a7401
> (set_attr "amdfam10_decode" "double")
7330a7423
> (set_attr "amdfam10_decode" "double")
10312c10405,10406
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "vector")])
10527c10621,10622
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "vector")])
11287c11382,11383
< (set_attr "athlon_decode" "vector")])
---
> (set_attr "athlon_decode" "vector")
> (set_attr "amdfam10_decode" "vector")])
14561c14657,14663
< "")
---
> {
> if (TARGET_ABM)
> {
> emit_insn (gen_clzsi2_abm (operands[0], operands[1]));
> DONE;
> }
> })
14562a14665,14674
> (define_insn "clzsi2_abm"
> [(set (match_operand:SI 0 "register_operand" "=r")
> (clz:SI (match_operand:SI 1 "nonimmediate_operand" "")))
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_ABM"
> "lzcnt{l}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "SI")])
>
14570c14682,14683
< [(set_attr "prefix_0f" "1")])
---
> [(set_attr "prefix_0f" "1")
> (set_attr "mode" "SI")])
14571a14685,14720
> (define_insn "popcountsi2"
> [(set (match_operand:SI 0 "register_operand" "=r")
> (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "")))
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_POPCNT"
> "popcnt{l}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "SI")])
>
> (define_insn "*popcountsi2_cmp"
> [(set (reg FLAGS_REG)
> (compare
> (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))
> (const_int 0)))
> (set (match_operand:SI 0 "register_operand" "=r")
> (popcount:SI (match_dup 1)))]
> "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
> "popcnt{l}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "SI")])
>
> (define_insn "*popcountsi2_cmp_zext"
> [(set (reg FLAGS_REG)
> (compare
> (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))
> (const_int 0)))
> (set (match_operand:DI 0 "register_operand" "=r")
> (zero_extend:DI(popcount:SI (match_dup 1))))]
> "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
> "popcnt{l}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "SI")])
>
14582c14731,14737
< "")
---
> {
> if (TARGET_ABM)
> {
> emit_insn (gen_clzdi2_abm (operands[0], operands[1]));
> DONE;
> }
> })
14583a14739,14748
> (define_insn "clzdi2_abm"
> [(set (match_operand:DI 0 "register_operand" "=r")
> (clz:DI (match_operand:DI 1 "nonimmediate_operand" "")))
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_64BIT && TARGET_ABM"
> "lzcnt{q}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "DI")])
>
14591c14756,14841
< [(set_attr "prefix_0f" "1")])
---
> [(set_attr "prefix_0f" "1")
> (set_attr "mode" "DI")])
>
> (define_insn "popcountdi2"
> [(set (match_operand:DI 0 "register_operand" "=r")
> (popcount:DI (match_operand:DI 1 "nonimmediate_operand" "")))
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_64BIT && TARGET_POPCNT"
> "popcnt{q}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "DI")])
>
> (define_insn "*popcountdi2_cmp"
> [(set (reg FLAGS_REG)
> (compare
> (popcount:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))
> (const_int 0)))
> (set (match_operand:DI 0 "register_operand" "=r")
> (popcount:DI (match_dup 1)))]
> "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
> "popcnt{q}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "DI")])
>
> (define_expand "clzhi2"
> [(parallel
> [(set (match_operand:HI 0 "register_operand" "")
> (minus:HI (const_int 15)
> (clz:HI (match_operand:HI 1 "nonimmediate_operand" ""))))
> (clobber (reg:CC FLAGS_REG))])
> (parallel
> [(set (match_dup 0) (xor:HI (match_dup 0) (const_int 15)))
> (clobber (reg:CC FLAGS_REG))])]
> ""
> {
> if (TARGET_ABM)
> {
> emit_insn (gen_clzhi2_abm (operands[0], operands[1]));
> DONE;
> }
> })
>
> (define_insn "clzhi2_abm"
> [(set (match_operand:HI 0 "register_operand" "=r")
> (clz:HI (match_operand:HI 1 "nonimmediate_operand" "")))
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_ABM"
> "lzcnt{w}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "HI")])
>
> (define_insn "*bsrhi"
> [(set (match_operand:HI 0 "register_operand" "=r")
> (minus:HI (const_int 15)
> (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))))
> (clobber (reg:CC FLAGS_REG))]
> ""
> "bsr{w}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_0f" "1")
> (set_attr "mode" "HI")])
>
> (define_insn "popcounthi2"
> [(set (match_operand:HI 0 "register_operand" "=r")
> (popcount:HI (match_operand:HI 1 "nonimmediate_operand" "")))
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_POPCNT"
> "popcnt{w}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "HI")])
>
> (define_insn "*popcounthi2_cmp"
> [(set (reg FLAGS_REG)
> (compare
> (popcount:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))
> (const_int 0)))
> (set (match_operand:HI 0 "register_operand" "=r")
> (popcount:HI (match_dup 1)))]
> "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
> "popcnt{w}\t{%1, %0|%0, %1}"
> [(set_attr "prefix_rep" "1")
> (set_attr "type" "bitmanip")
> (set_attr "mode" "HI")])
15497c15747,15748
< (set_attr "athlon_decode" "direct,*")])
---
> (set_attr "athlon_decode" "direct,*")
> (set_attr "amdfam10_decode" "direct,*")])
15506c15757,15758
< (set_attr "athlon_decode" "*")])
---
> (set_attr "athlon_decode" "*")
> (set_attr "amdfam10_decode" "*")])
15515c15767,15768
< (set_attr "athlon_decode" "direct")])
---
> (set_attr "athlon_decode" "direct")
> (set_attr "amdfam10_decode" "direct")])
15535c15788,15789
< (set_attr "athlon_decode" "direct,*")])
---
> (set_attr "athlon_decode" "direct,*")
> (set_attr "amdfam10_decode" "direct,*")])
15544c15798,15799
< (set_attr "athlon_decode" "*")])
---
> (set_attr "athlon_decode" "*")
> (set_attr "amdfam10_decode" "*")])
15553c15808,15809
< (set_attr "athlon_decode" "direct")])
---
> (set_attr "athlon_decode" "direct")
> (set_attr "amdfam10_decode" "direct")])
15564c15820,15821
< (set_attr "athlon_decode" "direct")])
---
> (set_attr "athlon_decode" "direct")
> (set_attr "amdfam10_decode" "direct")])
15573c15830,15831
< (set_attr "athlon_decode" "direct")])
---
> (set_attr "athlon_decode" "direct")
> (set_attr "amdfam10_decode" "direct")])
15583c15841,15842
< (set_attr "athlon_decode" "direct")])
---
> (set_attr "athlon_decode" "direct")
> (set_attr "amdfam10_decode" "direct")])
15593c15852,15853
< (set_attr "athlon_decode" "direct")])
---
> (set_attr "athlon_decode" "direct")
> (set_attr "amdfam10_decode" "direct")])
20394c20654
< "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
---
> "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
20407c20667
< "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
---
> "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
20421c20681
< "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
---
> "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
20438c20698
< "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
---
> "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
20454c20714
< "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
---
> "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
20470c20730
< "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size"
---
> "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size"