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i386.h (237021) i386.h (251212)
1/* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by

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136#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
137#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
138#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
139#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
140#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
141#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
142#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
143#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
1/* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by

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136#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
137#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
138#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
139#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
140#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
141#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
142#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
143#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
144#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
144
145#define TUNEMASK (1 << ix86_tune)
146extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
147extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
148extern const int x86_branch_hints, x86_unroll_strlen;
149extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
150extern const int x86_use_himode_fiop, x86_use_simode_fiop;
151extern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write;
152extern const int x86_read_modify, x86_split_long_moves;
153extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
154extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
155extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
156extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
157extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
158extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
159extern const int x86_epilogue_using_move, x86_decompose_lea;
160extern const int x86_arch_always_fancy_math_387, x86_shift1;
161extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs;
145
146#define TUNEMASK (1 << ix86_tune)
147extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
148extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
149extern const int x86_branch_hints, x86_unroll_strlen;
150extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
151extern const int x86_use_himode_fiop, x86_use_simode_fiop;
152extern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write;
153extern const int x86_read_modify, x86_split_long_moves;
154extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
155extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
156extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
157extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
158extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
159extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
160extern const int x86_epilogue_using_move, x86_decompose_lea;
161extern const int x86_arch_always_fancy_math_387, x86_shift1;
162extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs;
163extern const int x86_sse_unaligned_move_optimal;
162extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
163extern const int x86_use_ffreep;
164extern const int x86_inter_unit_moves, x86_schedule;
165extern const int x86_use_bt;
164extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
165extern const int x86_use_ffreep;
166extern const int x86_inter_unit_moves, x86_schedule;
167extern const int x86_use_bt;
166extern const int x86_cmpxchg, x86_cmpxchg8b, x86_cmpxchg16b, x86_xadd;
168extern const int x86_cmpxchg, x86_cmpxchg8b, x86_xadd;
167extern const int x86_use_incdec;
168extern const int x86_pad_returns;
169extern const int x86_partial_flag_reg_stall;
169extern const int x86_use_incdec;
170extern const int x86_pad_returns;
171extern const int x86_partial_flag_reg_stall;
170extern int x86_prefetch_sse;
172extern int x86_prefetch_sse, x86_cmpxchg16b;
171
172#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
173#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
174#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
175#define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
176#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
177/* For sane SSE instruction set generation we need fcomi instruction. It is
178 safe to enable all CMOVE instructions. */

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202#define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
203#define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
204#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
205#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
206#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
207#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
208#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
209 (x86_sse_partial_reg_dependency & TUNEMASK)
173
174#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
175#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
176#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
177#define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
178#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
179/* For sane SSE instruction set generation we need fcomi instruction. It is
180 safe to enable all CMOVE instructions. */

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204#define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
205#define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
206#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
207#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
208#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
209#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
210#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
211 (x86_sse_partial_reg_dependency & TUNEMASK)
212#define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
213 (x86_sse_unaligned_move_optimal & TUNEMASK)
210#define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK)
211#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
212#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
213#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
214#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
215#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
216#define TARGET_PREFETCH_SSE (x86_prefetch_sse)
217#define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)

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232
233#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
234#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
235#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
236#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
237
238#define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch))
239#define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch))
214#define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK)
215#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
216#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
217#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
218#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
219#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
220#define TARGET_PREFETCH_SSE (x86_prefetch_sse)
221#define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)

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236
237#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
238#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
239#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
240#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
241
242#define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch))
243#define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch))
240#define TARGET_CMPXCHG16B (x86_cmpxchg16b & (1 << ix86_arch))
244#define TARGET_CMPXCHG16B (x86_cmpxchg16b)
241#define TARGET_XADD (x86_xadd & (1 << ix86_arch))
242
243#ifndef TARGET_64BIT_DEFAULT
244#define TARGET_64BIT_DEFAULT 0
245#endif
246#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
247#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
248#endif

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394 { \
395 builtin_define ("__tune_athlon__"); \
396 /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \
397 if (last_tune_char != 'n' && last_tune_char != 'd') \
398 builtin_define ("__tune_athlon_sse__"); \
399 } \
400 else if (TARGET_K8) \
401 builtin_define ("__tune_k8__"); \
245#define TARGET_XADD (x86_xadd & (1 << ix86_arch))
246
247#ifndef TARGET_64BIT_DEFAULT
248#define TARGET_64BIT_DEFAULT 0
249#endif
250#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
251#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
252#endif

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398 { \
399 builtin_define ("__tune_athlon__"); \
400 /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \
401 if (last_tune_char != 'n' && last_tune_char != 'd') \
402 builtin_define ("__tune_athlon_sse__"); \
403 } \
404 else if (TARGET_K8) \
405 builtin_define ("__tune_k8__"); \
406 else if (TARGET_AMDFAM10) \
407 builtin_define ("__tune_amdfam10__"); \
402 else if (TARGET_PENTIUM4) \
403 builtin_define ("__tune_pentium4__"); \
404 else if (TARGET_NOCONA) \
405 builtin_define ("__tune_nocona__"); \
406 else if (TARGET_CORE2) \
407 builtin_define ("__tune_core2__"); \
408 \
409 if (TARGET_MMX) \

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415 if (TARGET_SSE) \
416 builtin_define ("__SSE__"); \
417 if (TARGET_SSE2) \
418 builtin_define ("__SSE2__"); \
419 if (TARGET_SSE3) \
420 builtin_define ("__SSE3__"); \
421 if (TARGET_SSSE3) \
422 builtin_define ("__SSSE3__"); \
408 else if (TARGET_PENTIUM4) \
409 builtin_define ("__tune_pentium4__"); \
410 else if (TARGET_NOCONA) \
411 builtin_define ("__tune_nocona__"); \
412 else if (TARGET_CORE2) \
413 builtin_define ("__tune_core2__"); \
414 \
415 if (TARGET_MMX) \

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421 if (TARGET_SSE) \
422 builtin_define ("__SSE__"); \
423 if (TARGET_SSE2) \
424 builtin_define ("__SSE2__"); \
425 if (TARGET_SSE3) \
426 builtin_define ("__SSE3__"); \
427 if (TARGET_SSSE3) \
428 builtin_define ("__SSSE3__"); \
429 if (TARGET_SSE4A) \
430 builtin_define ("__SSE4A__"); \
423 if (TARGET_SSE_MATH && TARGET_SSE) \
424 builtin_define ("__SSE_MATH__"); \
425 if (TARGET_SSE_MATH && TARGET_SSE2) \
426 builtin_define ("__SSE2_MATH__"); \
427 \
428 /* Built-ins based on -march=. */ \
429 if (ix86_arch == PROCESSOR_I486) \
430 { \

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470 if (last_tune_char != 'n' && last_tune_char != 'd') \
471 builtin_define ("__athlon_sse__"); \
472 } \
473 else if (ix86_arch == PROCESSOR_K8) \
474 { \
475 builtin_define ("__k8"); \
476 builtin_define ("__k8__"); \
477 } \
431 if (TARGET_SSE_MATH && TARGET_SSE) \
432 builtin_define ("__SSE_MATH__"); \
433 if (TARGET_SSE_MATH && TARGET_SSE2) \
434 builtin_define ("__SSE2_MATH__"); \
435 \
436 /* Built-ins based on -march=. */ \
437 if (ix86_arch == PROCESSOR_I486) \
438 { \

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478 if (last_tune_char != 'n' && last_tune_char != 'd') \
479 builtin_define ("__athlon_sse__"); \
480 } \
481 else if (ix86_arch == PROCESSOR_K8) \
482 { \
483 builtin_define ("__k8"); \
484 builtin_define ("__k8__"); \
485 } \
486 else if (ix86_arch == PROCESSOR_AMDFAM10) \
487 { \
488 builtin_define ("__amdfam10"); \
489 builtin_define ("__amdfam10__"); \
490 } \
478 else if (ix86_arch == PROCESSOR_PENTIUM4) \
479 { \
480 builtin_define ("__pentium4"); \
481 builtin_define ("__pentium4__"); \
482 } \
483 else if (ix86_arch == PROCESSOR_NOCONA) \
484 { \
485 builtin_define ("__nocona"); \

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508#define TARGET_CPU_DEFAULT_athlon 12
509#define TARGET_CPU_DEFAULT_athlon_sse 13
510#define TARGET_CPU_DEFAULT_k8 14
511#define TARGET_CPU_DEFAULT_pentium_m 15
512#define TARGET_CPU_DEFAULT_prescott 16
513#define TARGET_CPU_DEFAULT_nocona 17
514#define TARGET_CPU_DEFAULT_core2 18
515#define TARGET_CPU_DEFAULT_generic 19
491 else if (ix86_arch == PROCESSOR_PENTIUM4) \
492 { \
493 builtin_define ("__pentium4"); \
494 builtin_define ("__pentium4__"); \
495 } \
496 else if (ix86_arch == PROCESSOR_NOCONA) \
497 { \
498 builtin_define ("__nocona"); \

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521#define TARGET_CPU_DEFAULT_athlon 12
522#define TARGET_CPU_DEFAULT_athlon_sse 13
523#define TARGET_CPU_DEFAULT_k8 14
524#define TARGET_CPU_DEFAULT_pentium_m 15
525#define TARGET_CPU_DEFAULT_prescott 16
526#define TARGET_CPU_DEFAULT_nocona 17
527#define TARGET_CPU_DEFAULT_core2 18
528#define TARGET_CPU_DEFAULT_generic 19
529#define TARGET_CPU_DEFAULT_amdfam10 20
516
517#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
518 "pentiumpro", "pentium2", "pentium3", \
519 "pentium4", "geode", "k6", "k6-2", "k6-3", \
520 "athlon", "athlon-4", "k8", \
521 "pentium-m", "prescott", "nocona", \
530
531#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
532 "pentiumpro", "pentium2", "pentium3", \
533 "pentium4", "geode", "k6", "k6-2", "k6-3", \
534 "athlon", "athlon-4", "k8", \
535 "pentium-m", "prescott", "nocona", \
522 "core2", "generic"}
536 "core2", "generic", "amdfam10"}
523
524#ifndef CC1_SPEC
525#define CC1_SPEC "%(cc1_cpu) "
526#endif
527
528/* This macro defines names of additional specifications to put in the
529 specs that can be used in various specifications like CC1_SPEC. Its
530 definition is an initializer with a subgrouping for each command option.

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2103 PROCESSOR_K6,
2104 PROCESSOR_ATHLON,
2105 PROCESSOR_PENTIUM4,
2106 PROCESSOR_K8,
2107 PROCESSOR_NOCONA,
2108 PROCESSOR_CORE2,
2109 PROCESSOR_GENERIC32,
2110 PROCESSOR_GENERIC64,
537
538#ifndef CC1_SPEC
539#define CC1_SPEC "%(cc1_cpu) "
540#endif
541
542/* This macro defines names of additional specifications to put in the
543 specs that can be used in various specifications like CC1_SPEC. Its
544 definition is an initializer with a subgrouping for each command option.

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2117 PROCESSOR_K6,
2118 PROCESSOR_ATHLON,
2119 PROCESSOR_PENTIUM4,
2120 PROCESSOR_K8,
2121 PROCESSOR_NOCONA,
2122 PROCESSOR_CORE2,
2123 PROCESSOR_GENERIC32,
2124 PROCESSOR_GENERIC64,
2125 PROCESSOR_AMDFAM10,
2111 PROCESSOR_max
2112};
2113
2114extern enum processor_type ix86_tune;
2115extern enum processor_type ix86_arch;
2116
2117enum fpmath_unit
2118{

--- 190 unchanged lines hidden --- 		2126 PROCESSOR_max
2127};
2128
2129extern enum processor_type ix86_tune;
2130extern enum processor_type ix86_arch;
2131
2132enum fpmath_unit
2133{

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