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i386.h (237021) i386.h (251212)
1/* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12GCC is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING. If not, write to
19the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20Boston, MA 02110-1301, USA. */
21
22/* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
24
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
27
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
30
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
36
37/* Define the specific costs for a given cpu */
38
39struct processor_costs {
40 const int add; /* cost of an add instruction */
41 const int lea; /* cost of a lea instruction */
42 const int shift_var; /* variable shift costs */
43 const int shift_const; /* constant shift costs */
44 const int mult_init[5]; /* cost of starting a multiply
45 in QImode, HImode, SImode, DImode, TImode*/
46 const int mult_bit; /* cost of multiply per each bit set */
47 const int divide[5]; /* cost of a divide/mod
48 in QImode, HImode, SImode, DImode, TImode*/
49 int movsx; /* The cost of movsx operation. */
50 int movzx; /* The cost of movzx operation. */
51 const int large_insn; /* insns larger than this cost more */
52 const int move_ratio; /* The threshold of number of scalar
53 memory-to-memory move insns. */
54 const int movzbl_load; /* cost of loading using movzbl */
55 const int int_load[3]; /* cost of loading integer registers
56 in QImode, HImode and SImode relative
57 to reg-reg move (2). */
58 const int int_store[3]; /* cost of storing integer register
59 in QImode, HImode and SImode */
60 const int fp_move; /* cost of reg,reg fld/fst */
61 const int fp_load[3]; /* cost of loading FP register
62 in SFmode, DFmode and XFmode */
63 const int fp_store[3]; /* cost of storing FP register
64 in SFmode, DFmode and XFmode */
65 const int mmx_move; /* cost of moving MMX register. */
66 const int mmx_load[2]; /* cost of loading MMX register
67 in SImode and DImode */
68 const int mmx_store[2]; /* cost of storing MMX register
69 in SImode and DImode */
70 const int sse_move; /* cost of moving SSE register. */
71 const int sse_load[3]; /* cost of loading SSE register
72 in SImode, DImode and TImode*/
73 const int sse_store[3]; /* cost of storing SSE register
74 in SImode, DImode and TImode*/
75 const int mmxsse_to_integer; /* cost of moving mmxsse register to
76 integer and vice versa. */
77 const int prefetch_block; /* bytes moved to cache for prefetch. */
78 const int simultaneous_prefetches; /* number of parallel prefetch
79 operations. */
80 const int branch_cost; /* Default value for BRANCH_COST. */
81 const int fadd; /* cost of FADD and FSUB instructions. */
82 const int fmul; /* cost of FMUL instruction. */
83 const int fdiv; /* cost of FDIV instruction. */
84 const int fabs; /* cost of FABS instruction. */
85 const int fchs; /* cost of FCHS instruction. */
86 const int fsqrt; /* cost of FSQRT instruction. */
87};
88
89extern const struct processor_costs *ix86_cost;
90
91/* Macros used in the machine description to test the flags. */
92
93/* configure can arrange to make this 2, to force a 486. */
94
95#ifndef TARGET_CPU_DEFAULT
96#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
97#endif
98
99#ifndef TARGET_FPMATH_DEFAULT
100#define TARGET_FPMATH_DEFAULT \
101 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
102#endif
103
104#define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
105
106/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
107 compile-time constant. */
108#ifdef IN_LIBGCC2
109#undef TARGET_64BIT
110#ifdef __x86_64__
111#define TARGET_64BIT 1
112#else
113#define TARGET_64BIT 0
114#endif
115#else
116#ifndef TARGET_BI_ARCH
117#undef TARGET_64BIT
118#if TARGET_64BIT_DEFAULT
119#define TARGET_64BIT 1
120#else
121#define TARGET_64BIT 0
122#endif
123#endif
124#endif
125
126#define HAS_LONG_COND_BRANCH 1
127#define HAS_LONG_UNCOND_BRANCH 1
128
129#define TARGET_386 (ix86_tune == PROCESSOR_I386)
130#define TARGET_486 (ix86_tune == PROCESSOR_I486)
131#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
132#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
133#define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
134#define TARGET_K6 (ix86_tune == PROCESSOR_K6)
135#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
136#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
137#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
138#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
139#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
140#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
141#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
142#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
143#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
1/* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12GCC is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING. If not, write to
19the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20Boston, MA 02110-1301, USA. */
21
22/* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
24
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
27
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
30
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
36
37/* Define the specific costs for a given cpu */
38
39struct processor_costs {
40 const int add; /* cost of an add instruction */
41 const int lea; /* cost of a lea instruction */
42 const int shift_var; /* variable shift costs */
43 const int shift_const; /* constant shift costs */
44 const int mult_init[5]; /* cost of starting a multiply
45 in QImode, HImode, SImode, DImode, TImode*/
46 const int mult_bit; /* cost of multiply per each bit set */
47 const int divide[5]; /* cost of a divide/mod
48 in QImode, HImode, SImode, DImode, TImode*/
49 int movsx; /* The cost of movsx operation. */
50 int movzx; /* The cost of movzx operation. */
51 const int large_insn; /* insns larger than this cost more */
52 const int move_ratio; /* The threshold of number of scalar
53 memory-to-memory move insns. */
54 const int movzbl_load; /* cost of loading using movzbl */
55 const int int_load[3]; /* cost of loading integer registers
56 in QImode, HImode and SImode relative
57 to reg-reg move (2). */
58 const int int_store[3]; /* cost of storing integer register
59 in QImode, HImode and SImode */
60 const int fp_move; /* cost of reg,reg fld/fst */
61 const int fp_load[3]; /* cost of loading FP register
62 in SFmode, DFmode and XFmode */
63 const int fp_store[3]; /* cost of storing FP register
64 in SFmode, DFmode and XFmode */
65 const int mmx_move; /* cost of moving MMX register. */
66 const int mmx_load[2]; /* cost of loading MMX register
67 in SImode and DImode */
68 const int mmx_store[2]; /* cost of storing MMX register
69 in SImode and DImode */
70 const int sse_move; /* cost of moving SSE register. */
71 const int sse_load[3]; /* cost of loading SSE register
72 in SImode, DImode and TImode*/
73 const int sse_store[3]; /* cost of storing SSE register
74 in SImode, DImode and TImode*/
75 const int mmxsse_to_integer; /* cost of moving mmxsse register to
76 integer and vice versa. */
77 const int prefetch_block; /* bytes moved to cache for prefetch. */
78 const int simultaneous_prefetches; /* number of parallel prefetch
79 operations. */
80 const int branch_cost; /* Default value for BRANCH_COST. */
81 const int fadd; /* cost of FADD and FSUB instructions. */
82 const int fmul; /* cost of FMUL instruction. */
83 const int fdiv; /* cost of FDIV instruction. */
84 const int fabs; /* cost of FABS instruction. */
85 const int fchs; /* cost of FCHS instruction. */
86 const int fsqrt; /* cost of FSQRT instruction. */
87};
88
89extern const struct processor_costs *ix86_cost;
90
91/* Macros used in the machine description to test the flags. */
92
93/* configure can arrange to make this 2, to force a 486. */
94
95#ifndef TARGET_CPU_DEFAULT
96#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
97#endif
98
99#ifndef TARGET_FPMATH_DEFAULT
100#define TARGET_FPMATH_DEFAULT \
101 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
102#endif
103
104#define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
105
106/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
107 compile-time constant. */
108#ifdef IN_LIBGCC2
109#undef TARGET_64BIT
110#ifdef __x86_64__
111#define TARGET_64BIT 1
112#else
113#define TARGET_64BIT 0
114#endif
115#else
116#ifndef TARGET_BI_ARCH
117#undef TARGET_64BIT
118#if TARGET_64BIT_DEFAULT
119#define TARGET_64BIT 1
120#else
121#define TARGET_64BIT 0
122#endif
123#endif
124#endif
125
126#define HAS_LONG_COND_BRANCH 1
127#define HAS_LONG_UNCOND_BRANCH 1
128
129#define TARGET_386 (ix86_tune == PROCESSOR_I386)
130#define TARGET_486 (ix86_tune == PROCESSOR_I486)
131#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
132#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
133#define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
134#define TARGET_K6 (ix86_tune == PROCESSOR_K6)
135#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
136#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
137#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
138#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
139#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
140#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
141#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
142#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
143#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
144#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
144
145#define TUNEMASK (1 << ix86_tune)
146extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
147extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
148extern const int x86_branch_hints, x86_unroll_strlen;
149extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
150extern const int x86_use_himode_fiop, x86_use_simode_fiop;
151extern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write;
152extern const int x86_read_modify, x86_split_long_moves;
153extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
154extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
155extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
156extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
157extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
158extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
159extern const int x86_epilogue_using_move, x86_decompose_lea;
160extern const int x86_arch_always_fancy_math_387, x86_shift1;
161extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs;
145
146#define TUNEMASK (1 << ix86_tune)
147extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
148extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
149extern const int x86_branch_hints, x86_unroll_strlen;
150extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
151extern const int x86_use_himode_fiop, x86_use_simode_fiop;
152extern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write;
153extern const int x86_read_modify, x86_split_long_moves;
154extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
155extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
156extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
157extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
158extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
159extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
160extern const int x86_epilogue_using_move, x86_decompose_lea;
161extern const int x86_arch_always_fancy_math_387, x86_shift1;
162extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs;
163extern const int x86_sse_unaligned_move_optimal;
162extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
163extern const int x86_use_ffreep;
164extern const int x86_inter_unit_moves, x86_schedule;
165extern const int x86_use_bt;
164extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
165extern const int x86_use_ffreep;
166extern const int x86_inter_unit_moves, x86_schedule;
167extern const int x86_use_bt;
166extern const int x86_cmpxchg, x86_cmpxchg8b, x86_cmpxchg16b, x86_xadd;
168extern const int x86_cmpxchg, x86_cmpxchg8b, x86_xadd;
167extern const int x86_use_incdec;
168extern const int x86_pad_returns;
169extern const int x86_partial_flag_reg_stall;
169extern const int x86_use_incdec;
170extern const int x86_pad_returns;
171extern const int x86_partial_flag_reg_stall;
170extern int x86_prefetch_sse;
172extern int x86_prefetch_sse, x86_cmpxchg16b;
171
172#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
173#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
174#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
175#define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
176#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
177/* For sane SSE instruction set generation we need fcomi instruction. It is
178 safe to enable all CMOVE instructions. */
179#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
180#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
181#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
182#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
183#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)
184#define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
185#define TARGET_MOVX (x86_movx & TUNEMASK)
186#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
187#define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK)
188#define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK)
189#define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK)
190#define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)
191#define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK)
192#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK)
193#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK)
194#define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK)
195#define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK)
196#define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK)
197#define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK)
198#define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK)
199#define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK)
200#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK)
201#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK)
202#define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
203#define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
204#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
205#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
206#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
207#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
208#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
209 (x86_sse_partial_reg_dependency & TUNEMASK)
173
174#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
175#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
176#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
177#define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
178#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
179/* For sane SSE instruction set generation we need fcomi instruction. It is
180 safe to enable all CMOVE instructions. */
181#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
182#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
183#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
184#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
185#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)
186#define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
187#define TARGET_MOVX (x86_movx & TUNEMASK)
188#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
189#define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK)
190#define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK)
191#define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK)
192#define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)
193#define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK)
194#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK)
195#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK)
196#define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK)
197#define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK)
198#define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK)
199#define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK)
200#define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK)
201#define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK)
202#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK)
203#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK)
204#define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
205#define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
206#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
207#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
208#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
209#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
210#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
211 (x86_sse_partial_reg_dependency & TUNEMASK)
212#define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
213 (x86_sse_unaligned_move_optimal & TUNEMASK)
210#define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK)
211#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
212#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
213#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
214#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
215#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
216#define TARGET_PREFETCH_SSE (x86_prefetch_sse)
217#define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)
218#define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK)
219#define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK)
220#define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK)
221#define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK)
222#define TARGET_SCHEDULE (x86_schedule & TUNEMASK)
223#define TARGET_USE_BT (x86_use_bt & TUNEMASK)
224#define TARGET_USE_INCDEC (x86_use_incdec & TUNEMASK)
225#define TARGET_PAD_RETURNS (x86_pad_returns & TUNEMASK)
226
227#define ASSEMBLER_DIALECT (ix86_asm_dialect)
228
229#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
230#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
231 && (ix86_fpmath & FPMATH_387))
232
233#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
234#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
235#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
236#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
237
238#define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch))
239#define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch))
214#define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK)
215#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
216#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
217#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
218#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
219#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
220#define TARGET_PREFETCH_SSE (x86_prefetch_sse)
221#define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)
222#define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK)
223#define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK)
224#define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK)
225#define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK)
226#define TARGET_SCHEDULE (x86_schedule & TUNEMASK)
227#define TARGET_USE_BT (x86_use_bt & TUNEMASK)
228#define TARGET_USE_INCDEC (x86_use_incdec & TUNEMASK)
229#define TARGET_PAD_RETURNS (x86_pad_returns & TUNEMASK)
230
231#define ASSEMBLER_DIALECT (ix86_asm_dialect)
232
233#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
234#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
235 && (ix86_fpmath & FPMATH_387))
236
237#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
238#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
239#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
240#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
241
242#define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch))
243#define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch))
240#define TARGET_CMPXCHG16B (x86_cmpxchg16b & (1 << ix86_arch))
244#define TARGET_CMPXCHG16B (x86_cmpxchg16b)
241#define TARGET_XADD (x86_xadd & (1 << ix86_arch))
242
243#ifndef TARGET_64BIT_DEFAULT
244#define TARGET_64BIT_DEFAULT 0
245#endif
246#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
247#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
248#endif
249
250/* Once GDB has been enhanced to deal with functions without frame
251 pointers, we can change this to allow for elimination of
252 the frame pointer in leaf functions. */
253#define TARGET_DEFAULT 0
254
255/* This is not really a target flag, but is done this way so that
256 it's analogous to similar code for Mach-O on PowerPC. darwin.h
257 redefines this to 1. */
258#define TARGET_MACHO 0
259
260/* Subtargets may reset this to 1 in order to enable 96-bit long double
261 with the rounding mode forced to 53 bits. */
262#define TARGET_96_ROUND_53_LONG_DOUBLE 0
263
264/* Sometimes certain combinations of command options do not make
265 sense on a particular target machine. You can define a macro
266 `OVERRIDE_OPTIONS' to take account of this. This macro, if
267 defined, is executed once just after all the command options have
268 been parsed.
269
270 Don't use this macro to turn on various extra optimizations for
271 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
272
273#define OVERRIDE_OPTIONS override_options ()
274
275/* Define this to change the optimizations performed by default. */
276#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
277 optimization_options ((LEVEL), (SIZE))
278
279/* -march=native handling only makes sense with compiler running on
280 an x86 or x86_64 chip. If changing this condition, also change
281 the condition in driver-i386.c. */
282#if defined(__i386__) || defined(__x86_64__)
283/* In driver-i386.c. */
284extern const char *host_detect_local_cpu (int argc, const char **argv);
285#define EXTRA_SPEC_FUNCTIONS \
286 { "local_cpu_detect", host_detect_local_cpu },
287#define HAVE_LOCAL_CPU_DETECT
288#endif
289
290/* Support for configure-time defaults of some command line options.
291 The order here is important so that -march doesn't squash the
292 tune or cpu values. */
293#define OPTION_DEFAULT_SPECS \
294 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
295 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
296 {"arch", "%{!march=*:-march=%(VALUE)}"}
297
298/* Specs for the compiler proper */
299
300#ifndef CC1_CPU_SPEC
301#define CC1_CPU_SPEC_1 "\
302%{!mtune*: \
303%{m386:mtune=i386 \
304%n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \
305%{m486:-mtune=i486 \
306%n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \
307%{mpentium:-mtune=pentium \
308%n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \
309%{mpentiumpro:-mtune=pentiumpro \
310%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \
311%{mcpu=*:-mtune=%* \
312%n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \
313%<mcpu=* \
314%{mintel-syntax:-masm=intel \
315%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
316%{mno-intel-syntax:-masm=att \
317%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
318
319#ifndef HAVE_LOCAL_CPU_DETECT
320#define CC1_CPU_SPEC CC1_CPU_SPEC_1
321#else
322#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
323"%{march=native:%<march=native %:local_cpu_detect(arch) \
324 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
325%{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
326#endif
327#endif
328
329/* Target CPU builtins. */
330#define TARGET_CPU_CPP_BUILTINS() \
331 do \
332 { \
333 size_t arch_len = strlen (ix86_arch_string); \
334 size_t tune_len = strlen (ix86_tune_string); \
335 int last_arch_char = ix86_arch_string[arch_len - 1]; \
336 int last_tune_char = ix86_tune_string[tune_len - 1]; \
337 \
338 if (TARGET_64BIT) \
339 { \
340 builtin_assert ("cpu=x86_64"); \
341 builtin_assert ("machine=x86_64"); \
342 builtin_define ("__amd64"); \
343 builtin_define ("__amd64__"); \
344 builtin_define ("__x86_64"); \
345 builtin_define ("__x86_64__"); \
346 } \
347 else \
348 { \
349 builtin_assert ("cpu=i386"); \
350 builtin_assert ("machine=i386"); \
351 builtin_define_std ("i386"); \
352 } \
353 \
354 /* Built-ins based on -mtune= (or -march= if no \
355 -mtune= given). */ \
356 if (TARGET_386) \
357 builtin_define ("__tune_i386__"); \
358 else if (TARGET_486) \
359 builtin_define ("__tune_i486__"); \
360 else if (TARGET_PENTIUM) \
361 { \
362 builtin_define ("__tune_i586__"); \
363 builtin_define ("__tune_pentium__"); \
364 if (last_tune_char == 'x') \
365 builtin_define ("__tune_pentium_mmx__"); \
366 } \
367 else if (TARGET_PENTIUMPRO) \
368 { \
369 builtin_define ("__tune_i686__"); \
370 builtin_define ("__tune_pentiumpro__"); \
371 switch (last_tune_char) \
372 { \
373 case '3': \
374 builtin_define ("__tune_pentium3__"); \
375 /* FALLTHRU */ \
376 case '2': \
377 builtin_define ("__tune_pentium2__"); \
378 break; \
379 } \
380 } \
381 else if (TARGET_GEODE) \
382 { \
383 builtin_define ("__tune_geode__"); \
384 } \
385 else if (TARGET_K6) \
386 { \
387 builtin_define ("__tune_k6__"); \
388 if (last_tune_char == '2') \
389 builtin_define ("__tune_k6_2__"); \
390 else if (last_tune_char == '3') \
391 builtin_define ("__tune_k6_3__"); \
392 } \
393 else if (TARGET_ATHLON) \
394 { \
395 builtin_define ("__tune_athlon__"); \
396 /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \
397 if (last_tune_char != 'n' && last_tune_char != 'd') \
398 builtin_define ("__tune_athlon_sse__"); \
399 } \
400 else if (TARGET_K8) \
401 builtin_define ("__tune_k8__"); \
245#define TARGET_XADD (x86_xadd & (1 << ix86_arch))
246
247#ifndef TARGET_64BIT_DEFAULT
248#define TARGET_64BIT_DEFAULT 0
249#endif
250#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
251#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
252#endif
253
254/* Once GDB has been enhanced to deal with functions without frame
255 pointers, we can change this to allow for elimination of
256 the frame pointer in leaf functions. */
257#define TARGET_DEFAULT 0
258
259/* This is not really a target flag, but is done this way so that
260 it's analogous to similar code for Mach-O on PowerPC. darwin.h
261 redefines this to 1. */
262#define TARGET_MACHO 0
263
264/* Subtargets may reset this to 1 in order to enable 96-bit long double
265 with the rounding mode forced to 53 bits. */
266#define TARGET_96_ROUND_53_LONG_DOUBLE 0
267
268/* Sometimes certain combinations of command options do not make
269 sense on a particular target machine. You can define a macro
270 `OVERRIDE_OPTIONS' to take account of this. This macro, if
271 defined, is executed once just after all the command options have
272 been parsed.
273
274 Don't use this macro to turn on various extra optimizations for
275 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
276
277#define OVERRIDE_OPTIONS override_options ()
278
279/* Define this to change the optimizations performed by default. */
280#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
281 optimization_options ((LEVEL), (SIZE))
282
283/* -march=native handling only makes sense with compiler running on
284 an x86 or x86_64 chip. If changing this condition, also change
285 the condition in driver-i386.c. */
286#if defined(__i386__) || defined(__x86_64__)
287/* In driver-i386.c. */
288extern const char *host_detect_local_cpu (int argc, const char **argv);
289#define EXTRA_SPEC_FUNCTIONS \
290 { "local_cpu_detect", host_detect_local_cpu },
291#define HAVE_LOCAL_CPU_DETECT
292#endif
293
294/* Support for configure-time defaults of some command line options.
295 The order here is important so that -march doesn't squash the
296 tune or cpu values. */
297#define OPTION_DEFAULT_SPECS \
298 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
299 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
300 {"arch", "%{!march=*:-march=%(VALUE)}"}
301
302/* Specs for the compiler proper */
303
304#ifndef CC1_CPU_SPEC
305#define CC1_CPU_SPEC_1 "\
306%{!mtune*: \
307%{m386:mtune=i386 \
308%n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \
309%{m486:-mtune=i486 \
310%n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \
311%{mpentium:-mtune=pentium \
312%n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \
313%{mpentiumpro:-mtune=pentiumpro \
314%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \
315%{mcpu=*:-mtune=%* \
316%n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \
317%<mcpu=* \
318%{mintel-syntax:-masm=intel \
319%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
320%{mno-intel-syntax:-masm=att \
321%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
322
323#ifndef HAVE_LOCAL_CPU_DETECT
324#define CC1_CPU_SPEC CC1_CPU_SPEC_1
325#else
326#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
327"%{march=native:%<march=native %:local_cpu_detect(arch) \
328 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
329%{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
330#endif
331#endif
332
333/* Target CPU builtins. */
334#define TARGET_CPU_CPP_BUILTINS() \
335 do \
336 { \
337 size_t arch_len = strlen (ix86_arch_string); \
338 size_t tune_len = strlen (ix86_tune_string); \
339 int last_arch_char = ix86_arch_string[arch_len - 1]; \
340 int last_tune_char = ix86_tune_string[tune_len - 1]; \
341 \
342 if (TARGET_64BIT) \
343 { \
344 builtin_assert ("cpu=x86_64"); \
345 builtin_assert ("machine=x86_64"); \
346 builtin_define ("__amd64"); \
347 builtin_define ("__amd64__"); \
348 builtin_define ("__x86_64"); \
349 builtin_define ("__x86_64__"); \
350 } \
351 else \
352 { \
353 builtin_assert ("cpu=i386"); \
354 builtin_assert ("machine=i386"); \
355 builtin_define_std ("i386"); \
356 } \
357 \
358 /* Built-ins based on -mtune= (or -march= if no \
359 -mtune= given). */ \
360 if (TARGET_386) \
361 builtin_define ("__tune_i386__"); \
362 else if (TARGET_486) \
363 builtin_define ("__tune_i486__"); \
364 else if (TARGET_PENTIUM) \
365 { \
366 builtin_define ("__tune_i586__"); \
367 builtin_define ("__tune_pentium__"); \
368 if (last_tune_char == 'x') \
369 builtin_define ("__tune_pentium_mmx__"); \
370 } \
371 else if (TARGET_PENTIUMPRO) \
372 { \
373 builtin_define ("__tune_i686__"); \
374 builtin_define ("__tune_pentiumpro__"); \
375 switch (last_tune_char) \
376 { \
377 case '3': \
378 builtin_define ("__tune_pentium3__"); \
379 /* FALLTHRU */ \
380 case '2': \
381 builtin_define ("__tune_pentium2__"); \
382 break; \
383 } \
384 } \
385 else if (TARGET_GEODE) \
386 { \
387 builtin_define ("__tune_geode__"); \
388 } \
389 else if (TARGET_K6) \
390 { \
391 builtin_define ("__tune_k6__"); \
392 if (last_tune_char == '2') \
393 builtin_define ("__tune_k6_2__"); \
394 else if (last_tune_char == '3') \
395 builtin_define ("__tune_k6_3__"); \
396 } \
397 else if (TARGET_ATHLON) \
398 { \
399 builtin_define ("__tune_athlon__"); \
400 /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \
401 if (last_tune_char != 'n' && last_tune_char != 'd') \
402 builtin_define ("__tune_athlon_sse__"); \
403 } \
404 else if (TARGET_K8) \
405 builtin_define ("__tune_k8__"); \
406 else if (TARGET_AMDFAM10) \
407 builtin_define ("__tune_amdfam10__"); \
402 else if (TARGET_PENTIUM4) \
403 builtin_define ("__tune_pentium4__"); \
404 else if (TARGET_NOCONA) \
405 builtin_define ("__tune_nocona__"); \
406 else if (TARGET_CORE2) \
407 builtin_define ("__tune_core2__"); \
408 \
409 if (TARGET_MMX) \
410 builtin_define ("__MMX__"); \
411 if (TARGET_3DNOW) \
412 builtin_define ("__3dNOW__"); \
413 if (TARGET_3DNOW_A) \
414 builtin_define ("__3dNOW_A__"); \
415 if (TARGET_SSE) \
416 builtin_define ("__SSE__"); \
417 if (TARGET_SSE2) \
418 builtin_define ("__SSE2__"); \
419 if (TARGET_SSE3) \
420 builtin_define ("__SSE3__"); \
421 if (TARGET_SSSE3) \
422 builtin_define ("__SSSE3__"); \
408 else if (TARGET_PENTIUM4) \
409 builtin_define ("__tune_pentium4__"); \
410 else if (TARGET_NOCONA) \
411 builtin_define ("__tune_nocona__"); \
412 else if (TARGET_CORE2) \
413 builtin_define ("__tune_core2__"); \
414 \
415 if (TARGET_MMX) \
416 builtin_define ("__MMX__"); \
417 if (TARGET_3DNOW) \
418 builtin_define ("__3dNOW__"); \
419 if (TARGET_3DNOW_A) \
420 builtin_define ("__3dNOW_A__"); \
421 if (TARGET_SSE) \
422 builtin_define ("__SSE__"); \
423 if (TARGET_SSE2) \
424 builtin_define ("__SSE2__"); \
425 if (TARGET_SSE3) \
426 builtin_define ("__SSE3__"); \
427 if (TARGET_SSSE3) \
428 builtin_define ("__SSSE3__"); \
429 if (TARGET_SSE4A) \
430 builtin_define ("__SSE4A__"); \
423 if (TARGET_SSE_MATH && TARGET_SSE) \
424 builtin_define ("__SSE_MATH__"); \
425 if (TARGET_SSE_MATH && TARGET_SSE2) \
426 builtin_define ("__SSE2_MATH__"); \
427 \
428 /* Built-ins based on -march=. */ \
429 if (ix86_arch == PROCESSOR_I486) \
430 { \
431 builtin_define ("__i486"); \
432 builtin_define ("__i486__"); \
433 } \
434 else if (ix86_arch == PROCESSOR_PENTIUM) \
435 { \
436 builtin_define ("__i586"); \
437 builtin_define ("__i586__"); \
438 builtin_define ("__pentium"); \
439 builtin_define ("__pentium__"); \
440 if (last_arch_char == 'x') \
441 builtin_define ("__pentium_mmx__"); \
442 } \
443 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
444 { \
445 builtin_define ("__i686"); \
446 builtin_define ("__i686__"); \
447 builtin_define ("__pentiumpro"); \
448 builtin_define ("__pentiumpro__"); \
449 } \
450 else if (ix86_arch == PROCESSOR_GEODE) \
451 { \
452 builtin_define ("__geode"); \
453 builtin_define ("__geode__"); \
454 } \
455 else if (ix86_arch == PROCESSOR_K6) \
456 { \
457 \
458 builtin_define ("__k6"); \
459 builtin_define ("__k6__"); \
460 if (last_arch_char == '2') \
461 builtin_define ("__k6_2__"); \
462 else if (last_arch_char == '3') \
463 builtin_define ("__k6_3__"); \
464 } \
465 else if (ix86_arch == PROCESSOR_ATHLON) \
466 { \
467 builtin_define ("__athlon"); \
468 builtin_define ("__athlon__"); \
469 /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \
470 if (last_tune_char != 'n' && last_tune_char != 'd') \
471 builtin_define ("__athlon_sse__"); \
472 } \
473 else if (ix86_arch == PROCESSOR_K8) \
474 { \
475 builtin_define ("__k8"); \
476 builtin_define ("__k8__"); \
477 } \
431 if (TARGET_SSE_MATH && TARGET_SSE) \
432 builtin_define ("__SSE_MATH__"); \
433 if (TARGET_SSE_MATH && TARGET_SSE2) \
434 builtin_define ("__SSE2_MATH__"); \
435 \
436 /* Built-ins based on -march=. */ \
437 if (ix86_arch == PROCESSOR_I486) \
438 { \
439 builtin_define ("__i486"); \
440 builtin_define ("__i486__"); \
441 } \
442 else if (ix86_arch == PROCESSOR_PENTIUM) \
443 { \
444 builtin_define ("__i586"); \
445 builtin_define ("__i586__"); \
446 builtin_define ("__pentium"); \
447 builtin_define ("__pentium__"); \
448 if (last_arch_char == 'x') \
449 builtin_define ("__pentium_mmx__"); \
450 } \
451 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
452 { \
453 builtin_define ("__i686"); \
454 builtin_define ("__i686__"); \
455 builtin_define ("__pentiumpro"); \
456 builtin_define ("__pentiumpro__"); \
457 } \
458 else if (ix86_arch == PROCESSOR_GEODE) \
459 { \
460 builtin_define ("__geode"); \
461 builtin_define ("__geode__"); \
462 } \
463 else if (ix86_arch == PROCESSOR_K6) \
464 { \
465 \
466 builtin_define ("__k6"); \
467 builtin_define ("__k6__"); \
468 if (last_arch_char == '2') \
469 builtin_define ("__k6_2__"); \
470 else if (last_arch_char == '3') \
471 builtin_define ("__k6_3__"); \
472 } \
473 else if (ix86_arch == PROCESSOR_ATHLON) \
474 { \
475 builtin_define ("__athlon"); \
476 builtin_define ("__athlon__"); \
477 /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \
478 if (last_tune_char != 'n' && last_tune_char != 'd') \
479 builtin_define ("__athlon_sse__"); \
480 } \
481 else if (ix86_arch == PROCESSOR_K8) \
482 { \
483 builtin_define ("__k8"); \
484 builtin_define ("__k8__"); \
485 } \
486 else if (ix86_arch == PROCESSOR_AMDFAM10) \
487 { \
488 builtin_define ("__amdfam10"); \
489 builtin_define ("__amdfam10__"); \
490 } \
478 else if (ix86_arch == PROCESSOR_PENTIUM4) \
479 { \
480 builtin_define ("__pentium4"); \
481 builtin_define ("__pentium4__"); \
482 } \
483 else if (ix86_arch == PROCESSOR_NOCONA) \
484 { \
485 builtin_define ("__nocona"); \
486 builtin_define ("__nocona__"); \
487 } \
488 else if (ix86_arch == PROCESSOR_CORE2) \
489 { \
490 builtin_define ("__core2"); \
491 builtin_define ("__core2__"); \
492 } \
493 } \
494 while (0)
495
496#define TARGET_CPU_DEFAULT_i386 0
497#define TARGET_CPU_DEFAULT_i486 1
498#define TARGET_CPU_DEFAULT_pentium 2
499#define TARGET_CPU_DEFAULT_pentium_mmx 3
500#define TARGET_CPU_DEFAULT_pentiumpro 4
501#define TARGET_CPU_DEFAULT_pentium2 5
502#define TARGET_CPU_DEFAULT_pentium3 6
503#define TARGET_CPU_DEFAULT_pentium4 7
504#define TARGET_CPU_DEFAULT_geode 8
505#define TARGET_CPU_DEFAULT_k6 9
506#define TARGET_CPU_DEFAULT_k6_2 10
507#define TARGET_CPU_DEFAULT_k6_3 11
508#define TARGET_CPU_DEFAULT_athlon 12
509#define TARGET_CPU_DEFAULT_athlon_sse 13
510#define TARGET_CPU_DEFAULT_k8 14
511#define TARGET_CPU_DEFAULT_pentium_m 15
512#define TARGET_CPU_DEFAULT_prescott 16
513#define TARGET_CPU_DEFAULT_nocona 17
514#define TARGET_CPU_DEFAULT_core2 18
515#define TARGET_CPU_DEFAULT_generic 19
491 else if (ix86_arch == PROCESSOR_PENTIUM4) \
492 { \
493 builtin_define ("__pentium4"); \
494 builtin_define ("__pentium4__"); \
495 } \
496 else if (ix86_arch == PROCESSOR_NOCONA) \
497 { \
498 builtin_define ("__nocona"); \
499 builtin_define ("__nocona__"); \
500 } \
501 else if (ix86_arch == PROCESSOR_CORE2) \
502 { \
503 builtin_define ("__core2"); \
504 builtin_define ("__core2__"); \
505 } \
506 } \
507 while (0)
508
509#define TARGET_CPU_DEFAULT_i386 0
510#define TARGET_CPU_DEFAULT_i486 1
511#define TARGET_CPU_DEFAULT_pentium 2
512#define TARGET_CPU_DEFAULT_pentium_mmx 3
513#define TARGET_CPU_DEFAULT_pentiumpro 4
514#define TARGET_CPU_DEFAULT_pentium2 5
515#define TARGET_CPU_DEFAULT_pentium3 6
516#define TARGET_CPU_DEFAULT_pentium4 7
517#define TARGET_CPU_DEFAULT_geode 8
518#define TARGET_CPU_DEFAULT_k6 9
519#define TARGET_CPU_DEFAULT_k6_2 10
520#define TARGET_CPU_DEFAULT_k6_3 11
521#define TARGET_CPU_DEFAULT_athlon 12
522#define TARGET_CPU_DEFAULT_athlon_sse 13
523#define TARGET_CPU_DEFAULT_k8 14
524#define TARGET_CPU_DEFAULT_pentium_m 15
525#define TARGET_CPU_DEFAULT_prescott 16
526#define TARGET_CPU_DEFAULT_nocona 17
527#define TARGET_CPU_DEFAULT_core2 18
528#define TARGET_CPU_DEFAULT_generic 19
529#define TARGET_CPU_DEFAULT_amdfam10 20
516
517#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
518 "pentiumpro", "pentium2", "pentium3", \
519 "pentium4", "geode", "k6", "k6-2", "k6-3", \
520 "athlon", "athlon-4", "k8", \
521 "pentium-m", "prescott", "nocona", \
530
531#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
532 "pentiumpro", "pentium2", "pentium3", \
533 "pentium4", "geode", "k6", "k6-2", "k6-3", \
534 "athlon", "athlon-4", "k8", \
535 "pentium-m", "prescott", "nocona", \
522 "core2", "generic"}
536 "core2", "generic", "amdfam10"}
523
524#ifndef CC1_SPEC
525#define CC1_SPEC "%(cc1_cpu) "
526#endif
527
528/* This macro defines names of additional specifications to put in the
529 specs that can be used in various specifications like CC1_SPEC. Its
530 definition is an initializer with a subgrouping for each command option.
531
532 Each subgrouping contains a string constant, that defines the
533 specification name, and a string constant that used by the GCC driver
534 program.
535
536 Do not define this macro if it does not need to do anything. */
537
538#ifndef SUBTARGET_EXTRA_SPECS
539#define SUBTARGET_EXTRA_SPECS
540#endif
541
542#define EXTRA_SPECS \
543 { "cc1_cpu", CC1_CPU_SPEC }, \
544 SUBTARGET_EXTRA_SPECS
545
546/* target machine storage layout */
547
548#define LONG_DOUBLE_TYPE_SIZE 80
549
550/* Set the value of FLT_EVAL_METHOD in float.h. When using only the
551 FPU, assume that the fpcw is set to extended precision; when using
552 only SSE, rounding is correct; when using both SSE and the FPU,
553 the rounding precision is indeterminate, since either may be chosen
554 apparently at random. */
555#define TARGET_FLT_EVAL_METHOD \
556 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
557
558#define SHORT_TYPE_SIZE 16
559#define INT_TYPE_SIZE 32
560#define FLOAT_TYPE_SIZE 32
561#ifndef LONG_TYPE_SIZE
562#define LONG_TYPE_SIZE BITS_PER_WORD
563#endif
564#define DOUBLE_TYPE_SIZE 64
565#define LONG_LONG_TYPE_SIZE 64
566
567#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
568#define MAX_BITS_PER_WORD 64
569#else
570#define MAX_BITS_PER_WORD 32
571#endif
572
573/* Define this if most significant byte of a word is the lowest numbered. */
574/* That is true on the 80386. */
575
576#define BITS_BIG_ENDIAN 0
577
578/* Define this if most significant byte of a word is the lowest numbered. */
579/* That is not true on the 80386. */
580#define BYTES_BIG_ENDIAN 0
581
582/* Define this if most significant word of a multiword number is the lowest
583 numbered. */
584/* Not true for 80386 */
585#define WORDS_BIG_ENDIAN 0
586
587/* Width of a word, in units (bytes). */
588#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
589#ifdef IN_LIBGCC2
590#define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
591#else
592#define MIN_UNITS_PER_WORD 4
593#endif
594
595/* Allocation boundary (in *bits*) for storing arguments in argument list. */
596#define PARM_BOUNDARY BITS_PER_WORD
597
598/* Boundary (in *bits*) on which stack pointer should be aligned. */
599#define STACK_BOUNDARY BITS_PER_WORD
600
601/* Boundary (in *bits*) on which the stack pointer prefers to be
602 aligned; the compiler cannot rely on having this alignment. */
603#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
604
605/* As of July 2001, many runtimes do not align the stack properly when
606 entering main. This causes expand_main_function to forcibly align
607 the stack, which results in aligned frames for functions called from
608 main, though it does nothing for the alignment of main itself. */
609#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
610 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
611
612/* Minimum allocation boundary for the code of a function. */
613#define FUNCTION_BOUNDARY 8
614
615/* C++ stores the virtual bit in the lowest bit of function pointers. */
616#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
617
618/* Alignment of field after `int : 0' in a structure. */
619
620#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
621
622/* Minimum size in bits of the largest boundary to which any
623 and all fundamental data types supported by the hardware
624 might need to be aligned. No data type wants to be aligned
625 rounder than this.
626
627 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
628 and Pentium Pro XFmode values at 128 bit boundaries. */
629
630#define BIGGEST_ALIGNMENT 128
631
632/* Decide whether a variable of mode MODE should be 128 bit aligned. */
633#define ALIGN_MODE_128(MODE) \
634 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
635
636/* The published ABIs say that doubles should be aligned on word
637 boundaries, so lower the alignment for structure fields unless
638 -malign-double is set. */
639
640/* ??? Blah -- this macro is used directly by libobjc. Since it
641 supports no vector modes, cut out the complexity and fall back
642 on BIGGEST_FIELD_ALIGNMENT. */
643#ifdef IN_TARGET_LIBS
644#ifdef __x86_64__
645#define BIGGEST_FIELD_ALIGNMENT 128
646#else
647#define BIGGEST_FIELD_ALIGNMENT 32
648#endif
649#else
650#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
651 x86_field_alignment (FIELD, COMPUTED)
652#endif
653
654/* If defined, a C expression to compute the alignment given to a
655 constant that is being placed in memory. EXP is the constant
656 and ALIGN is the alignment that the object would ordinarily have.
657 The value of this macro is used instead of that alignment to align
658 the object.
659
660 If this macro is not defined, then ALIGN is used.
661
662 The typical use of this macro is to increase alignment for string
663 constants to be word aligned so that `strcpy' calls that copy
664 constants can be done inline. */
665
666#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
667
668/* If defined, a C expression to compute the alignment for a static
669 variable. TYPE is the data type, and ALIGN is the alignment that
670 the object would ordinarily have. The value of this macro is used
671 instead of that alignment to align the object.
672
673 If this macro is not defined, then ALIGN is used.
674
675 One use of this macro is to increase alignment of medium-size
676 data to make it all fit in fewer cache lines. Another is to
677 cause character arrays to be word-aligned so that `strcpy' calls
678 that copy constants to character arrays can be done inline. */
679
680#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
681
682/* If defined, a C expression to compute the alignment for a local
683 variable. TYPE is the data type, and ALIGN is the alignment that
684 the object would ordinarily have. The value of this macro is used
685 instead of that alignment to align the object.
686
687 If this macro is not defined, then ALIGN is used.
688
689 One use of this macro is to increase alignment of medium-size
690 data to make it all fit in fewer cache lines. */
691
692#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
693
694/* If defined, a C expression that gives the alignment boundary, in
695 bits, of an argument with the specified mode and type. If it is
696 not defined, `PARM_BOUNDARY' is used for all arguments. */
697
698#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
699 ix86_function_arg_boundary ((MODE), (TYPE))
700
701/* Set this nonzero if move instructions will actually fail to work
702 when given unaligned data. */
703#define STRICT_ALIGNMENT 0
704
705/* If bit field type is int, don't let it cross an int,
706 and give entire struct the alignment of an int. */
707/* Required on the 386 since it doesn't have bit-field insns. */
708#define PCC_BITFIELD_TYPE_MATTERS 1
709
710/* Standard register usage. */
711
712/* This processor has special stack-like registers. See reg-stack.c
713 for details. */
714
715#define STACK_REGS
716#define IS_STACK_MODE(MODE) \
717 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
718 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
719 || (MODE) == XFmode)
720
721/* Number of actual hardware registers.
722 The hardware registers are assigned numbers for the compiler
723 from 0 to just below FIRST_PSEUDO_REGISTER.
724 All registers that the compiler knows about must be given numbers,
725 even those that are not normally considered general registers.
726
727 In the 80386 we give the 8 general purpose registers the numbers 0-7.
728 We number the floating point registers 8-15.
729 Note that registers 0-7 can be accessed as a short or int,
730 while only 0-3 may be used with byte `mov' instructions.
731
732 Reg 16 does not correspond to any hardware register, but instead
733 appears in the RTL as an argument pointer prior to reload, and is
734 eliminated during reloading in favor of either the stack or frame
735 pointer. */
736
737#define FIRST_PSEUDO_REGISTER 53
738
739/* Number of hardware registers that go into the DWARF-2 unwind info.
740 If not defined, equals FIRST_PSEUDO_REGISTER. */
741
742#define DWARF_FRAME_REGISTERS 17
743
744/* 1 for registers that have pervasive standard uses
745 and are not available for the register allocator.
746 On the 80386, the stack pointer is such, as is the arg pointer.
747
748 The value is zero if the register is not fixed on either 32 or
749 64 bit targets, one if the register if fixed on both 32 and 64
750 bit targets, two if it is only fixed on 32bit targets and three
751 if its only fixed on 64bit targets.
752 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
753 */
754#define FIXED_REGISTERS \
755/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
756{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
757/*arg,flags,fpsr,dir,frame*/ \
758 1, 1, 1, 1, 1, \
759/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
760 0, 0, 0, 0, 0, 0, 0, 0, \
761/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
762 0, 0, 0, 0, 0, 0, 0, 0, \
763/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
764 2, 2, 2, 2, 2, 2, 2, 2, \
765/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
766 2, 2, 2, 2, 2, 2, 2, 2}
767
768
769/* 1 for registers not available across function calls.
770 These must include the FIXED_REGISTERS and also any
771 registers that can be used without being saved.
772 The latter must include the registers where values are returned
773 and the register where structure-value addresses are passed.
774 Aside from that, you can include as many other registers as you like.
775
776 The value is zero if the register is not call used on either 32 or
777 64 bit targets, one if the register if call used on both 32 and 64
778 bit targets, two if it is only call used on 32bit targets and three
779 if its only call used on 64bit targets.
780 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
781*/
782#define CALL_USED_REGISTERS \
783/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
784{ 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
785/*arg,flags,fpsr,dir,frame*/ \
786 1, 1, 1, 1, 1, \
787/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
788 1, 1, 1, 1, 1, 1, 1, 1, \
789/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
790 1, 1, 1, 1, 1, 1, 1, 1, \
791/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
792 1, 1, 1, 1, 2, 2, 2, 2, \
793/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
794 1, 1, 1, 1, 1, 1, 1, 1} \
795
796/* Order in which to allocate registers. Each register must be
797 listed once, even those in FIXED_REGISTERS. List frame pointer
798 late and fixed registers last. Note that, in general, we prefer
799 registers listed in CALL_USED_REGISTERS, keeping the others
800 available for storage of persistent values.
801
802 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
803 so this is just empty initializer for array. */
804
805#define REG_ALLOC_ORDER \
806{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
807 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
808 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
809 48, 49, 50, 51, 52 }
810
811/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
812 to be rearranged based on a particular function. When using sse math,
813 we want to allocate SSE before x87 registers and vice vera. */
814
815#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
816
817
818/* Macro to conditionally modify fixed_regs/call_used_regs. */
819#define CONDITIONAL_REGISTER_USAGE \
820do { \
821 int i; \
822 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
823 { \
824 if (fixed_regs[i] > 1) \
825 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
826 if (call_used_regs[i] > 1) \
827 call_used_regs[i] = (call_used_regs[i] \
828 == (TARGET_64BIT ? 3 : 2)); \
829 } \
830 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
831 { \
832 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
833 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
834 } \
835 if (! TARGET_MMX) \
836 { \
837 int i; \
838 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
839 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
840 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
841 } \
842 if (! TARGET_SSE) \
843 { \
844 int i; \
845 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
846 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
847 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
848 } \
849 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
850 { \
851 int i; \
852 HARD_REG_SET x; \
853 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
854 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
855 if (TEST_HARD_REG_BIT (x, i)) \
856 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
857 } \
858 if (! TARGET_64BIT) \
859 { \
860 int i; \
861 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
862 reg_names[i] = ""; \
863 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
864 reg_names[i] = ""; \
865 } \
866 } while (0)
867
868/* Return number of consecutive hard regs needed starting at reg REGNO
869 to hold something of mode MODE.
870 This is ordinarily the length in words of a value of mode MODE
871 but can be less for certain modes in special long registers.
872
873 Actually there are no two word move instructions for consecutive
874 registers. And only registers 0-3 may have mov byte instructions
875 applied to them.
876 */
877
878#define HARD_REGNO_NREGS(REGNO, MODE) \
879 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
880 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
881 : ((MODE) == XFmode \
882 ? (TARGET_64BIT ? 2 : 3) \
883 : (MODE) == XCmode \
884 ? (TARGET_64BIT ? 4 : 6) \
885 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
886
887#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
888 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
889 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
890 ? 0 \
891 : ((MODE) == XFmode || (MODE) == XCmode)) \
892 : 0)
893
894#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
895
896#define VALID_SSE2_REG_MODE(MODE) \
897 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
898 || (MODE) == V2DImode || (MODE) == DFmode)
899
900#define VALID_SSE_REG_MODE(MODE) \
901 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
902 || (MODE) == SFmode || (MODE) == TFmode)
903
904#define VALID_MMX_REG_MODE_3DNOW(MODE) \
905 ((MODE) == V2SFmode || (MODE) == SFmode)
906
907#define VALID_MMX_REG_MODE(MODE) \
908 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
909 || (MODE) == V2SImode || (MODE) == SImode)
910
911/* ??? No autovectorization into MMX or 3DNOW until we can reliably
912 place emms and femms instructions. */
913#define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
914
915#define VALID_FP_MODE_P(MODE) \
916 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
917 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
918
919#define VALID_INT_MODE_P(MODE) \
920 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
921 || (MODE) == DImode \
922 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
923 || (MODE) == CDImode \
924 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
925 || (MODE) == TFmode || (MODE) == TCmode)))
926
927/* Return true for modes passed in SSE registers. */
928#define SSE_REG_MODE_P(MODE) \
929 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
930 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
931 || (MODE) == V4SFmode || (MODE) == V4SImode)
932
933/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
934
935#define HARD_REGNO_MODE_OK(REGNO, MODE) \
936 ix86_hard_regno_mode_ok ((REGNO), (MODE))
937
938/* Value is 1 if it is a good idea to tie two pseudo registers
939 when one has mode MODE1 and one has mode MODE2.
940 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
941 for any hard reg, then this must be 0 for correct output. */
942
943#define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
944
945/* It is possible to write patterns to move flags; but until someone
946 does it, */
947#define AVOID_CCMODE_COPIES
948
949/* Specify the modes required to caller save a given hard regno.
950 We do this on i386 to prevent flags from being saved at all.
951
952 Kill any attempts to combine saving of modes. */
953
954#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
955 (CC_REGNO_P (REGNO) ? VOIDmode \
956 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
957 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
958 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
959 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
960 : (MODE))
961/* Specify the registers used for certain standard purposes.
962 The values of these macros are register numbers. */
963
964/* on the 386 the pc register is %eip, and is not usable as a general
965 register. The ordinary mov instructions won't work */
966/* #define PC_REGNUM */
967
968/* Register to use for pushing function arguments. */
969#define STACK_POINTER_REGNUM 7
970
971/* Base register for access to local variables of the function. */
972#define HARD_FRAME_POINTER_REGNUM 6
973
974/* Base register for access to local variables of the function. */
975#define FRAME_POINTER_REGNUM 20
976
977/* First floating point reg */
978#define FIRST_FLOAT_REG 8
979
980/* First & last stack-like regs */
981#define FIRST_STACK_REG FIRST_FLOAT_REG
982#define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
983
984#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
985#define LAST_SSE_REG (FIRST_SSE_REG + 7)
986
987#define FIRST_MMX_REG (LAST_SSE_REG + 1)
988#define LAST_MMX_REG (FIRST_MMX_REG + 7)
989
990#define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
991#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
992
993#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
994#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
995
996/* Value should be nonzero if functions must have frame pointers.
997 Zero means the frame pointer need not be set up (and parms
998 may be accessed via the stack pointer) in functions that seem suitable.
999 This is computed in `reload', in reload1.c. */
1000#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1001
1002/* Override this in other tm.h files to cope with various OS lossage
1003 requiring a frame pointer. */
1004#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1005#define SUBTARGET_FRAME_POINTER_REQUIRED 0
1006#endif
1007
1008/* Make sure we can access arbitrary call frames. */
1009#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1010
1011/* Base register for access to arguments of the function. */
1012#define ARG_POINTER_REGNUM 16
1013
1014/* Register in which static-chain is passed to a function.
1015 We do use ECX as static chain register for 32 bit ABI. On the
1016 64bit ABI, ECX is an argument register, so we use R10 instead. */
1017#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1018
1019/* Register to hold the addressing base for position independent
1020 code access to data items. We don't use PIC pointer for 64bit
1021 mode. Define the regnum to dummy value to prevent gcc from
1022 pessimizing code dealing with EBX.
1023
1024 To avoid clobbering a call-saved register unnecessarily, we renumber
1025 the pic register when possible. The change is visible after the
1026 prologue has been emitted. */
1027
1028#define REAL_PIC_OFFSET_TABLE_REGNUM 3
1029
1030#define PIC_OFFSET_TABLE_REGNUM \
1031 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1032 || !flag_pic ? INVALID_REGNUM \
1033 : reload_completed ? REGNO (pic_offset_table_rtx) \
1034 : REAL_PIC_OFFSET_TABLE_REGNUM)
1035
1036#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1037
1038/* A C expression which can inhibit the returning of certain function
1039 values in registers, based on the type of value. A nonzero value
1040 says to return the function value in memory, just as large
1041 structures are always returned. Here TYPE will be a C expression
1042 of type `tree', representing the data type of the value.
1043
1044 Note that values of mode `BLKmode' must be explicitly handled by
1045 this macro. Also, the option `-fpcc-struct-return' takes effect
1046 regardless of this macro. On most systems, it is possible to
1047 leave the macro undefined; this causes a default definition to be
1048 used, whose value is the constant 1 for `BLKmode' values, and 0
1049 otherwise.
1050
1051 Do not use this macro to indicate that structures and unions
1052 should always be returned in memory. You should instead use
1053 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1054
1055#define RETURN_IN_MEMORY(TYPE) \
1056 ix86_return_in_memory (TYPE)
1057
1058/* This is overridden by <cygwin.h>. */
1059#define MS_AGGREGATE_RETURN 0
1060
1061/* This is overridden by <netware.h>. */
1062#define KEEP_AGGREGATE_RETURN_POINTER 0
1063
1064/* Define the classes of registers for register constraints in the
1065 machine description. Also define ranges of constants.
1066
1067 One of the classes must always be named ALL_REGS and include all hard regs.
1068 If there is more than one class, another class must be named NO_REGS
1069 and contain no registers.
1070
1071 The name GENERAL_REGS must be the name of a class (or an alias for
1072 another name such as ALL_REGS). This is the class of registers
1073 that is allowed by "g" or "r" in a register constraint.
1074 Also, registers outside this class are allocated only when
1075 instructions express preferences for them.
1076
1077 The classes must be numbered in nondecreasing order; that is,
1078 a larger-numbered class must never be contained completely
1079 in a smaller-numbered class.
1080
1081 For any two classes, it is very desirable that there be another
1082 class that represents their union.
1083
1084 It might seem that class BREG is unnecessary, since no useful 386
1085 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1086 and the "b" register constraint is useful in asms for syscalls.
1087
1088 The flags and fpsr registers are in no class. */
1089
1090enum reg_class
1091{
1092 NO_REGS,
1093 AREG, DREG, CREG, BREG, SIREG, DIREG,
1094 AD_REGS, /* %eax/%edx for DImode */
1095 Q_REGS, /* %eax %ebx %ecx %edx */
1096 NON_Q_REGS, /* %esi %edi %ebp %esp */
1097 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1098 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1099 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1100 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1101 FLOAT_REGS,
1102 SSE_REGS,
1103 MMX_REGS,
1104 FP_TOP_SSE_REGS,
1105 FP_SECOND_SSE_REGS,
1106 FLOAT_SSE_REGS,
1107 FLOAT_INT_REGS,
1108 INT_SSE_REGS,
1109 FLOAT_INT_SSE_REGS,
1110 ALL_REGS, LIM_REG_CLASSES
1111};
1112
1113#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1114
1115#define INTEGER_CLASS_P(CLASS) \
1116 reg_class_subset_p ((CLASS), GENERAL_REGS)
1117#define FLOAT_CLASS_P(CLASS) \
1118 reg_class_subset_p ((CLASS), FLOAT_REGS)
1119#define SSE_CLASS_P(CLASS) \
1120 ((CLASS) == SSE_REGS)
1121#define MMX_CLASS_P(CLASS) \
1122 ((CLASS) == MMX_REGS)
1123#define MAYBE_INTEGER_CLASS_P(CLASS) \
1124 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1125#define MAYBE_FLOAT_CLASS_P(CLASS) \
1126 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1127#define MAYBE_SSE_CLASS_P(CLASS) \
1128 reg_classes_intersect_p (SSE_REGS, (CLASS))
1129#define MAYBE_MMX_CLASS_P(CLASS) \
1130 reg_classes_intersect_p (MMX_REGS, (CLASS))
1131
1132#define Q_CLASS_P(CLASS) \
1133 reg_class_subset_p ((CLASS), Q_REGS)
1134
1135/* Give names of register classes as strings for dump file. */
1136
1137#define REG_CLASS_NAMES \
1138{ "NO_REGS", \
1139 "AREG", "DREG", "CREG", "BREG", \
1140 "SIREG", "DIREG", \
1141 "AD_REGS", \
1142 "Q_REGS", "NON_Q_REGS", \
1143 "INDEX_REGS", \
1144 "LEGACY_REGS", \
1145 "GENERAL_REGS", \
1146 "FP_TOP_REG", "FP_SECOND_REG", \
1147 "FLOAT_REGS", \
1148 "SSE_REGS", \
1149 "MMX_REGS", \
1150 "FP_TOP_SSE_REGS", \
1151 "FP_SECOND_SSE_REGS", \
1152 "FLOAT_SSE_REGS", \
1153 "FLOAT_INT_REGS", \
1154 "INT_SSE_REGS", \
1155 "FLOAT_INT_SSE_REGS", \
1156 "ALL_REGS" }
1157
1158/* Define which registers fit in which classes.
1159 This is an initializer for a vector of HARD_REG_SET
1160 of length N_REG_CLASSES. */
1161
1162#define REG_CLASS_CONTENTS \
1163{ { 0x00, 0x0 }, \
1164 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1165 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1166 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1167 { 0x03, 0x0 }, /* AD_REGS */ \
1168 { 0x0f, 0x0 }, /* Q_REGS */ \
1169 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1170 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1171 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1172 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1173 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1174 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1175{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1176{ 0xe0000000, 0x1f }, /* MMX_REGS */ \
1177{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1178{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1179{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1180 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1181{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1182{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1183{ 0xffffffff,0x1fffff } \
1184}
1185
1186/* The same information, inverted:
1187 Return the class number of the smallest class containing
1188 reg number REGNO. This could be a conditional expression
1189 or could index an array. */
1190
1191#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1192
1193/* When defined, the compiler allows registers explicitly used in the
1194 rtl to be used as spill registers but prevents the compiler from
1195 extending the lifetime of these registers. */
1196
1197#define SMALL_REGISTER_CLASSES 1
1198
1199#define QI_REG_P(X) \
1200 (REG_P (X) && REGNO (X) < 4)
1201
1202#define GENERAL_REGNO_P(N) \
1203 ((N) < 8 || REX_INT_REGNO_P (N))
1204
1205#define GENERAL_REG_P(X) \
1206 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1207
1208#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1209
1210#define NON_QI_REG_P(X) \
1211 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1212
1213#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1214#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1215
1216#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1217#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1218#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1219#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1220
1221#define SSE_REGNO_P(N) \
1222 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1223 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1224
1225#define REX_SSE_REGNO_P(N) \
1226 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)
1227
1228#define SSE_REGNO(N) \
1229 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1230#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1231
1232#define SSE_FLOAT_MODE_P(MODE) \
1233 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1234
1235#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1236#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1237
1238#define STACK_REG_P(XOP) \
1239 (REG_P (XOP) && \
1240 REGNO (XOP) >= FIRST_STACK_REG && \
1241 REGNO (XOP) <= LAST_STACK_REG)
1242
1243#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1244
1245#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1246
1247#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1248#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1249
1250/* The class value for index registers, and the one for base regs. */
1251
1252#define INDEX_REG_CLASS INDEX_REGS
1253#define BASE_REG_CLASS GENERAL_REGS
1254
1255/* Place additional restrictions on the register class to use when it
1256 is necessary to be able to hold a value of mode MODE in a reload
1257 register for which class CLASS would ordinarily be used. */
1258
1259#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1260 ((MODE) == QImode && !TARGET_64BIT \
1261 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1262 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1263 ? Q_REGS : (CLASS))
1264
1265/* Given an rtx X being reloaded into a reg required to be
1266 in class CLASS, return the class of reg to actually use.
1267 In general this is just CLASS; but on some machines
1268 in some cases it is preferable to use a more restrictive class.
1269 On the 80386 series, we prevent floating constants from being
1270 reloaded into floating registers (since no move-insn can do that)
1271 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1272
1273/* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1274 QImode must go into class Q_REGS.
1275 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1276 movdf to do mem-to-mem moves through integer regs. */
1277
1278#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1279 ix86_preferred_reload_class ((X), (CLASS))
1280
1281/* Discourage putting floating-point values in SSE registers unless
1282 SSE math is being used, and likewise for the 387 registers. */
1283
1284#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1285 ix86_preferred_output_reload_class ((X), (CLASS))
1286
1287/* If we are copying between general and FP registers, we need a memory
1288 location. The same is true for SSE and MMX registers. */
1289#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1290 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1291
1292/* QImode spills from non-QI registers need a scratch. This does not
1293 happen often -- the only example so far requires an uninitialized
1294 pseudo. */
1295
1296#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1297 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1298 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1299 ? Q_REGS : NO_REGS)
1300
1301/* Return the maximum number of consecutive registers
1302 needed to represent mode MODE in a register of class CLASS. */
1303/* On the 80386, this is the size of MODE in words,
1304 except in the FP regs, where a single reg is always enough. */
1305#define CLASS_MAX_NREGS(CLASS, MODE) \
1306 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1307 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1308 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1309 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1310
1311/* A C expression whose value is nonzero if pseudos that have been
1312 assigned to registers of class CLASS would likely be spilled
1313 because registers of CLASS are needed for spill registers.
1314
1315 The default value of this macro returns 1 if CLASS has exactly one
1316 register and zero otherwise. On most machines, this default
1317 should be used. Only define this macro to some other expression
1318 if pseudo allocated by `local-alloc.c' end up in memory because
1319 their hard registers were needed for spill registers. If this
1320 macro returns nonzero for those classes, those pseudos will only
1321 be allocated by `global.c', which knows how to reallocate the
1322 pseudo to another register. If there would not be another
1323 register available for reallocation, you should not change the
1324 definition of this macro since the only effect of such a
1325 definition would be to slow down register allocation. */
1326
1327#define CLASS_LIKELY_SPILLED_P(CLASS) \
1328 (((CLASS) == AREG) \
1329 || ((CLASS) == DREG) \
1330 || ((CLASS) == CREG) \
1331 || ((CLASS) == BREG) \
1332 || ((CLASS) == AD_REGS) \
1333 || ((CLASS) == SIREG) \
1334 || ((CLASS) == DIREG) \
1335 || ((CLASS) == FP_TOP_REG) \
1336 || ((CLASS) == FP_SECOND_REG))
1337
1338/* Return a class of registers that cannot change FROM mode to TO mode. */
1339
1340#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1341 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1342
1343/* Stack layout; function entry, exit and calling. */
1344
1345/* Define this if pushing a word on the stack
1346 makes the stack pointer a smaller address. */
1347#define STACK_GROWS_DOWNWARD
1348
1349/* Define this to nonzero if the nominal address of the stack frame
1350 is at the high-address end of the local variables;
1351 that is, each additional local variable allocated
1352 goes at a more negative offset in the frame. */
1353#define FRAME_GROWS_DOWNWARD 1
1354
1355/* Offset within stack frame to start allocating local variables at.
1356 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1357 first local allocated. Otherwise, it is the offset to the BEGINNING
1358 of the first local allocated. */
1359#define STARTING_FRAME_OFFSET 0
1360
1361/* If we generate an insn to push BYTES bytes,
1362 this says how many the stack pointer really advances by.
1363 On 386, we have pushw instruction that decrements by exactly 2 no
1364 matter what the position was, there is no pushb.
1365 But as CIE data alignment factor on this arch is -4, we need to make
1366 sure all stack pointer adjustments are in multiple of 4.
1367
1368 For 64bit ABI we round up to 8 bytes.
1369 */
1370
1371#define PUSH_ROUNDING(BYTES) \
1372 (TARGET_64BIT \
1373 ? (((BYTES) + 7) & (-8)) \
1374 : (((BYTES) + 3) & (-4)))
1375
1376/* If defined, the maximum amount of space required for outgoing arguments will
1377 be computed and placed into the variable
1378 `current_function_outgoing_args_size'. No space will be pushed onto the
1379 stack for each call; instead, the function prologue should increase the stack
1380 frame size by this amount. */
1381
1382#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1383
1384/* If defined, a C expression whose value is nonzero when we want to use PUSH
1385 instructions to pass outgoing arguments. */
1386
1387#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1388
1389/* We want the stack and args grow in opposite directions, even if
1390 PUSH_ARGS is 0. */
1391#define PUSH_ARGS_REVERSED 1
1392
1393/* Offset of first parameter from the argument pointer register value. */
1394#define FIRST_PARM_OFFSET(FNDECL) 0
1395
1396/* Define this macro if functions should assume that stack space has been
1397 allocated for arguments even when their values are passed in registers.
1398
1399 The value of this macro is the size, in bytes, of the area reserved for
1400 arguments passed in registers for the function represented by FNDECL.
1401
1402 This space can be allocated by the caller, or be a part of the
1403 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1404 which. */
1405#define REG_PARM_STACK_SPACE(FNDECL) 0
1406
1407/* Value is the number of bytes of arguments automatically
1408 popped when returning from a subroutine call.
1409 FUNDECL is the declaration node of the function (as a tree),
1410 FUNTYPE is the data type of the function (as a tree),
1411 or for a library call it is an identifier node for the subroutine name.
1412 SIZE is the number of bytes of arguments passed on the stack.
1413
1414 On the 80386, the RTD insn may be used to pop them if the number
1415 of args is fixed, but if the number is variable then the caller
1416 must pop them all. RTD can't be used for library calls now
1417 because the library is compiled with the Unix compiler.
1418 Use of RTD is a selectable option, since it is incompatible with
1419 standard Unix calling sequences. If the option is not selected,
1420 the caller must always pop the args.
1421
1422 The attribute stdcall is equivalent to RTD on a per module basis. */
1423
1424#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1425 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1426
1427#define FUNCTION_VALUE_REGNO_P(N) \
1428 ix86_function_value_regno_p (N)
1429
1430/* Define how to find the value returned by a library function
1431 assuming the value has mode MODE. */
1432
1433#define LIBCALL_VALUE(MODE) \
1434 ix86_libcall_value (MODE)
1435
1436/* Define the size of the result block used for communication between
1437 untyped_call and untyped_return. The block contains a DImode value
1438 followed by the block used by fnsave and frstor. */
1439
1440#define APPLY_RESULT_SIZE (8+108)
1441
1442/* 1 if N is a possible register number for function argument passing. */
1443#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1444
1445/* Define a data type for recording info about an argument list
1446 during the scan of that argument list. This data type should
1447 hold all necessary information about the function itself
1448 and about the args processed so far, enough to enable macros
1449 such as FUNCTION_ARG to determine where the next arg should go. */
1450
1451typedef struct ix86_args {
1452 int words; /* # words passed so far */
1453 int nregs; /* # registers available for passing */
1454 int regno; /* next available register number */
1455 int fastcall; /* fastcall calling convention is used */
1456 int sse_words; /* # sse words passed so far */
1457 int sse_nregs; /* # sse registers available for passing */
1458 int warn_sse; /* True when we want to warn about SSE ABI. */
1459 int warn_mmx; /* True when we want to warn about MMX ABI. */
1460 int sse_regno; /* next available sse register number */
1461 int mmx_words; /* # mmx words passed so far */
1462 int mmx_nregs; /* # mmx registers available for passing */
1463 int mmx_regno; /* next available mmx register number */
1464 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1465 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1466 be passed in SSE registers. Otherwise 0. */
1467} CUMULATIVE_ARGS;
1468
1469/* Initialize a variable CUM of type CUMULATIVE_ARGS
1470 for a call to a function whose data type is FNTYPE.
1471 For a library call, FNTYPE is 0. */
1472
1473#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1474 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1475
1476/* Update the data in CUM to advance over an argument
1477 of mode MODE and data type TYPE.
1478 (TYPE is null for libcalls where that information may not be available.) */
1479
1480#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1481 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1482
1483/* Define where to put the arguments to a function.
1484 Value is zero to push the argument on the stack,
1485 or a hard register in which to store the argument.
1486
1487 MODE is the argument's machine mode.
1488 TYPE is the data type of the argument (as a tree).
1489 This is null for libcalls where that information may
1490 not be available.
1491 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1492 the preceding args and about the function being called.
1493 NAMED is nonzero if this argument is a named parameter
1494 (otherwise it is an extra parameter matching an ellipsis). */
1495
1496#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1497 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1498
1499/* Implement `va_start' for varargs and stdarg. */
1500#define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1501 ix86_va_start (VALIST, NEXTARG)
1502
1503#define TARGET_ASM_FILE_END ix86_file_end
1504#define NEED_INDICATE_EXEC_STACK 0
1505
1506/* Output assembler code to FILE to increment profiler label # LABELNO
1507 for profiling a function entry. */
1508
1509#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1510
1511#define MCOUNT_NAME "_mcount"
1512
1513#define PROFILE_COUNT_REGISTER "edx"
1514
1515/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1516 the stack pointer does not matter. The value is tested only in
1517 functions that have frame pointers.
1518 No definition is equivalent to always zero. */
1519/* Note on the 386 it might be more efficient not to define this since
1520 we have to restore it ourselves from the frame pointer, in order to
1521 use pop */
1522
1523#define EXIT_IGNORE_STACK 1
1524
1525/* Output assembler code for a block containing the constant parts
1526 of a trampoline, leaving space for the variable parts. */
1527
1528/* On the 386, the trampoline contains two instructions:
1529 mov #STATIC,ecx
1530 jmp FUNCTION
1531 The trampoline is generated entirely at runtime. The operand of JMP
1532 is the address of FUNCTION relative to the instruction following the
1533 JMP (which is 5 bytes long). */
1534
1535/* Length in units of the trampoline for entering a nested function. */
1536
1537#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1538
1539/* Emit RTL insns to initialize the variable parts of a trampoline.
1540 FNADDR is an RTX for the address of the function's pure code.
1541 CXT is an RTX for the static chain value for the function. */
1542
1543#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1544 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1545
1546/* Definitions for register eliminations.
1547
1548 This is an array of structures. Each structure initializes one pair
1549 of eliminable registers. The "from" register number is given first,
1550 followed by "to". Eliminations of the same "from" register are listed
1551 in order of preference.
1552
1553 There are two registers that can always be eliminated on the i386.
1554 The frame pointer and the arg pointer can be replaced by either the
1555 hard frame pointer or to the stack pointer, depending upon the
1556 circumstances. The hard frame pointer is not used before reload and
1557 so it is not eligible for elimination. */
1558
1559#define ELIMINABLE_REGS \
1560{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1561 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1562 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1563 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1564
1565/* Given FROM and TO register numbers, say whether this elimination is
1566 allowed. Frame pointer elimination is automatically handled.
1567
1568 All other eliminations are valid. */
1569
1570#define CAN_ELIMINATE(FROM, TO) \
1571 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1572
1573/* Define the offset between two registers, one to be eliminated, and the other
1574 its replacement, at the start of a routine. */
1575
1576#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1577 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1578
1579/* Addressing modes, and classification of registers for them. */
1580
1581/* Macros to check register numbers against specific register classes. */
1582
1583/* These assume that REGNO is a hard or pseudo reg number.
1584 They give nonzero only if REGNO is a hard reg of the suitable class
1585 or a pseudo reg currently allocated to a suitable hard reg.
1586 Since they use reg_renumber, they are safe only once reg_renumber
1587 has been allocated, which happens in local-alloc.c. */
1588
1589#define REGNO_OK_FOR_INDEX_P(REGNO) \
1590 ((REGNO) < STACK_POINTER_REGNUM \
1591 || (REGNO >= FIRST_REX_INT_REG \
1592 && (REGNO) <= LAST_REX_INT_REG) \
1593 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1594 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1595 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1596
1597#define REGNO_OK_FOR_BASE_P(REGNO) \
1598 ((REGNO) <= STACK_POINTER_REGNUM \
1599 || (REGNO) == ARG_POINTER_REGNUM \
1600 || (REGNO) == FRAME_POINTER_REGNUM \
1601 || (REGNO >= FIRST_REX_INT_REG \
1602 && (REGNO) <= LAST_REX_INT_REG) \
1603 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1604 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1605 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1606
1607#define REGNO_OK_FOR_SIREG_P(REGNO) \
1608 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1609#define REGNO_OK_FOR_DIREG_P(REGNO) \
1610 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1611
1612/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1613 and check its validity for a certain class.
1614 We have two alternate definitions for each of them.
1615 The usual definition accepts all pseudo regs; the other rejects
1616 them unless they have been allocated suitable hard regs.
1617 The symbol REG_OK_STRICT causes the latter definition to be used.
1618
1619 Most source files want to accept pseudo regs in the hope that
1620 they will get allocated to the class that the insn wants them to be in.
1621 Source files for reload pass need to be strict.
1622 After reload, it makes no difference, since pseudo regs have
1623 been eliminated by then. */
1624
1625
1626/* Non strict versions, pseudos are ok. */
1627#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1628 (REGNO (X) < STACK_POINTER_REGNUM \
1629 || (REGNO (X) >= FIRST_REX_INT_REG \
1630 && REGNO (X) <= LAST_REX_INT_REG) \
1631 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1632
1633#define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1634 (REGNO (X) <= STACK_POINTER_REGNUM \
1635 || REGNO (X) == ARG_POINTER_REGNUM \
1636 || REGNO (X) == FRAME_POINTER_REGNUM \
1637 || (REGNO (X) >= FIRST_REX_INT_REG \
1638 && REGNO (X) <= LAST_REX_INT_REG) \
1639 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1640
1641/* Strict versions, hard registers only */
1642#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1643#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1644
1645#ifndef REG_OK_STRICT
1646#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1647#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1648
1649#else
1650#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1651#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1652#endif
1653
1654/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1655 that is a valid memory address for an instruction.
1656 The MODE argument is the machine mode for the MEM expression
1657 that wants to use this address.
1658
1659 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1660 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1661
1662 See legitimize_pic_address in i386.c for details as to what
1663 constitutes a legitimate address when -fpic is used. */
1664
1665#define MAX_REGS_PER_ADDRESS 2
1666
1667#define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1668
1669/* Nonzero if the constant value X is a legitimate general operand.
1670 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1671
1672#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1673
1674#ifdef REG_OK_STRICT
1675#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1676do { \
1677 if (legitimate_address_p ((MODE), (X), 1)) \
1678 goto ADDR; \
1679} while (0)
1680
1681#else
1682#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1683do { \
1684 if (legitimate_address_p ((MODE), (X), 0)) \
1685 goto ADDR; \
1686} while (0)
1687
1688#endif
1689
1690/* If defined, a C expression to determine the base term of address X.
1691 This macro is used in only one place: `find_base_term' in alias.c.
1692
1693 It is always safe for this macro to not be defined. It exists so
1694 that alias analysis can understand machine-dependent addresses.
1695
1696 The typical use of this macro is to handle addresses containing
1697 a label_ref or symbol_ref within an UNSPEC. */
1698
1699#define FIND_BASE_TERM(X) ix86_find_base_term (X)
1700
1701/* Try machine-dependent ways of modifying an illegitimate address
1702 to be legitimate. If we find one, return the new, valid address.
1703 This macro is used in only one place: `memory_address' in explow.c.
1704
1705 OLDX is the address as it was before break_out_memory_refs was called.
1706 In some cases it is useful to look at this to decide what needs to be done.
1707
1708 MODE and WIN are passed so that this macro can use
1709 GO_IF_LEGITIMATE_ADDRESS.
1710
1711 It is always safe for this macro to do nothing. It exists to recognize
1712 opportunities to optimize the output.
1713
1714 For the 80386, we handle X+REG by loading X into a register R and
1715 using R+REG. R will go in a general reg and indexing will be used.
1716 However, if REG is a broken-out memory address or multiplication,
1717 nothing needs to be done because REG can certainly go in a general reg.
1718
1719 When -fpic is used, special handling is needed for symbolic references.
1720 See comments by legitimize_pic_address in i386.c for details. */
1721
1722#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1723do { \
1724 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1725 if (memory_address_p ((MODE), (X))) \
1726 goto WIN; \
1727} while (0)
1728
1729#define REWRITE_ADDRESS(X) rewrite_address (X)
1730
1731/* Nonzero if the constant value X is a legitimate general operand
1732 when generating PIC code. It is given that flag_pic is on and
1733 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1734
1735#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1736
1737#define SYMBOLIC_CONST(X) \
1738 (GET_CODE (X) == SYMBOL_REF \
1739 || GET_CODE (X) == LABEL_REF \
1740 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1741
1742/* Go to LABEL if ADDR (a legitimate address expression)
1743 has an effect that depends on the machine mode it is used for.
1744 On the 80386, only postdecrement and postincrement address depend thus
1745 (the amount of decrement or increment being the length of the operand). */
1746#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1747do { \
1748 if (GET_CODE (ADDR) == POST_INC \
1749 || GET_CODE (ADDR) == POST_DEC) \
1750 goto LABEL; \
1751} while (0)
1752
1753/* Max number of args passed in registers. If this is more than 3, we will
1754 have problems with ebx (register #4), since it is a caller save register and
1755 is also used as the pic register in ELF. So for now, don't allow more than
1756 3 registers to be passed in registers. */
1757
1758#define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1759
1760#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1761
1762#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1763
1764
1765/* Specify the machine mode that this machine uses
1766 for the index in the tablejump instruction. */
1767#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
1768
1769/* Define this as 1 if `char' should by default be signed; else as 0. */
1770#define DEFAULT_SIGNED_CHAR 1
1771
1772/* Number of bytes moved into a data cache for a single prefetch operation. */
1773#define PREFETCH_BLOCK ix86_cost->prefetch_block
1774
1775/* Number of prefetch operations that can be done in parallel. */
1776#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
1777
1778/* Max number of bytes we can move from memory to memory
1779 in one reasonably fast instruction. */
1780#define MOVE_MAX 16
1781
1782/* MOVE_MAX_PIECES is the number of bytes at a time which we can
1783 move efficiently, as opposed to MOVE_MAX which is the maximum
1784 number of bytes we can move with a single instruction. */
1785#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1786
1787/* If a memory-to-memory move would take MOVE_RATIO or more simple
1788 move-instruction pairs, we will do a movmem or libcall instead.
1789 Increasing the value will always make code faster, but eventually
1790 incurs high cost in increased code size.
1791
1792 If you don't define this, a reasonable default is used. */
1793
1794#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1795
1796/* If a clear memory operation would take CLEAR_RATIO or more simple
1797 move-instruction sequences, we will do a clrmem or libcall instead. */
1798
1799#define CLEAR_RATIO (optimize_size ? 2 \
1800 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
1801
1802/* Define if shifts truncate the shift count
1803 which implies one can omit a sign-extension or zero-extension
1804 of a shift count. */
1805/* On i386, shifts do truncate the count. But bit opcodes don't. */
1806
1807/* #define SHIFT_COUNT_TRUNCATED */
1808
1809/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1810 is done just by pretending it is already truncated. */
1811#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1812
1813/* A macro to update M and UNSIGNEDP when an object whose type is
1814 TYPE and which has the specified mode and signedness is to be
1815 stored in a register. This macro is only called when TYPE is a
1816 scalar type.
1817
1818 On i386 it is sometimes useful to promote HImode and QImode
1819 quantities to SImode. The choice depends on target type. */
1820
1821#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1822do { \
1823 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1824 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1825 (MODE) = SImode; \
1826} while (0)
1827
1828/* Specify the machine mode that pointers have.
1829 After generation of rtl, the compiler makes no further distinction
1830 between pointers and any other objects of this machine mode. */
1831#define Pmode (TARGET_64BIT ? DImode : SImode)
1832
1833/* A function address in a call instruction
1834 is a byte address (for indexing purposes)
1835 so give the MEM rtx a byte's mode. */
1836#define FUNCTION_MODE QImode
1837
1838/* A C expression for the cost of moving data from a register in class FROM to
1839 one in class TO. The classes are expressed using the enumeration values
1840 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1841 interpreted relative to that.
1842
1843 It is not required that the cost always equal 2 when FROM is the same as TO;
1844 on some machines it is expensive to move between registers if they are not
1845 general registers. */
1846
1847#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1848 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1849
1850/* A C expression for the cost of moving data of mode M between a
1851 register and memory. A value of 2 is the default; this cost is
1852 relative to those in `REGISTER_MOVE_COST'.
1853
1854 If moving between registers and memory is more expensive than
1855 between two registers, you should define this macro to express the
1856 relative cost. */
1857
1858#define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1859 ix86_memory_move_cost ((MODE), (CLASS), (IN))
1860
1861/* A C expression for the cost of a branch instruction. A value of 1
1862 is the default; other values are interpreted relative to that. */
1863
1864#define BRANCH_COST ix86_branch_cost
1865
1866/* Define this macro as a C expression which is nonzero if accessing
1867 less than a word of memory (i.e. a `char' or a `short') is no
1868 faster than accessing a word of memory, i.e., if such access
1869 require more than one instruction or if there is no difference in
1870 cost between byte and (aligned) word loads.
1871
1872 When this macro is not defined, the compiler will access a field by
1873 finding the smallest containing object; when it is defined, a
1874 fullword load will be used if alignment permits. Unless bytes
1875 accesses are faster than word accesses, using word accesses is
1876 preferable since it may eliminate subsequent memory access if
1877 subsequent accesses occur to other fields in the same word of the
1878 structure, but to different bytes. */
1879
1880#define SLOW_BYTE_ACCESS 0
1881
1882/* Nonzero if access to memory by shorts is slow and undesirable. */
1883#define SLOW_SHORT_ACCESS 0
1884
1885/* Define this macro to be the value 1 if unaligned accesses have a
1886 cost many times greater than aligned accesses, for example if they
1887 are emulated in a trap handler.
1888
1889 When this macro is nonzero, the compiler will act as if
1890 `STRICT_ALIGNMENT' were nonzero when generating code for block
1891 moves. This can cause significantly more instructions to be
1892 produced. Therefore, do not set this macro nonzero if unaligned
1893 accesses only add a cycle or two to the time for a memory access.
1894
1895 If the value of this macro is always zero, it need not be defined. */
1896
1897/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1898
1899/* Define this macro if it is as good or better to call a constant
1900 function address than to call an address kept in a register.
1901
1902 Desirable on the 386 because a CALL with a constant address is
1903 faster than one with a register address. */
1904
1905#define NO_FUNCTION_CSE
1906
1907/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1908 return the mode to be used for the comparison.
1909
1910 For floating-point equality comparisons, CCFPEQmode should be used.
1911 VOIDmode should be used in all other cases.
1912
1913 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1914 possible, to allow for more combinations. */
1915
1916#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1917
1918/* Return nonzero if MODE implies a floating point inequality can be
1919 reversed. */
1920
1921#define REVERSIBLE_CC_MODE(MODE) 1
1922
1923/* A C expression whose value is reversed condition code of the CODE for
1924 comparison done in CC_MODE mode. */
1925#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1926
1927
1928/* Control the assembler format that we output, to the extent
1929 this does not vary between assemblers. */
1930
1931/* How to refer to registers in assembler output.
1932 This sequence is indexed by compiler's hard-register-number (see above). */
1933
1934/* In order to refer to the first 8 regs as 32 bit regs, prefix an "e".
1935 For non floating point regs, the following are the HImode names.
1936
1937 For float regs, the stack top is sometimes referred to as "%st(0)"
1938 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
1939
1940#define HI_REGISTER_NAMES \
1941{"ax","dx","cx","bx","si","di","bp","sp", \
1942 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1943 "argp", "flags", "fpsr", "dirflag", "frame", \
1944 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1945 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
1946 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1947 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
1948
1949#define REGISTER_NAMES HI_REGISTER_NAMES
1950
1951/* Table of additional register names to use in user input. */
1952
1953#define ADDITIONAL_REGISTER_NAMES \
1954{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
1955 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
1956 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
1957 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
1958 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
1959 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
1960
1961/* Note we are omitting these since currently I don't know how
1962to get gcc to use these, since they want the same but different
1963number as al, and ax.
1964*/
1965
1966#define QI_REGISTER_NAMES \
1967{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
1968
1969/* These parallel the array above, and can be used to access bits 8:15
1970 of regs 0 through 3. */
1971
1972#define QI_HIGH_REGISTER_NAMES \
1973{"ah", "dh", "ch", "bh", }
1974
1975/* How to renumber registers for dbx and gdb. */
1976
1977#define DBX_REGISTER_NUMBER(N) \
1978 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
1979
1980extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
1981extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
1982extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
1983
1984/* Before the prologue, RA is at 0(%esp). */
1985#define INCOMING_RETURN_ADDR_RTX \
1986 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1987
1988/* After the prologue, RA is at -4(AP) in the current frame. */
1989#define RETURN_ADDR_RTX(COUNT, FRAME) \
1990 ((COUNT) == 0 \
1991 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
1992 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
1993
1994/* PC is dbx register 8; let's use that column for RA. */
1995#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
1996
1997/* Before the prologue, the top of the frame is at 4(%esp). */
1998#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
1999
2000/* Describe how we implement __builtin_eh_return. */
2001#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2002#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2003
2004
2005/* Select a format to encode pointers in exception handling data. CODE
2006 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2007 true if the symbol may be affected by dynamic relocations.
2008
2009 ??? All x86 object file formats are capable of representing this.
2010 After all, the relocation needed is the same as for the call insn.
2011 Whether or not a particular assembler allows us to enter such, I
2012 guess we'll have to see. */
2013#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2014 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2015
2016/* This is how to output an insn to push a register on the stack.
2017 It need not be very fast code. */
2018
2019#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2020do { \
2021 if (TARGET_64BIT) \
2022 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2023 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2024 else \
2025 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2026} while (0)
2027
2028/* This is how to output an insn to pop a register from the stack.
2029 It need not be very fast code. */
2030
2031#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2032do { \
2033 if (TARGET_64BIT) \
2034 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2035 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2036 else \
2037 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2038} while (0)
2039
2040/* This is how to output an element of a case-vector that is absolute. */
2041
2042#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2043 ix86_output_addr_vec_elt ((FILE), (VALUE))
2044
2045/* This is how to output an element of a case-vector that is relative. */
2046
2047#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2048 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2049
2050/* Under some conditions we need jump tables in the text section,
2051 because the assembler cannot handle label differences between
2052 sections. This is the case for x86_64 on Mach-O for example. */
2053
2054#define JUMP_TABLES_IN_TEXT_SECTION \
2055 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2056 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2057
2058/* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2059 and switch back. For x86 we do this only to save a few bytes that
2060 would otherwise be unused in the text section. */
2061#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2062 asm (SECTION_OP "\n\t" \
2063 "call " USER_LABEL_PREFIX #FUNC "\n" \
2064 TEXT_SECTION_ASM_OP);
2065
2066/* Print operand X (an rtx) in assembler syntax to file FILE.
2067 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2068 Effect of various CODE letters is described in i386.c near
2069 print_operand function. */
2070
2071#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2072 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2073
2074#define PRINT_OPERAND(FILE, X, CODE) \
2075 print_operand ((FILE), (X), (CODE))
2076
2077#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2078 print_operand_address ((FILE), (ADDR))
2079
2080#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2081do { \
2082 if (! output_addr_const_extra (FILE, (X))) \
2083 goto FAIL; \
2084} while (0);
2085
2086/* a letter which is not needed by the normal asm syntax, which
2087 we can use for operand syntax in the extended asm */
2088
2089#define ASM_OPERAND_LETTER '#'
2090#define RET return ""
2091#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
2092
2093/* Which processor to schedule for. The cpu attribute defines a list that
2094 mirrors this list, so changes to i386.md must be made at the same time. */
2095
2096enum processor_type
2097{
2098 PROCESSOR_I386, /* 80386 */
2099 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2100 PROCESSOR_PENTIUM,
2101 PROCESSOR_PENTIUMPRO,
2102 PROCESSOR_GEODE,
2103 PROCESSOR_K6,
2104 PROCESSOR_ATHLON,
2105 PROCESSOR_PENTIUM4,
2106 PROCESSOR_K8,
2107 PROCESSOR_NOCONA,
2108 PROCESSOR_CORE2,
2109 PROCESSOR_GENERIC32,
2110 PROCESSOR_GENERIC64,
537
538#ifndef CC1_SPEC
539#define CC1_SPEC "%(cc1_cpu) "
540#endif
541
542/* This macro defines names of additional specifications to put in the
543 specs that can be used in various specifications like CC1_SPEC. Its
544 definition is an initializer with a subgrouping for each command option.
545
546 Each subgrouping contains a string constant, that defines the
547 specification name, and a string constant that used by the GCC driver
548 program.
549
550 Do not define this macro if it does not need to do anything. */
551
552#ifndef SUBTARGET_EXTRA_SPECS
553#define SUBTARGET_EXTRA_SPECS
554#endif
555
556#define EXTRA_SPECS \
557 { "cc1_cpu", CC1_CPU_SPEC }, \
558 SUBTARGET_EXTRA_SPECS
559
560/* target machine storage layout */
561
562#define LONG_DOUBLE_TYPE_SIZE 80
563
564/* Set the value of FLT_EVAL_METHOD in float.h. When using only the
565 FPU, assume that the fpcw is set to extended precision; when using
566 only SSE, rounding is correct; when using both SSE and the FPU,
567 the rounding precision is indeterminate, since either may be chosen
568 apparently at random. */
569#define TARGET_FLT_EVAL_METHOD \
570 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
571
572#define SHORT_TYPE_SIZE 16
573#define INT_TYPE_SIZE 32
574#define FLOAT_TYPE_SIZE 32
575#ifndef LONG_TYPE_SIZE
576#define LONG_TYPE_SIZE BITS_PER_WORD
577#endif
578#define DOUBLE_TYPE_SIZE 64
579#define LONG_LONG_TYPE_SIZE 64
580
581#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
582#define MAX_BITS_PER_WORD 64
583#else
584#define MAX_BITS_PER_WORD 32
585#endif
586
587/* Define this if most significant byte of a word is the lowest numbered. */
588/* That is true on the 80386. */
589
590#define BITS_BIG_ENDIAN 0
591
592/* Define this if most significant byte of a word is the lowest numbered. */
593/* That is not true on the 80386. */
594#define BYTES_BIG_ENDIAN 0
595
596/* Define this if most significant word of a multiword number is the lowest
597 numbered. */
598/* Not true for 80386 */
599#define WORDS_BIG_ENDIAN 0
600
601/* Width of a word, in units (bytes). */
602#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
603#ifdef IN_LIBGCC2
604#define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
605#else
606#define MIN_UNITS_PER_WORD 4
607#endif
608
609/* Allocation boundary (in *bits*) for storing arguments in argument list. */
610#define PARM_BOUNDARY BITS_PER_WORD
611
612/* Boundary (in *bits*) on which stack pointer should be aligned. */
613#define STACK_BOUNDARY BITS_PER_WORD
614
615/* Boundary (in *bits*) on which the stack pointer prefers to be
616 aligned; the compiler cannot rely on having this alignment. */
617#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
618
619/* As of July 2001, many runtimes do not align the stack properly when
620 entering main. This causes expand_main_function to forcibly align
621 the stack, which results in aligned frames for functions called from
622 main, though it does nothing for the alignment of main itself. */
623#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
624 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
625
626/* Minimum allocation boundary for the code of a function. */
627#define FUNCTION_BOUNDARY 8
628
629/* C++ stores the virtual bit in the lowest bit of function pointers. */
630#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
631
632/* Alignment of field after `int : 0' in a structure. */
633
634#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
635
636/* Minimum size in bits of the largest boundary to which any
637 and all fundamental data types supported by the hardware
638 might need to be aligned. No data type wants to be aligned
639 rounder than this.
640
641 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
642 and Pentium Pro XFmode values at 128 bit boundaries. */
643
644#define BIGGEST_ALIGNMENT 128
645
646/* Decide whether a variable of mode MODE should be 128 bit aligned. */
647#define ALIGN_MODE_128(MODE) \
648 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
649
650/* The published ABIs say that doubles should be aligned on word
651 boundaries, so lower the alignment for structure fields unless
652 -malign-double is set. */
653
654/* ??? Blah -- this macro is used directly by libobjc. Since it
655 supports no vector modes, cut out the complexity and fall back
656 on BIGGEST_FIELD_ALIGNMENT. */
657#ifdef IN_TARGET_LIBS
658#ifdef __x86_64__
659#define BIGGEST_FIELD_ALIGNMENT 128
660#else
661#define BIGGEST_FIELD_ALIGNMENT 32
662#endif
663#else
664#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
665 x86_field_alignment (FIELD, COMPUTED)
666#endif
667
668/* If defined, a C expression to compute the alignment given to a
669 constant that is being placed in memory. EXP is the constant
670 and ALIGN is the alignment that the object would ordinarily have.
671 The value of this macro is used instead of that alignment to align
672 the object.
673
674 If this macro is not defined, then ALIGN is used.
675
676 The typical use of this macro is to increase alignment for string
677 constants to be word aligned so that `strcpy' calls that copy
678 constants can be done inline. */
679
680#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
681
682/* If defined, a C expression to compute the alignment for a static
683 variable. TYPE is the data type, and ALIGN is the alignment that
684 the object would ordinarily have. The value of this macro is used
685 instead of that alignment to align the object.
686
687 If this macro is not defined, then ALIGN is used.
688
689 One use of this macro is to increase alignment of medium-size
690 data to make it all fit in fewer cache lines. Another is to
691 cause character arrays to be word-aligned so that `strcpy' calls
692 that copy constants to character arrays can be done inline. */
693
694#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
695
696/* If defined, a C expression to compute the alignment for a local
697 variable. TYPE is the data type, and ALIGN is the alignment that
698 the object would ordinarily have. The value of this macro is used
699 instead of that alignment to align the object.
700
701 If this macro is not defined, then ALIGN is used.
702
703 One use of this macro is to increase alignment of medium-size
704 data to make it all fit in fewer cache lines. */
705
706#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
707
708/* If defined, a C expression that gives the alignment boundary, in
709 bits, of an argument with the specified mode and type. If it is
710 not defined, `PARM_BOUNDARY' is used for all arguments. */
711
712#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
713 ix86_function_arg_boundary ((MODE), (TYPE))
714
715/* Set this nonzero if move instructions will actually fail to work
716 when given unaligned data. */
717#define STRICT_ALIGNMENT 0
718
719/* If bit field type is int, don't let it cross an int,
720 and give entire struct the alignment of an int. */
721/* Required on the 386 since it doesn't have bit-field insns. */
722#define PCC_BITFIELD_TYPE_MATTERS 1
723
724/* Standard register usage. */
725
726/* This processor has special stack-like registers. See reg-stack.c
727 for details. */
728
729#define STACK_REGS
730#define IS_STACK_MODE(MODE) \
731 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
732 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
733 || (MODE) == XFmode)
734
735/* Number of actual hardware registers.
736 The hardware registers are assigned numbers for the compiler
737 from 0 to just below FIRST_PSEUDO_REGISTER.
738 All registers that the compiler knows about must be given numbers,
739 even those that are not normally considered general registers.
740
741 In the 80386 we give the 8 general purpose registers the numbers 0-7.
742 We number the floating point registers 8-15.
743 Note that registers 0-7 can be accessed as a short or int,
744 while only 0-3 may be used with byte `mov' instructions.
745
746 Reg 16 does not correspond to any hardware register, but instead
747 appears in the RTL as an argument pointer prior to reload, and is
748 eliminated during reloading in favor of either the stack or frame
749 pointer. */
750
751#define FIRST_PSEUDO_REGISTER 53
752
753/* Number of hardware registers that go into the DWARF-2 unwind info.
754 If not defined, equals FIRST_PSEUDO_REGISTER. */
755
756#define DWARF_FRAME_REGISTERS 17
757
758/* 1 for registers that have pervasive standard uses
759 and are not available for the register allocator.
760 On the 80386, the stack pointer is such, as is the arg pointer.
761
762 The value is zero if the register is not fixed on either 32 or
763 64 bit targets, one if the register if fixed on both 32 and 64
764 bit targets, two if it is only fixed on 32bit targets and three
765 if its only fixed on 64bit targets.
766 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
767 */
768#define FIXED_REGISTERS \
769/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
770{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
771/*arg,flags,fpsr,dir,frame*/ \
772 1, 1, 1, 1, 1, \
773/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
774 0, 0, 0, 0, 0, 0, 0, 0, \
775/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
776 0, 0, 0, 0, 0, 0, 0, 0, \
777/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
778 2, 2, 2, 2, 2, 2, 2, 2, \
779/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
780 2, 2, 2, 2, 2, 2, 2, 2}
781
782
783/* 1 for registers not available across function calls.
784 These must include the FIXED_REGISTERS and also any
785 registers that can be used without being saved.
786 The latter must include the registers where values are returned
787 and the register where structure-value addresses are passed.
788 Aside from that, you can include as many other registers as you like.
789
790 The value is zero if the register is not call used on either 32 or
791 64 bit targets, one if the register if call used on both 32 and 64
792 bit targets, two if it is only call used on 32bit targets and three
793 if its only call used on 64bit targets.
794 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
795*/
796#define CALL_USED_REGISTERS \
797/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
798{ 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
799/*arg,flags,fpsr,dir,frame*/ \
800 1, 1, 1, 1, 1, \
801/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
802 1, 1, 1, 1, 1, 1, 1, 1, \
803/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
804 1, 1, 1, 1, 1, 1, 1, 1, \
805/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
806 1, 1, 1, 1, 2, 2, 2, 2, \
807/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
808 1, 1, 1, 1, 1, 1, 1, 1} \
809
810/* Order in which to allocate registers. Each register must be
811 listed once, even those in FIXED_REGISTERS. List frame pointer
812 late and fixed registers last. Note that, in general, we prefer
813 registers listed in CALL_USED_REGISTERS, keeping the others
814 available for storage of persistent values.
815
816 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
817 so this is just empty initializer for array. */
818
819#define REG_ALLOC_ORDER \
820{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
821 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
822 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
823 48, 49, 50, 51, 52 }
824
825/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
826 to be rearranged based on a particular function. When using sse math,
827 we want to allocate SSE before x87 registers and vice vera. */
828
829#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
830
831
832/* Macro to conditionally modify fixed_regs/call_used_regs. */
833#define CONDITIONAL_REGISTER_USAGE \
834do { \
835 int i; \
836 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
837 { \
838 if (fixed_regs[i] > 1) \
839 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
840 if (call_used_regs[i] > 1) \
841 call_used_regs[i] = (call_used_regs[i] \
842 == (TARGET_64BIT ? 3 : 2)); \
843 } \
844 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
845 { \
846 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
847 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
848 } \
849 if (! TARGET_MMX) \
850 { \
851 int i; \
852 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
853 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
854 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
855 } \
856 if (! TARGET_SSE) \
857 { \
858 int i; \
859 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
860 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
861 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
862 } \
863 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
864 { \
865 int i; \
866 HARD_REG_SET x; \
867 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
868 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
869 if (TEST_HARD_REG_BIT (x, i)) \
870 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
871 } \
872 if (! TARGET_64BIT) \
873 { \
874 int i; \
875 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
876 reg_names[i] = ""; \
877 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
878 reg_names[i] = ""; \
879 } \
880 } while (0)
881
882/* Return number of consecutive hard regs needed starting at reg REGNO
883 to hold something of mode MODE.
884 This is ordinarily the length in words of a value of mode MODE
885 but can be less for certain modes in special long registers.
886
887 Actually there are no two word move instructions for consecutive
888 registers. And only registers 0-3 may have mov byte instructions
889 applied to them.
890 */
891
892#define HARD_REGNO_NREGS(REGNO, MODE) \
893 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
894 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
895 : ((MODE) == XFmode \
896 ? (TARGET_64BIT ? 2 : 3) \
897 : (MODE) == XCmode \
898 ? (TARGET_64BIT ? 4 : 6) \
899 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
900
901#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
902 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
903 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
904 ? 0 \
905 : ((MODE) == XFmode || (MODE) == XCmode)) \
906 : 0)
907
908#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
909
910#define VALID_SSE2_REG_MODE(MODE) \
911 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
912 || (MODE) == V2DImode || (MODE) == DFmode)
913
914#define VALID_SSE_REG_MODE(MODE) \
915 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
916 || (MODE) == SFmode || (MODE) == TFmode)
917
918#define VALID_MMX_REG_MODE_3DNOW(MODE) \
919 ((MODE) == V2SFmode || (MODE) == SFmode)
920
921#define VALID_MMX_REG_MODE(MODE) \
922 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
923 || (MODE) == V2SImode || (MODE) == SImode)
924
925/* ??? No autovectorization into MMX or 3DNOW until we can reliably
926 place emms and femms instructions. */
927#define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
928
929#define VALID_FP_MODE_P(MODE) \
930 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
931 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
932
933#define VALID_INT_MODE_P(MODE) \
934 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
935 || (MODE) == DImode \
936 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
937 || (MODE) == CDImode \
938 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
939 || (MODE) == TFmode || (MODE) == TCmode)))
940
941/* Return true for modes passed in SSE registers. */
942#define SSE_REG_MODE_P(MODE) \
943 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
944 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
945 || (MODE) == V4SFmode || (MODE) == V4SImode)
946
947/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
948
949#define HARD_REGNO_MODE_OK(REGNO, MODE) \
950 ix86_hard_regno_mode_ok ((REGNO), (MODE))
951
952/* Value is 1 if it is a good idea to tie two pseudo registers
953 when one has mode MODE1 and one has mode MODE2.
954 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
955 for any hard reg, then this must be 0 for correct output. */
956
957#define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
958
959/* It is possible to write patterns to move flags; but until someone
960 does it, */
961#define AVOID_CCMODE_COPIES
962
963/* Specify the modes required to caller save a given hard regno.
964 We do this on i386 to prevent flags from being saved at all.
965
966 Kill any attempts to combine saving of modes. */
967
968#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
969 (CC_REGNO_P (REGNO) ? VOIDmode \
970 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
971 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
972 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
973 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
974 : (MODE))
975/* Specify the registers used for certain standard purposes.
976 The values of these macros are register numbers. */
977
978/* on the 386 the pc register is %eip, and is not usable as a general
979 register. The ordinary mov instructions won't work */
980/* #define PC_REGNUM */
981
982/* Register to use for pushing function arguments. */
983#define STACK_POINTER_REGNUM 7
984
985/* Base register for access to local variables of the function. */
986#define HARD_FRAME_POINTER_REGNUM 6
987
988/* Base register for access to local variables of the function. */
989#define FRAME_POINTER_REGNUM 20
990
991/* First floating point reg */
992#define FIRST_FLOAT_REG 8
993
994/* First & last stack-like regs */
995#define FIRST_STACK_REG FIRST_FLOAT_REG
996#define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
997
998#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
999#define LAST_SSE_REG (FIRST_SSE_REG + 7)
1000
1001#define FIRST_MMX_REG (LAST_SSE_REG + 1)
1002#define LAST_MMX_REG (FIRST_MMX_REG + 7)
1003
1004#define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1005#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1006
1007#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1008#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1009
1010/* Value should be nonzero if functions must have frame pointers.
1011 Zero means the frame pointer need not be set up (and parms
1012 may be accessed via the stack pointer) in functions that seem suitable.
1013 This is computed in `reload', in reload1.c. */
1014#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1015
1016/* Override this in other tm.h files to cope with various OS lossage
1017 requiring a frame pointer. */
1018#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1019#define SUBTARGET_FRAME_POINTER_REQUIRED 0
1020#endif
1021
1022/* Make sure we can access arbitrary call frames. */
1023#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1024
1025/* Base register for access to arguments of the function. */
1026#define ARG_POINTER_REGNUM 16
1027
1028/* Register in which static-chain is passed to a function.
1029 We do use ECX as static chain register for 32 bit ABI. On the
1030 64bit ABI, ECX is an argument register, so we use R10 instead. */
1031#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1032
1033/* Register to hold the addressing base for position independent
1034 code access to data items. We don't use PIC pointer for 64bit
1035 mode. Define the regnum to dummy value to prevent gcc from
1036 pessimizing code dealing with EBX.
1037
1038 To avoid clobbering a call-saved register unnecessarily, we renumber
1039 the pic register when possible. The change is visible after the
1040 prologue has been emitted. */
1041
1042#define REAL_PIC_OFFSET_TABLE_REGNUM 3
1043
1044#define PIC_OFFSET_TABLE_REGNUM \
1045 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1046 || !flag_pic ? INVALID_REGNUM \
1047 : reload_completed ? REGNO (pic_offset_table_rtx) \
1048 : REAL_PIC_OFFSET_TABLE_REGNUM)
1049
1050#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1051
1052/* A C expression which can inhibit the returning of certain function
1053 values in registers, based on the type of value. A nonzero value
1054 says to return the function value in memory, just as large
1055 structures are always returned. Here TYPE will be a C expression
1056 of type `tree', representing the data type of the value.
1057
1058 Note that values of mode `BLKmode' must be explicitly handled by
1059 this macro. Also, the option `-fpcc-struct-return' takes effect
1060 regardless of this macro. On most systems, it is possible to
1061 leave the macro undefined; this causes a default definition to be
1062 used, whose value is the constant 1 for `BLKmode' values, and 0
1063 otherwise.
1064
1065 Do not use this macro to indicate that structures and unions
1066 should always be returned in memory. You should instead use
1067 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1068
1069#define RETURN_IN_MEMORY(TYPE) \
1070 ix86_return_in_memory (TYPE)
1071
1072/* This is overridden by <cygwin.h>. */
1073#define MS_AGGREGATE_RETURN 0
1074
1075/* This is overridden by <netware.h>. */
1076#define KEEP_AGGREGATE_RETURN_POINTER 0
1077
1078/* Define the classes of registers for register constraints in the
1079 machine description. Also define ranges of constants.
1080
1081 One of the classes must always be named ALL_REGS and include all hard regs.
1082 If there is more than one class, another class must be named NO_REGS
1083 and contain no registers.
1084
1085 The name GENERAL_REGS must be the name of a class (or an alias for
1086 another name such as ALL_REGS). This is the class of registers
1087 that is allowed by "g" or "r" in a register constraint.
1088 Also, registers outside this class are allocated only when
1089 instructions express preferences for them.
1090
1091 The classes must be numbered in nondecreasing order; that is,
1092 a larger-numbered class must never be contained completely
1093 in a smaller-numbered class.
1094
1095 For any two classes, it is very desirable that there be another
1096 class that represents their union.
1097
1098 It might seem that class BREG is unnecessary, since no useful 386
1099 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1100 and the "b" register constraint is useful in asms for syscalls.
1101
1102 The flags and fpsr registers are in no class. */
1103
1104enum reg_class
1105{
1106 NO_REGS,
1107 AREG, DREG, CREG, BREG, SIREG, DIREG,
1108 AD_REGS, /* %eax/%edx for DImode */
1109 Q_REGS, /* %eax %ebx %ecx %edx */
1110 NON_Q_REGS, /* %esi %edi %ebp %esp */
1111 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1112 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1113 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1114 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1115 FLOAT_REGS,
1116 SSE_REGS,
1117 MMX_REGS,
1118 FP_TOP_SSE_REGS,
1119 FP_SECOND_SSE_REGS,
1120 FLOAT_SSE_REGS,
1121 FLOAT_INT_REGS,
1122 INT_SSE_REGS,
1123 FLOAT_INT_SSE_REGS,
1124 ALL_REGS, LIM_REG_CLASSES
1125};
1126
1127#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1128
1129#define INTEGER_CLASS_P(CLASS) \
1130 reg_class_subset_p ((CLASS), GENERAL_REGS)
1131#define FLOAT_CLASS_P(CLASS) \
1132 reg_class_subset_p ((CLASS), FLOAT_REGS)
1133#define SSE_CLASS_P(CLASS) \
1134 ((CLASS) == SSE_REGS)
1135#define MMX_CLASS_P(CLASS) \
1136 ((CLASS) == MMX_REGS)
1137#define MAYBE_INTEGER_CLASS_P(CLASS) \
1138 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1139#define MAYBE_FLOAT_CLASS_P(CLASS) \
1140 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1141#define MAYBE_SSE_CLASS_P(CLASS) \
1142 reg_classes_intersect_p (SSE_REGS, (CLASS))
1143#define MAYBE_MMX_CLASS_P(CLASS) \
1144 reg_classes_intersect_p (MMX_REGS, (CLASS))
1145
1146#define Q_CLASS_P(CLASS) \
1147 reg_class_subset_p ((CLASS), Q_REGS)
1148
1149/* Give names of register classes as strings for dump file. */
1150
1151#define REG_CLASS_NAMES \
1152{ "NO_REGS", \
1153 "AREG", "DREG", "CREG", "BREG", \
1154 "SIREG", "DIREG", \
1155 "AD_REGS", \
1156 "Q_REGS", "NON_Q_REGS", \
1157 "INDEX_REGS", \
1158 "LEGACY_REGS", \
1159 "GENERAL_REGS", \
1160 "FP_TOP_REG", "FP_SECOND_REG", \
1161 "FLOAT_REGS", \
1162 "SSE_REGS", \
1163 "MMX_REGS", \
1164 "FP_TOP_SSE_REGS", \
1165 "FP_SECOND_SSE_REGS", \
1166 "FLOAT_SSE_REGS", \
1167 "FLOAT_INT_REGS", \
1168 "INT_SSE_REGS", \
1169 "FLOAT_INT_SSE_REGS", \
1170 "ALL_REGS" }
1171
1172/* Define which registers fit in which classes.
1173 This is an initializer for a vector of HARD_REG_SET
1174 of length N_REG_CLASSES. */
1175
1176#define REG_CLASS_CONTENTS \
1177{ { 0x00, 0x0 }, \
1178 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1179 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1180 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1181 { 0x03, 0x0 }, /* AD_REGS */ \
1182 { 0x0f, 0x0 }, /* Q_REGS */ \
1183 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1184 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1185 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1186 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1187 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1188 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1189{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1190{ 0xe0000000, 0x1f }, /* MMX_REGS */ \
1191{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1192{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1193{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1194 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1195{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1196{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1197{ 0xffffffff,0x1fffff } \
1198}
1199
1200/* The same information, inverted:
1201 Return the class number of the smallest class containing
1202 reg number REGNO. This could be a conditional expression
1203 or could index an array. */
1204
1205#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1206
1207/* When defined, the compiler allows registers explicitly used in the
1208 rtl to be used as spill registers but prevents the compiler from
1209 extending the lifetime of these registers. */
1210
1211#define SMALL_REGISTER_CLASSES 1
1212
1213#define QI_REG_P(X) \
1214 (REG_P (X) && REGNO (X) < 4)
1215
1216#define GENERAL_REGNO_P(N) \
1217 ((N) < 8 || REX_INT_REGNO_P (N))
1218
1219#define GENERAL_REG_P(X) \
1220 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1221
1222#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1223
1224#define NON_QI_REG_P(X) \
1225 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1226
1227#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1228#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1229
1230#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1231#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1232#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1233#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1234
1235#define SSE_REGNO_P(N) \
1236 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1237 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1238
1239#define REX_SSE_REGNO_P(N) \
1240 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)
1241
1242#define SSE_REGNO(N) \
1243 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1244#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1245
1246#define SSE_FLOAT_MODE_P(MODE) \
1247 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1248
1249#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1250#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1251
1252#define STACK_REG_P(XOP) \
1253 (REG_P (XOP) && \
1254 REGNO (XOP) >= FIRST_STACK_REG && \
1255 REGNO (XOP) <= LAST_STACK_REG)
1256
1257#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1258
1259#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1260
1261#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1262#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1263
1264/* The class value for index registers, and the one for base regs. */
1265
1266#define INDEX_REG_CLASS INDEX_REGS
1267#define BASE_REG_CLASS GENERAL_REGS
1268
1269/* Place additional restrictions on the register class to use when it
1270 is necessary to be able to hold a value of mode MODE in a reload
1271 register for which class CLASS would ordinarily be used. */
1272
1273#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1274 ((MODE) == QImode && !TARGET_64BIT \
1275 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1276 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1277 ? Q_REGS : (CLASS))
1278
1279/* Given an rtx X being reloaded into a reg required to be
1280 in class CLASS, return the class of reg to actually use.
1281 In general this is just CLASS; but on some machines
1282 in some cases it is preferable to use a more restrictive class.
1283 On the 80386 series, we prevent floating constants from being
1284 reloaded into floating registers (since no move-insn can do that)
1285 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1286
1287/* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1288 QImode must go into class Q_REGS.
1289 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1290 movdf to do mem-to-mem moves through integer regs. */
1291
1292#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1293 ix86_preferred_reload_class ((X), (CLASS))
1294
1295/* Discourage putting floating-point values in SSE registers unless
1296 SSE math is being used, and likewise for the 387 registers. */
1297
1298#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1299 ix86_preferred_output_reload_class ((X), (CLASS))
1300
1301/* If we are copying between general and FP registers, we need a memory
1302 location. The same is true for SSE and MMX registers. */
1303#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1304 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1305
1306/* QImode spills from non-QI registers need a scratch. This does not
1307 happen often -- the only example so far requires an uninitialized
1308 pseudo. */
1309
1310#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1311 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1312 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1313 ? Q_REGS : NO_REGS)
1314
1315/* Return the maximum number of consecutive registers
1316 needed to represent mode MODE in a register of class CLASS. */
1317/* On the 80386, this is the size of MODE in words,
1318 except in the FP regs, where a single reg is always enough. */
1319#define CLASS_MAX_NREGS(CLASS, MODE) \
1320 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1321 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1322 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1323 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1324
1325/* A C expression whose value is nonzero if pseudos that have been
1326 assigned to registers of class CLASS would likely be spilled
1327 because registers of CLASS are needed for spill registers.
1328
1329 The default value of this macro returns 1 if CLASS has exactly one
1330 register and zero otherwise. On most machines, this default
1331 should be used. Only define this macro to some other expression
1332 if pseudo allocated by `local-alloc.c' end up in memory because
1333 their hard registers were needed for spill registers. If this
1334 macro returns nonzero for those classes, those pseudos will only
1335 be allocated by `global.c', which knows how to reallocate the
1336 pseudo to another register. If there would not be another
1337 register available for reallocation, you should not change the
1338 definition of this macro since the only effect of such a
1339 definition would be to slow down register allocation. */
1340
1341#define CLASS_LIKELY_SPILLED_P(CLASS) \
1342 (((CLASS) == AREG) \
1343 || ((CLASS) == DREG) \
1344 || ((CLASS) == CREG) \
1345 || ((CLASS) == BREG) \
1346 || ((CLASS) == AD_REGS) \
1347 || ((CLASS) == SIREG) \
1348 || ((CLASS) == DIREG) \
1349 || ((CLASS) == FP_TOP_REG) \
1350 || ((CLASS) == FP_SECOND_REG))
1351
1352/* Return a class of registers that cannot change FROM mode to TO mode. */
1353
1354#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1355 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1356
1357/* Stack layout; function entry, exit and calling. */
1358
1359/* Define this if pushing a word on the stack
1360 makes the stack pointer a smaller address. */
1361#define STACK_GROWS_DOWNWARD
1362
1363/* Define this to nonzero if the nominal address of the stack frame
1364 is at the high-address end of the local variables;
1365 that is, each additional local variable allocated
1366 goes at a more negative offset in the frame. */
1367#define FRAME_GROWS_DOWNWARD 1
1368
1369/* Offset within stack frame to start allocating local variables at.
1370 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1371 first local allocated. Otherwise, it is the offset to the BEGINNING
1372 of the first local allocated. */
1373#define STARTING_FRAME_OFFSET 0
1374
1375/* If we generate an insn to push BYTES bytes,
1376 this says how many the stack pointer really advances by.
1377 On 386, we have pushw instruction that decrements by exactly 2 no
1378 matter what the position was, there is no pushb.
1379 But as CIE data alignment factor on this arch is -4, we need to make
1380 sure all stack pointer adjustments are in multiple of 4.
1381
1382 For 64bit ABI we round up to 8 bytes.
1383 */
1384
1385#define PUSH_ROUNDING(BYTES) \
1386 (TARGET_64BIT \
1387 ? (((BYTES) + 7) & (-8)) \
1388 : (((BYTES) + 3) & (-4)))
1389
1390/* If defined, the maximum amount of space required for outgoing arguments will
1391 be computed and placed into the variable
1392 `current_function_outgoing_args_size'. No space will be pushed onto the
1393 stack for each call; instead, the function prologue should increase the stack
1394 frame size by this amount. */
1395
1396#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1397
1398/* If defined, a C expression whose value is nonzero when we want to use PUSH
1399 instructions to pass outgoing arguments. */
1400
1401#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1402
1403/* We want the stack and args grow in opposite directions, even if
1404 PUSH_ARGS is 0. */
1405#define PUSH_ARGS_REVERSED 1
1406
1407/* Offset of first parameter from the argument pointer register value. */
1408#define FIRST_PARM_OFFSET(FNDECL) 0
1409
1410/* Define this macro if functions should assume that stack space has been
1411 allocated for arguments even when their values are passed in registers.
1412
1413 The value of this macro is the size, in bytes, of the area reserved for
1414 arguments passed in registers for the function represented by FNDECL.
1415
1416 This space can be allocated by the caller, or be a part of the
1417 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1418 which. */
1419#define REG_PARM_STACK_SPACE(FNDECL) 0
1420
1421/* Value is the number of bytes of arguments automatically
1422 popped when returning from a subroutine call.
1423 FUNDECL is the declaration node of the function (as a tree),
1424 FUNTYPE is the data type of the function (as a tree),
1425 or for a library call it is an identifier node for the subroutine name.
1426 SIZE is the number of bytes of arguments passed on the stack.
1427
1428 On the 80386, the RTD insn may be used to pop them if the number
1429 of args is fixed, but if the number is variable then the caller
1430 must pop them all. RTD can't be used for library calls now
1431 because the library is compiled with the Unix compiler.
1432 Use of RTD is a selectable option, since it is incompatible with
1433 standard Unix calling sequences. If the option is not selected,
1434 the caller must always pop the args.
1435
1436 The attribute stdcall is equivalent to RTD on a per module basis. */
1437
1438#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1439 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1440
1441#define FUNCTION_VALUE_REGNO_P(N) \
1442 ix86_function_value_regno_p (N)
1443
1444/* Define how to find the value returned by a library function
1445 assuming the value has mode MODE. */
1446
1447#define LIBCALL_VALUE(MODE) \
1448 ix86_libcall_value (MODE)
1449
1450/* Define the size of the result block used for communication between
1451 untyped_call and untyped_return. The block contains a DImode value
1452 followed by the block used by fnsave and frstor. */
1453
1454#define APPLY_RESULT_SIZE (8+108)
1455
1456/* 1 if N is a possible register number for function argument passing. */
1457#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1458
1459/* Define a data type for recording info about an argument list
1460 during the scan of that argument list. This data type should
1461 hold all necessary information about the function itself
1462 and about the args processed so far, enough to enable macros
1463 such as FUNCTION_ARG to determine where the next arg should go. */
1464
1465typedef struct ix86_args {
1466 int words; /* # words passed so far */
1467 int nregs; /* # registers available for passing */
1468 int regno; /* next available register number */
1469 int fastcall; /* fastcall calling convention is used */
1470 int sse_words; /* # sse words passed so far */
1471 int sse_nregs; /* # sse registers available for passing */
1472 int warn_sse; /* True when we want to warn about SSE ABI. */
1473 int warn_mmx; /* True when we want to warn about MMX ABI. */
1474 int sse_regno; /* next available sse register number */
1475 int mmx_words; /* # mmx words passed so far */
1476 int mmx_nregs; /* # mmx registers available for passing */
1477 int mmx_regno; /* next available mmx register number */
1478 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1479 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1480 be passed in SSE registers. Otherwise 0. */
1481} CUMULATIVE_ARGS;
1482
1483/* Initialize a variable CUM of type CUMULATIVE_ARGS
1484 for a call to a function whose data type is FNTYPE.
1485 For a library call, FNTYPE is 0. */
1486
1487#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1488 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1489
1490/* Update the data in CUM to advance over an argument
1491 of mode MODE and data type TYPE.
1492 (TYPE is null for libcalls where that information may not be available.) */
1493
1494#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1495 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1496
1497/* Define where to put the arguments to a function.
1498 Value is zero to push the argument on the stack,
1499 or a hard register in which to store the argument.
1500
1501 MODE is the argument's machine mode.
1502 TYPE is the data type of the argument (as a tree).
1503 This is null for libcalls where that information may
1504 not be available.
1505 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1506 the preceding args and about the function being called.
1507 NAMED is nonzero if this argument is a named parameter
1508 (otherwise it is an extra parameter matching an ellipsis). */
1509
1510#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1511 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1512
1513/* Implement `va_start' for varargs and stdarg. */
1514#define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1515 ix86_va_start (VALIST, NEXTARG)
1516
1517#define TARGET_ASM_FILE_END ix86_file_end
1518#define NEED_INDICATE_EXEC_STACK 0
1519
1520/* Output assembler code to FILE to increment profiler label # LABELNO
1521 for profiling a function entry. */
1522
1523#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1524
1525#define MCOUNT_NAME "_mcount"
1526
1527#define PROFILE_COUNT_REGISTER "edx"
1528
1529/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1530 the stack pointer does not matter. The value is tested only in
1531 functions that have frame pointers.
1532 No definition is equivalent to always zero. */
1533/* Note on the 386 it might be more efficient not to define this since
1534 we have to restore it ourselves from the frame pointer, in order to
1535 use pop */
1536
1537#define EXIT_IGNORE_STACK 1
1538
1539/* Output assembler code for a block containing the constant parts
1540 of a trampoline, leaving space for the variable parts. */
1541
1542/* On the 386, the trampoline contains two instructions:
1543 mov #STATIC,ecx
1544 jmp FUNCTION
1545 The trampoline is generated entirely at runtime. The operand of JMP
1546 is the address of FUNCTION relative to the instruction following the
1547 JMP (which is 5 bytes long). */
1548
1549/* Length in units of the trampoline for entering a nested function. */
1550
1551#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1552
1553/* Emit RTL insns to initialize the variable parts of a trampoline.
1554 FNADDR is an RTX for the address of the function's pure code.
1555 CXT is an RTX for the static chain value for the function. */
1556
1557#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1558 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1559
1560/* Definitions for register eliminations.
1561
1562 This is an array of structures. Each structure initializes one pair
1563 of eliminable registers. The "from" register number is given first,
1564 followed by "to". Eliminations of the same "from" register are listed
1565 in order of preference.
1566
1567 There are two registers that can always be eliminated on the i386.
1568 The frame pointer and the arg pointer can be replaced by either the
1569 hard frame pointer or to the stack pointer, depending upon the
1570 circumstances. The hard frame pointer is not used before reload and
1571 so it is not eligible for elimination. */
1572
1573#define ELIMINABLE_REGS \
1574{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1575 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1576 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1577 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1578
1579/* Given FROM and TO register numbers, say whether this elimination is
1580 allowed. Frame pointer elimination is automatically handled.
1581
1582 All other eliminations are valid. */
1583
1584#define CAN_ELIMINATE(FROM, TO) \
1585 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1586
1587/* Define the offset between two registers, one to be eliminated, and the other
1588 its replacement, at the start of a routine. */
1589
1590#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1591 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1592
1593/* Addressing modes, and classification of registers for them. */
1594
1595/* Macros to check register numbers against specific register classes. */
1596
1597/* These assume that REGNO is a hard or pseudo reg number.
1598 They give nonzero only if REGNO is a hard reg of the suitable class
1599 or a pseudo reg currently allocated to a suitable hard reg.
1600 Since they use reg_renumber, they are safe only once reg_renumber
1601 has been allocated, which happens in local-alloc.c. */
1602
1603#define REGNO_OK_FOR_INDEX_P(REGNO) \
1604 ((REGNO) < STACK_POINTER_REGNUM \
1605 || (REGNO >= FIRST_REX_INT_REG \
1606 && (REGNO) <= LAST_REX_INT_REG) \
1607 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1608 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1609 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1610
1611#define REGNO_OK_FOR_BASE_P(REGNO) \
1612 ((REGNO) <= STACK_POINTER_REGNUM \
1613 || (REGNO) == ARG_POINTER_REGNUM \
1614 || (REGNO) == FRAME_POINTER_REGNUM \
1615 || (REGNO >= FIRST_REX_INT_REG \
1616 && (REGNO) <= LAST_REX_INT_REG) \
1617 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1618 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1619 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1620
1621#define REGNO_OK_FOR_SIREG_P(REGNO) \
1622 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1623#define REGNO_OK_FOR_DIREG_P(REGNO) \
1624 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1625
1626/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1627 and check its validity for a certain class.
1628 We have two alternate definitions for each of them.
1629 The usual definition accepts all pseudo regs; the other rejects
1630 them unless they have been allocated suitable hard regs.
1631 The symbol REG_OK_STRICT causes the latter definition to be used.
1632
1633 Most source files want to accept pseudo regs in the hope that
1634 they will get allocated to the class that the insn wants them to be in.
1635 Source files for reload pass need to be strict.
1636 After reload, it makes no difference, since pseudo regs have
1637 been eliminated by then. */
1638
1639
1640/* Non strict versions, pseudos are ok. */
1641#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1642 (REGNO (X) < STACK_POINTER_REGNUM \
1643 || (REGNO (X) >= FIRST_REX_INT_REG \
1644 && REGNO (X) <= LAST_REX_INT_REG) \
1645 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1646
1647#define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1648 (REGNO (X) <= STACK_POINTER_REGNUM \
1649 || REGNO (X) == ARG_POINTER_REGNUM \
1650 || REGNO (X) == FRAME_POINTER_REGNUM \
1651 || (REGNO (X) >= FIRST_REX_INT_REG \
1652 && REGNO (X) <= LAST_REX_INT_REG) \
1653 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1654
1655/* Strict versions, hard registers only */
1656#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1657#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1658
1659#ifndef REG_OK_STRICT
1660#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1661#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1662
1663#else
1664#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1665#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1666#endif
1667
1668/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1669 that is a valid memory address for an instruction.
1670 The MODE argument is the machine mode for the MEM expression
1671 that wants to use this address.
1672
1673 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1674 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1675
1676 See legitimize_pic_address in i386.c for details as to what
1677 constitutes a legitimate address when -fpic is used. */
1678
1679#define MAX_REGS_PER_ADDRESS 2
1680
1681#define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1682
1683/* Nonzero if the constant value X is a legitimate general operand.
1684 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1685
1686#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1687
1688#ifdef REG_OK_STRICT
1689#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1690do { \
1691 if (legitimate_address_p ((MODE), (X), 1)) \
1692 goto ADDR; \
1693} while (0)
1694
1695#else
1696#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1697do { \
1698 if (legitimate_address_p ((MODE), (X), 0)) \
1699 goto ADDR; \
1700} while (0)
1701
1702#endif
1703
1704/* If defined, a C expression to determine the base term of address X.
1705 This macro is used in only one place: `find_base_term' in alias.c.
1706
1707 It is always safe for this macro to not be defined. It exists so
1708 that alias analysis can understand machine-dependent addresses.
1709
1710 The typical use of this macro is to handle addresses containing
1711 a label_ref or symbol_ref within an UNSPEC. */
1712
1713#define FIND_BASE_TERM(X) ix86_find_base_term (X)
1714
1715/* Try machine-dependent ways of modifying an illegitimate address
1716 to be legitimate. If we find one, return the new, valid address.
1717 This macro is used in only one place: `memory_address' in explow.c.
1718
1719 OLDX is the address as it was before break_out_memory_refs was called.
1720 In some cases it is useful to look at this to decide what needs to be done.
1721
1722 MODE and WIN are passed so that this macro can use
1723 GO_IF_LEGITIMATE_ADDRESS.
1724
1725 It is always safe for this macro to do nothing. It exists to recognize
1726 opportunities to optimize the output.
1727
1728 For the 80386, we handle X+REG by loading X into a register R and
1729 using R+REG. R will go in a general reg and indexing will be used.
1730 However, if REG is a broken-out memory address or multiplication,
1731 nothing needs to be done because REG can certainly go in a general reg.
1732
1733 When -fpic is used, special handling is needed for symbolic references.
1734 See comments by legitimize_pic_address in i386.c for details. */
1735
1736#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1737do { \
1738 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1739 if (memory_address_p ((MODE), (X))) \
1740 goto WIN; \
1741} while (0)
1742
1743#define REWRITE_ADDRESS(X) rewrite_address (X)
1744
1745/* Nonzero if the constant value X is a legitimate general operand
1746 when generating PIC code. It is given that flag_pic is on and
1747 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1748
1749#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1750
1751#define SYMBOLIC_CONST(X) \
1752 (GET_CODE (X) == SYMBOL_REF \
1753 || GET_CODE (X) == LABEL_REF \
1754 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1755
1756/* Go to LABEL if ADDR (a legitimate address expression)
1757 has an effect that depends on the machine mode it is used for.
1758 On the 80386, only postdecrement and postincrement address depend thus
1759 (the amount of decrement or increment being the length of the operand). */
1760#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1761do { \
1762 if (GET_CODE (ADDR) == POST_INC \
1763 || GET_CODE (ADDR) == POST_DEC) \
1764 goto LABEL; \
1765} while (0)
1766
1767/* Max number of args passed in registers. If this is more than 3, we will
1768 have problems with ebx (register #4), since it is a caller save register and
1769 is also used as the pic register in ELF. So for now, don't allow more than
1770 3 registers to be passed in registers. */
1771
1772#define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1773
1774#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1775
1776#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1777
1778
1779/* Specify the machine mode that this machine uses
1780 for the index in the tablejump instruction. */
1781#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
1782
1783/* Define this as 1 if `char' should by default be signed; else as 0. */
1784#define DEFAULT_SIGNED_CHAR 1
1785
1786/* Number of bytes moved into a data cache for a single prefetch operation. */
1787#define PREFETCH_BLOCK ix86_cost->prefetch_block
1788
1789/* Number of prefetch operations that can be done in parallel. */
1790#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
1791
1792/* Max number of bytes we can move from memory to memory
1793 in one reasonably fast instruction. */
1794#define MOVE_MAX 16
1795
1796/* MOVE_MAX_PIECES is the number of bytes at a time which we can
1797 move efficiently, as opposed to MOVE_MAX which is the maximum
1798 number of bytes we can move with a single instruction. */
1799#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1800
1801/* If a memory-to-memory move would take MOVE_RATIO or more simple
1802 move-instruction pairs, we will do a movmem or libcall instead.
1803 Increasing the value will always make code faster, but eventually
1804 incurs high cost in increased code size.
1805
1806 If you don't define this, a reasonable default is used. */
1807
1808#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1809
1810/* If a clear memory operation would take CLEAR_RATIO or more simple
1811 move-instruction sequences, we will do a clrmem or libcall instead. */
1812
1813#define CLEAR_RATIO (optimize_size ? 2 \
1814 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
1815
1816/* Define if shifts truncate the shift count
1817 which implies one can omit a sign-extension or zero-extension
1818 of a shift count. */
1819/* On i386, shifts do truncate the count. But bit opcodes don't. */
1820
1821/* #define SHIFT_COUNT_TRUNCATED */
1822
1823/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1824 is done just by pretending it is already truncated. */
1825#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1826
1827/* A macro to update M and UNSIGNEDP when an object whose type is
1828 TYPE and which has the specified mode and signedness is to be
1829 stored in a register. This macro is only called when TYPE is a
1830 scalar type.
1831
1832 On i386 it is sometimes useful to promote HImode and QImode
1833 quantities to SImode. The choice depends on target type. */
1834
1835#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1836do { \
1837 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1838 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1839 (MODE) = SImode; \
1840} while (0)
1841
1842/* Specify the machine mode that pointers have.
1843 After generation of rtl, the compiler makes no further distinction
1844 between pointers and any other objects of this machine mode. */
1845#define Pmode (TARGET_64BIT ? DImode : SImode)
1846
1847/* A function address in a call instruction
1848 is a byte address (for indexing purposes)
1849 so give the MEM rtx a byte's mode. */
1850#define FUNCTION_MODE QImode
1851
1852/* A C expression for the cost of moving data from a register in class FROM to
1853 one in class TO. The classes are expressed using the enumeration values
1854 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1855 interpreted relative to that.
1856
1857 It is not required that the cost always equal 2 when FROM is the same as TO;
1858 on some machines it is expensive to move between registers if they are not
1859 general registers. */
1860
1861#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1862 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1863
1864/* A C expression for the cost of moving data of mode M between a
1865 register and memory. A value of 2 is the default; this cost is
1866 relative to those in `REGISTER_MOVE_COST'.
1867
1868 If moving between registers and memory is more expensive than
1869 between two registers, you should define this macro to express the
1870 relative cost. */
1871
1872#define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1873 ix86_memory_move_cost ((MODE), (CLASS), (IN))
1874
1875/* A C expression for the cost of a branch instruction. A value of 1
1876 is the default; other values are interpreted relative to that. */
1877
1878#define BRANCH_COST ix86_branch_cost
1879
1880/* Define this macro as a C expression which is nonzero if accessing
1881 less than a word of memory (i.e. a `char' or a `short') is no
1882 faster than accessing a word of memory, i.e., if such access
1883 require more than one instruction or if there is no difference in
1884 cost between byte and (aligned) word loads.
1885
1886 When this macro is not defined, the compiler will access a field by
1887 finding the smallest containing object; when it is defined, a
1888 fullword load will be used if alignment permits. Unless bytes
1889 accesses are faster than word accesses, using word accesses is
1890 preferable since it may eliminate subsequent memory access if
1891 subsequent accesses occur to other fields in the same word of the
1892 structure, but to different bytes. */
1893
1894#define SLOW_BYTE_ACCESS 0
1895
1896/* Nonzero if access to memory by shorts is slow and undesirable. */
1897#define SLOW_SHORT_ACCESS 0
1898
1899/* Define this macro to be the value 1 if unaligned accesses have a
1900 cost many times greater than aligned accesses, for example if they
1901 are emulated in a trap handler.
1902
1903 When this macro is nonzero, the compiler will act as if
1904 `STRICT_ALIGNMENT' were nonzero when generating code for block
1905 moves. This can cause significantly more instructions to be
1906 produced. Therefore, do not set this macro nonzero if unaligned
1907 accesses only add a cycle or two to the time for a memory access.
1908
1909 If the value of this macro is always zero, it need not be defined. */
1910
1911/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1912
1913/* Define this macro if it is as good or better to call a constant
1914 function address than to call an address kept in a register.
1915
1916 Desirable on the 386 because a CALL with a constant address is
1917 faster than one with a register address. */
1918
1919#define NO_FUNCTION_CSE
1920
1921/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1922 return the mode to be used for the comparison.
1923
1924 For floating-point equality comparisons, CCFPEQmode should be used.
1925 VOIDmode should be used in all other cases.
1926
1927 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1928 possible, to allow for more combinations. */
1929
1930#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1931
1932/* Return nonzero if MODE implies a floating point inequality can be
1933 reversed. */
1934
1935#define REVERSIBLE_CC_MODE(MODE) 1
1936
1937/* A C expression whose value is reversed condition code of the CODE for
1938 comparison done in CC_MODE mode. */
1939#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1940
1941
1942/* Control the assembler format that we output, to the extent
1943 this does not vary between assemblers. */
1944
1945/* How to refer to registers in assembler output.
1946 This sequence is indexed by compiler's hard-register-number (see above). */
1947
1948/* In order to refer to the first 8 regs as 32 bit regs, prefix an "e".
1949 For non floating point regs, the following are the HImode names.
1950
1951 For float regs, the stack top is sometimes referred to as "%st(0)"
1952 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
1953
1954#define HI_REGISTER_NAMES \
1955{"ax","dx","cx","bx","si","di","bp","sp", \
1956 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1957 "argp", "flags", "fpsr", "dirflag", "frame", \
1958 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1959 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
1960 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1961 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
1962
1963#define REGISTER_NAMES HI_REGISTER_NAMES
1964
1965/* Table of additional register names to use in user input. */
1966
1967#define ADDITIONAL_REGISTER_NAMES \
1968{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
1969 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
1970 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
1971 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
1972 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
1973 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
1974
1975/* Note we are omitting these since currently I don't know how
1976to get gcc to use these, since they want the same but different
1977number as al, and ax.
1978*/
1979
1980#define QI_REGISTER_NAMES \
1981{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
1982
1983/* These parallel the array above, and can be used to access bits 8:15
1984 of regs 0 through 3. */
1985
1986#define QI_HIGH_REGISTER_NAMES \
1987{"ah", "dh", "ch", "bh", }
1988
1989/* How to renumber registers for dbx and gdb. */
1990
1991#define DBX_REGISTER_NUMBER(N) \
1992 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
1993
1994extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
1995extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
1996extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
1997
1998/* Before the prologue, RA is at 0(%esp). */
1999#define INCOMING_RETURN_ADDR_RTX \
2000 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2001
2002/* After the prologue, RA is at -4(AP) in the current frame. */
2003#define RETURN_ADDR_RTX(COUNT, FRAME) \
2004 ((COUNT) == 0 \
2005 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2006 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2007
2008/* PC is dbx register 8; let's use that column for RA. */
2009#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2010
2011/* Before the prologue, the top of the frame is at 4(%esp). */
2012#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2013
2014/* Describe how we implement __builtin_eh_return. */
2015#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2016#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2017
2018
2019/* Select a format to encode pointers in exception handling data. CODE
2020 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2021 true if the symbol may be affected by dynamic relocations.
2022
2023 ??? All x86 object file formats are capable of representing this.
2024 After all, the relocation needed is the same as for the call insn.
2025 Whether or not a particular assembler allows us to enter such, I
2026 guess we'll have to see. */
2027#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2028 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2029
2030/* This is how to output an insn to push a register on the stack.
2031 It need not be very fast code. */
2032
2033#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2034do { \
2035 if (TARGET_64BIT) \
2036 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2037 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2038 else \
2039 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2040} while (0)
2041
2042/* This is how to output an insn to pop a register from the stack.
2043 It need not be very fast code. */
2044
2045#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2046do { \
2047 if (TARGET_64BIT) \
2048 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2049 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2050 else \
2051 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2052} while (0)
2053
2054/* This is how to output an element of a case-vector that is absolute. */
2055
2056#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2057 ix86_output_addr_vec_elt ((FILE), (VALUE))
2058
2059/* This is how to output an element of a case-vector that is relative. */
2060
2061#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2062 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2063
2064/* Under some conditions we need jump tables in the text section,
2065 because the assembler cannot handle label differences between
2066 sections. This is the case for x86_64 on Mach-O for example. */
2067
2068#define JUMP_TABLES_IN_TEXT_SECTION \
2069 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2070 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2071
2072/* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2073 and switch back. For x86 we do this only to save a few bytes that
2074 would otherwise be unused in the text section. */
2075#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2076 asm (SECTION_OP "\n\t" \
2077 "call " USER_LABEL_PREFIX #FUNC "\n" \
2078 TEXT_SECTION_ASM_OP);
2079
2080/* Print operand X (an rtx) in assembler syntax to file FILE.
2081 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2082 Effect of various CODE letters is described in i386.c near
2083 print_operand function. */
2084
2085#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2086 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2087
2088#define PRINT_OPERAND(FILE, X, CODE) \
2089 print_operand ((FILE), (X), (CODE))
2090
2091#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2092 print_operand_address ((FILE), (ADDR))
2093
2094#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2095do { \
2096 if (! output_addr_const_extra (FILE, (X))) \
2097 goto FAIL; \
2098} while (0);
2099
2100/* a letter which is not needed by the normal asm syntax, which
2101 we can use for operand syntax in the extended asm */
2102
2103#define ASM_OPERAND_LETTER '#'
2104#define RET return ""
2105#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
2106
2107/* Which processor to schedule for. The cpu attribute defines a list that
2108 mirrors this list, so changes to i386.md must be made at the same time. */
2109
2110enum processor_type
2111{
2112 PROCESSOR_I386, /* 80386 */
2113 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2114 PROCESSOR_PENTIUM,
2115 PROCESSOR_PENTIUMPRO,
2116 PROCESSOR_GEODE,
2117 PROCESSOR_K6,
2118 PROCESSOR_ATHLON,
2119 PROCESSOR_PENTIUM4,
2120 PROCESSOR_K8,
2121 PROCESSOR_NOCONA,
2122 PROCESSOR_CORE2,
2123 PROCESSOR_GENERIC32,
2124 PROCESSOR_GENERIC64,
2125 PROCESSOR_AMDFAM10,
2111 PROCESSOR_max
2112};
2113
2114extern enum processor_type ix86_tune;
2115extern enum processor_type ix86_arch;
2116
2117enum fpmath_unit
2118{
2119 FPMATH_387 = 1,
2120 FPMATH_SSE = 2
2121};
2122
2123extern enum fpmath_unit ix86_fpmath;
2124
2125enum tls_dialect
2126{
2127 TLS_DIALECT_GNU,
2128 TLS_DIALECT_GNU2,
2129 TLS_DIALECT_SUN
2130};
2131
2132extern enum tls_dialect ix86_tls_dialect;
2133
2134enum cmodel {
2135 CM_32, /* The traditional 32-bit ABI. */
2136 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2137 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2138 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2139 CM_LARGE, /* No assumptions. */
2140 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2141 CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */
2142};
2143
2144extern enum cmodel ix86_cmodel;
2145
2146/* Size of the RED_ZONE area. */
2147#define RED_ZONE_SIZE 128
2148/* Reserved area of the red zone for temporaries. */
2149#define RED_ZONE_RESERVE 8
2150
2151enum asm_dialect {
2152 ASM_ATT,
2153 ASM_INTEL
2154};
2155
2156extern enum asm_dialect ix86_asm_dialect;
2157extern unsigned int ix86_preferred_stack_boundary;
2158extern int ix86_branch_cost, ix86_section_threshold;
2159
2160/* Smallest class containing REGNO. */
2161extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2162
2163extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2164extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2165extern rtx ix86_compare_emitted;
2166
2167/* To properly truncate FP values into integers, we need to set i387 control
2168 word. We can't emit proper mode switching code before reload, as spills
2169 generated by reload may truncate values incorrectly, but we still can avoid
2170 redundant computation of new control word by the mode switching pass.
2171 The fldcw instructions are still emitted redundantly, but this is probably
2172 not going to be noticeable problem, as most CPUs do have fast path for
2173 the sequence.
2174
2175 The machinery is to emit simple truncation instructions and split them
2176 before reload to instructions having USEs of two memory locations that
2177 are filled by this code to old and new control word.
2178
2179 Post-reload pass may be later used to eliminate the redundant fildcw if
2180 needed. */
2181
2182enum ix86_entity
2183{
2184 I387_TRUNC = 0,
2185 I387_FLOOR,
2186 I387_CEIL,
2187 I387_MASK_PM,
2188 MAX_386_ENTITIES
2189};
2190
2191enum ix86_stack_slot
2192{
2193 SLOT_VIRTUAL = 0,
2194 SLOT_TEMP,
2195 SLOT_CW_STORED,
2196 SLOT_CW_TRUNC,
2197 SLOT_CW_FLOOR,
2198 SLOT_CW_CEIL,
2199 SLOT_CW_MASK_PM,
2200 MAX_386_STACK_LOCALS
2201};
2202
2203/* Define this macro if the port needs extra instructions inserted
2204 for mode switching in an optimizing compilation. */
2205
2206#define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2207 ix86_optimize_mode_switching[(ENTITY)]
2208
2209/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2210 initializer for an array of integers. Each initializer element N
2211 refers to an entity that needs mode switching, and specifies the
2212 number of different modes that might need to be set for this
2213 entity. The position of the initializer in the initializer -
2214 starting counting at zero - determines the integer that is used to
2215 refer to the mode-switched entity in question. */
2216
2217#define NUM_MODES_FOR_MODE_SWITCHING \
2218 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2219
2220/* ENTITY is an integer specifying a mode-switched entity. If
2221 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2222 return an integer value not larger than the corresponding element
2223 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2224 must be switched into prior to the execution of INSN. */
2225
2226#define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2227
2228/* This macro specifies the order in which modes for ENTITY are
2229 processed. 0 is the highest priority. */
2230
2231#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2232
2233/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2234 is the set of hard registers live at the point where the insn(s)
2235 are to be inserted. */
2236
2237#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2238 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2239 ? emit_i387_cw_initialization (MODE), 0 \
2240 : 0)
2241
2242
2243/* Avoid renaming of stack registers, as doing so in combination with
2244 scheduling just increases amount of live registers at time and in
2245 the turn amount of fxch instructions needed.
2246
2247 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2248
2249#define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2250 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
2251
2252
2253#define DLL_IMPORT_EXPORT_PREFIX '#'
2254
2255#define FASTCALL_PREFIX '@'
2256
2257struct machine_function GTY(())
2258{
2259 struct stack_local_entry *stack_locals;
2260 const char *some_ld_name;
2261 rtx force_align_arg_pointer;
2262 int save_varrargs_registers;
2263 int accesses_prev_frame;
2264 int optimize_mode_switching[MAX_386_ENTITIES];
2265 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2266 determine the style used. */
2267 int use_fast_prologue_epilogue;
2268 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2269 for. */
2270 int use_fast_prologue_epilogue_nregs;
2271 /* If true, the current function needs the default PIC register, not
2272 an alternate register (on x86) and must not use the red zone (on
2273 x86_64), even if it's a leaf function. We don't want the
2274 function to be regarded as non-leaf because TLS calls need not
2275 affect register allocation. This flag is set when a TLS call
2276 instruction is expanded within a function, and never reset, even
2277 if all such instructions are optimized away. Use the
2278 ix86_current_function_calls_tls_descriptor macro for a better
2279 approximation. */
2280 int tls_descriptor_call_expanded_p;
2281};
2282
2283#define ix86_stack_locals (cfun->machine->stack_locals)
2284#define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2285#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2286#define ix86_tls_descriptor_calls_expanded_in_cfun \
2287 (cfun->machine->tls_descriptor_call_expanded_p)
2288/* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2289 calls are optimized away, we try to detect cases in which it was
2290 optimized away. Since such instructions (use (reg REG_SP)), we can
2291 verify whether there's any such instruction live by testing that
2292 REG_SP is live. */
2293#define ix86_current_function_calls_tls_descriptor \
2294 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG])
2295
2296/* Control behavior of x86_file_start. */
2297#define X86_FILE_START_VERSION_DIRECTIVE false
2298#define X86_FILE_START_FLTUSED false
2299
2300/* Flag to mark data that is in the large address area. */
2301#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2302#define SYMBOL_REF_FAR_ADDR_P(X) \
2303 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2304/*
2305Local variables:
2306version-control: t
2307End:
2308*/
2126 PROCESSOR_max
2127};
2128
2129extern enum processor_type ix86_tune;
2130extern enum processor_type ix86_arch;
2131
2132enum fpmath_unit
2133{
2134 FPMATH_387 = 1,
2135 FPMATH_SSE = 2
2136};
2137
2138extern enum fpmath_unit ix86_fpmath;
2139
2140enum tls_dialect
2141{
2142 TLS_DIALECT_GNU,
2143 TLS_DIALECT_GNU2,
2144 TLS_DIALECT_SUN
2145};
2146
2147extern enum tls_dialect ix86_tls_dialect;
2148
2149enum cmodel {
2150 CM_32, /* The traditional 32-bit ABI. */
2151 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2152 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2153 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2154 CM_LARGE, /* No assumptions. */
2155 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2156 CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */
2157};
2158
2159extern enum cmodel ix86_cmodel;
2160
2161/* Size of the RED_ZONE area. */
2162#define RED_ZONE_SIZE 128
2163/* Reserved area of the red zone for temporaries. */
2164#define RED_ZONE_RESERVE 8
2165
2166enum asm_dialect {
2167 ASM_ATT,
2168 ASM_INTEL
2169};
2170
2171extern enum asm_dialect ix86_asm_dialect;
2172extern unsigned int ix86_preferred_stack_boundary;
2173extern int ix86_branch_cost, ix86_section_threshold;
2174
2175/* Smallest class containing REGNO. */
2176extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2177
2178extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2179extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2180extern rtx ix86_compare_emitted;
2181
2182/* To properly truncate FP values into integers, we need to set i387 control
2183 word. We can't emit proper mode switching code before reload, as spills
2184 generated by reload may truncate values incorrectly, but we still can avoid
2185 redundant computation of new control word by the mode switching pass.
2186 The fldcw instructions are still emitted redundantly, but this is probably
2187 not going to be noticeable problem, as most CPUs do have fast path for
2188 the sequence.
2189
2190 The machinery is to emit simple truncation instructions and split them
2191 before reload to instructions having USEs of two memory locations that
2192 are filled by this code to old and new control word.
2193
2194 Post-reload pass may be later used to eliminate the redundant fildcw if
2195 needed. */
2196
2197enum ix86_entity
2198{
2199 I387_TRUNC = 0,
2200 I387_FLOOR,
2201 I387_CEIL,
2202 I387_MASK_PM,
2203 MAX_386_ENTITIES
2204};
2205
2206enum ix86_stack_slot
2207{
2208 SLOT_VIRTUAL = 0,
2209 SLOT_TEMP,
2210 SLOT_CW_STORED,
2211 SLOT_CW_TRUNC,
2212 SLOT_CW_FLOOR,
2213 SLOT_CW_CEIL,
2214 SLOT_CW_MASK_PM,
2215 MAX_386_STACK_LOCALS
2216};
2217
2218/* Define this macro if the port needs extra instructions inserted
2219 for mode switching in an optimizing compilation. */
2220
2221#define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2222 ix86_optimize_mode_switching[(ENTITY)]
2223
2224/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2225 initializer for an array of integers. Each initializer element N
2226 refers to an entity that needs mode switching, and specifies the
2227 number of different modes that might need to be set for this
2228 entity. The position of the initializer in the initializer -
2229 starting counting at zero - determines the integer that is used to
2230 refer to the mode-switched entity in question. */
2231
2232#define NUM_MODES_FOR_MODE_SWITCHING \
2233 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2234
2235/* ENTITY is an integer specifying a mode-switched entity. If
2236 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2237 return an integer value not larger than the corresponding element
2238 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2239 must be switched into prior to the execution of INSN. */
2240
2241#define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2242
2243/* This macro specifies the order in which modes for ENTITY are
2244 processed. 0 is the highest priority. */
2245
2246#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2247
2248/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2249 is the set of hard registers live at the point where the insn(s)
2250 are to be inserted. */
2251
2252#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2253 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2254 ? emit_i387_cw_initialization (MODE), 0 \
2255 : 0)
2256
2257
2258/* Avoid renaming of stack registers, as doing so in combination with
2259 scheduling just increases amount of live registers at time and in
2260 the turn amount of fxch instructions needed.
2261
2262 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2263
2264#define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2265 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
2266
2267
2268#define DLL_IMPORT_EXPORT_PREFIX '#'
2269
2270#define FASTCALL_PREFIX '@'
2271
2272struct machine_function GTY(())
2273{
2274 struct stack_local_entry *stack_locals;
2275 const char *some_ld_name;
2276 rtx force_align_arg_pointer;
2277 int save_varrargs_registers;
2278 int accesses_prev_frame;
2279 int optimize_mode_switching[MAX_386_ENTITIES];
2280 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2281 determine the style used. */
2282 int use_fast_prologue_epilogue;
2283 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2284 for. */
2285 int use_fast_prologue_epilogue_nregs;
2286 /* If true, the current function needs the default PIC register, not
2287 an alternate register (on x86) and must not use the red zone (on
2288 x86_64), even if it's a leaf function. We don't want the
2289 function to be regarded as non-leaf because TLS calls need not
2290 affect register allocation. This flag is set when a TLS call
2291 instruction is expanded within a function, and never reset, even
2292 if all such instructions are optimized away. Use the
2293 ix86_current_function_calls_tls_descriptor macro for a better
2294 approximation. */
2295 int tls_descriptor_call_expanded_p;
2296};
2297
2298#define ix86_stack_locals (cfun->machine->stack_locals)
2299#define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2300#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2301#define ix86_tls_descriptor_calls_expanded_in_cfun \
2302 (cfun->machine->tls_descriptor_call_expanded_p)
2303/* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2304 calls are optimized away, we try to detect cases in which it was
2305 optimized away. Since such instructions (use (reg REG_SP)), we can
2306 verify whether there's any such instruction live by testing that
2307 REG_SP is live. */
2308#define ix86_current_function_calls_tls_descriptor \
2309 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG])
2310
2311/* Control behavior of x86_file_start. */
2312#define X86_FILE_START_VERSION_DIRECTIVE false
2313#define X86_FILE_START_FLTUSED false
2314
2315/* Flag to mark data that is in the large address area. */
2316#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2317#define SYMBOL_REF_FAR_ADDR_P(X) \
2318 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2319/*
2320Local variables:
2321version-control: t
2322End:
2323*/