1/* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
--- 5 unchanged lines hidden (view full) ---
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING. If not, write to
19the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20Boston, MA 02110-1301, USA. */
21
22/* $FreeBSD: head/contrib/gcc/config/i386/i386.c 237021 2012-06-13 20:21:08Z pfg $ */
23
24#include "config.h"
25#include "system.h"
26#include "coretypes.h"
27#include "tm.h"
28#include "rtl.h"
29#include "tree.h"
30#include "tm_p.h"
--- 512 unchanged lines hidden (view full) ---
543 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
544 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
545 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
546 COSTS_N_INSNS (2), /* cost of FABS instruction. */
547 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
548 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
549};
550
551static const
552struct processor_costs pentium4_cost = {
553 COSTS_N_INSNS (1), /* cost of an add instruction */
554 COSTS_N_INSNS (3), /* cost of a lea instruction */
555 COSTS_N_INSNS (4), /* variable shift costs */
556 COSTS_N_INSNS (4), /* constant shift costs */
557 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
558 COSTS_N_INSNS (15), /* HI */
--- 270 unchanged lines hidden (view full) ---
829#define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
830#define m_GEODE (1<<PROCESSOR_GEODE)
831#define m_K6_GEODE (m_K6 | m_GEODE)
832#define m_K6 (1<<PROCESSOR_K6)
833#define m_ATHLON (1<<PROCESSOR_ATHLON)
834#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
835#define m_K8 (1<<PROCESSOR_K8)
836#define m_ATHLON_K8 (m_K8 | m_ATHLON)
837#define m_NOCONA (1<<PROCESSOR_NOCONA)
838#define m_CORE2 (1<<PROCESSOR_CORE2)
839#define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
840#define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
841#define m_GENERIC (m_GENERIC32 | m_GENERIC64)
842
843/* Generic instruction choice should be common subset of supported CPUs
844 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
845
846/* Leave is not affecting Nocona SPEC2000 results negatively, so enabling for
847 Generic64 seems like good code size tradeoff. We can't enable it for 32bit
848 generic because it is not working well with PPro base chips. */
849const int x86_use_leave = m_386 | m_K6_GEODE | m_ATHLON_K8 | m_CORE2 | m_GENERIC64;
850const int x86_push_memory = m_386 | m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
851const int x86_zero_extend_with_and = m_486 | m_PENT;
852const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */;
853const int x86_double_with_add = ~m_386;
854const int x86_use_bit_test = m_386;
855const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_CORE2 | m_GENERIC;
856const int x86_cmove = m_PPRO | m_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
857const int x86_3dnow_a = m_ATHLON_K8;
858const int x86_deep_branch = m_PPRO | m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
859/* Branch hints were put in P4 based on simulation result. But
860 after P4 was made, no performance benefit was observed with
861 branch hints. It also increases the code size. As the result,
862 icc never generates branch hints. */
863const int x86_branch_hints = 0;
864const int x86_use_sahf = m_PPRO | m_K6_GEODE | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_GENERIC | m_ATHLON_K8 ? */
865/* We probably ought to watch for partial register stalls on Generic32
866 compilation setting as well. However in current implementation the
867 partial register stalls are not eliminated very well - they can
868 be introduced via subregs synthesized by combine and can happen
869 in caller/callee saving sequences.
870 Because this option pays back little on PPro based chips and is in conflict
871 with partial reg. dependencies used by Athlon/P4 based chips, it is better
872 to leave it off for generic32 for now. */
873const int x86_partial_reg_stall = m_PPRO;
874const int x86_partial_flag_reg_stall = m_CORE2 | m_GENERIC;
875const int x86_use_himode_fiop = m_386 | m_486 | m_K6_GEODE;
876const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_CORE2 | m_GENERIC);
877const int x86_use_mov0 = m_K6;
878const int x86_use_cltd = ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC);
879const int x86_read_modify_write = ~m_PENT;
880const int x86_read_modify = ~(m_PENT | m_PPRO);
881const int x86_split_long_moves = m_PPRO;
882const int x86_promote_QImode = m_K6_GEODE | m_PENT | m_386 | m_486 | m_ATHLON_K8 | m_CORE2 | m_GENERIC; /* m_PENT4 ? */
883const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
884const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
885const int x86_qimode_math = ~(0);
886const int x86_promote_qi_regs = 0;
887/* On PPro this flag is meant to avoid partial register stalls. Just like
888 the x86_partial_reg_stall this option might be considered for Generic32
889 if our scheme for avoiding partial stalls was more effective. */
890const int x86_himode_math = ~(m_PPRO);
891const int x86_promote_hi_regs = m_PPRO;
892const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
893const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
894const int x86_add_esp_4 = m_ATHLON_K8 | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
895const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6_GEODE | m_386 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
896const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_GEODE);
897const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
898const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
899const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
900const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC;
901const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC;
902const int x86_shift1 = ~m_486;
903const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
904/* In Generic model we have an conflict here in between PPro/Pentium4 based chips
905 that thread 128bit SSE registers as single units versus K8 based chips that
906 divide SSE registers to two 64bit halves.
907 x86_sse_partial_reg_dependency promote all store destinations to be 128bit
908 to allow register renaming on 128bit SSE units, but usually results in one
909 extra microop on 64bit SSE units. Experimental results shows that disabling
910 this option on P4 brings over 20% SPECfp regression, while enabling it on
911 K8 brings roughly 2.4% regression that can be partly masked by careful scheduling
912 of moves. */
913const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
914/* Set for machines where the type and dependencies are resolved on SSE
915 register parts instead of whole registers, so we may maintain just
916 lower part of scalar values in proper format leaving the upper part
917 undefined. */
918const int x86_sse_split_regs = m_ATHLON_K8;
919const int x86_sse_typeless_stores = m_ATHLON_K8;
920const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
921const int x86_use_ffreep = m_ATHLON_K8;
922const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6_GEODE | m_CORE2;
923const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC);
924
925/* ??? Allowing interunit moves makes it all too easy for the compiler to put
926 integer data in xmm registers. Which results in pretty abysmal code. */
927const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */;
928
929const int x86_ext_80387_constants = m_K6_GEODE | m_ATHLON | m_PENT4 | m_NOCONA | m_CORE2 | m_PPRO | m_GENERIC32;
930/* Some CPU cores are not able to predict more than 4 branch instructions in
931 the 16 byte window. */
932const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
933const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC;
934const int x86_use_bt = m_ATHLON_K8;
935/* Compare and exchange was added for 80486. */
936const int x86_cmpxchg = ~m_386;
937/* Compare and exchange 8 bytes was added for pentium. */
938const int x86_cmpxchg8b = ~(m_386 | m_486);
939/* Compare and exchange 16 bytes was added for nocona. */
940const int x86_cmpxchg16b = m_NOCONA | m_CORE2;
941/* Exchange and add was added for 80486. */
942const int x86_xadd = ~m_386;
943const int x86_pad_returns = m_ATHLON_K8 | m_CORE2 | m_GENERIC;
944
945/* In case the average insn count for single function invocation is
946 lower than this constant, emit fast (but longer) prologue and
947 epilogue code. */
948#define FAST_PROLOGUE_INSN_COUNT 20
949
950/* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
951static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
--- 200 unchanged lines hidden (view full) ---
1152/* Which cpu are we scheduling for. */
1153enum processor_type ix86_tune;
1154/* Which instruction set architecture to use. */
1155enum processor_type ix86_arch;
1156
1157/* true if sse prefetch instruction is not NOOP. */
1158int x86_prefetch_sse;
1159
1160/* ix86_regparm_string as a number */
1161static int ix86_regparm;
1162
1163/* -mstackrealign option */
1164extern int ix86_force_align_arg_pointer;
1165static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer";
1166
1167/* Preferred alignment for stack boundary in bits. */
--- 338 unchanged lines hidden (view full) ---
1506 target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
1507 target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
1508 }
1509 return true;
1510
1511 case OPT_msse:
1512 if (!value)
1513 {
1514 target_flags &= ~(MASK_SSE2 | MASK_SSE3 | MASK_SSSE3);
1515 target_flags_explicit |= MASK_SSE2 | MASK_SSE3 | MASK_SSSE3;
1516 }
1517 return true;
1518
1519 case OPT_msse2:
1520 if (!value)
1521 {
1522 target_flags &= ~(MASK_SSE3 | MASK_SSSE3);
1523 target_flags_explicit |= MASK_SSE3 | MASK_SSSE3;
1524 }
1525 return true;
1526
1527 case OPT_msse3:
1528 if (!value)
1529 {
1530 target_flags &= ~MASK_SSSE3;
1531 target_flags_explicit |= MASK_SSSE3;
1532 }
1533 return true;
1534
1535 default:
1536 return true;
1537 }
1538}
1539
--- 35 unchanged lines hidden (view full) ---
1575 {&geode_cost, 0, 0, 0, 0, 0, 0, 0},
1576 {&k6_cost, 0, 0, 32, 7, 32, 7, 32},
1577 {&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
1578 {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
1579 {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
1580 {&nocona_cost, 0, 0, 0, 0, 0, 0, 0},
1581 {&core2_cost, 0, 0, 16, 7, 16, 7, 16},
1582 {&generic32_cost, 0, 0, 16, 7, 16, 7, 16},
1583 {&generic64_cost, 0, 0, 16, 7, 16, 7, 16}
1584 };
1585
1586 static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
1587 static struct pta
1588 {
1589 const char *const name; /* processor name or nickname. */
1590 const enum processor_type processor;
1591 const enum pta_flags
1592 {
1593 PTA_SSE = 1,
1594 PTA_SSE2 = 2,
1595 PTA_SSE3 = 4,
1596 PTA_MMX = 8,
1597 PTA_PREFETCH_SSE = 16,
1598 PTA_3DNOW = 32,
1599 PTA_3DNOW_A = 64,
1600 PTA_64BIT = 128,
1601 PTA_SSSE3 = 256
1602 } flags;
1603 }
1604 const processor_alias_table[] =
1605 {
1606 {"i386", PROCESSOR_I386, 0},
1607 {"i486", PROCESSOR_I486, 0},
1608 {"i586", PROCESSOR_PENTIUM, 0},
1609 {"pentium", PROCESSOR_PENTIUM, 0},
--- 10 unchanged lines hidden (view full) ---
1620 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE | PTA_SSE2},
1621 {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1622 | PTA_MMX | PTA_PREFETCH_SSE},
1623 {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1624 | PTA_MMX | PTA_PREFETCH_SSE},
1625 {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
1626 | PTA_MMX | PTA_PREFETCH_SSE},
1627 {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
1628 | PTA_MMX | PTA_PREFETCH_SSE},
1629 {"core2", PROCESSOR_CORE2, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
1630 | PTA_64BIT | PTA_MMX
1631 | PTA_PREFETCH_SSE},
1632 {"geode", PROCESSOR_GEODE, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1633 | PTA_3DNOW_A},
1634 {"k6", PROCESSOR_K6, PTA_MMX},
1635 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1636 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1637 {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1638 | PTA_3DNOW_A},
1639 {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
--- 18 unchanged lines hidden (view full) ---
1658 | PTA_SSE3 },
1659 {"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1660 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1661 {"athlon64-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1662 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
1663 | PTA_SSE3 },
1664 {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1665 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1666 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
1667 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
1668 };
1669
1670 int const pta_size = ARRAY_SIZE (processor_alias_table);
1671
1672#ifdef SUBTARGET_OVERRIDE_OPTIONS
1673 SUBTARGET_OVERRIDE_OPTIONS;
--- 146 unchanged lines hidden (view full) ---
1820 if (processor_alias_table[i].flags & PTA_SSE3
1821 && !(target_flags_explicit & MASK_SSE3))
1822 target_flags |= MASK_SSE3;
1823 if (processor_alias_table[i].flags & PTA_SSSE3
1824 && !(target_flags_explicit & MASK_SSSE3))
1825 target_flags |= MASK_SSSE3;
1826 if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
1827 x86_prefetch_sse = true;
1828 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1829 error ("CPU you selected does not support x86-64 "
1830 "instruction set");
1831 break;
1832 }
1833
1834 if (i == pta_size)
1835 error ("bad value (%s) for -march= switch", ix86_arch_string);
--- 162 unchanged lines hidden (view full) ---
1998 software floating point, don't use 387 inline intrinsics. */
1999 if (!TARGET_80387)
2000 target_flags |= MASK_NO_FANCY_MATH_387;
2001
2002 /* Turn on SSE3 builtins for -mssse3. */
2003 if (TARGET_SSSE3)
2004 target_flags |= MASK_SSE3;
2005
2006 /* Turn on SSE2 builtins for -msse3. */
2007 if (TARGET_SSE3)
2008 target_flags |= MASK_SSE2;
2009
2010 /* Turn on SSE builtins for -msse2. */
2011 if (TARGET_SSE2)
2012 target_flags |= MASK_SSE;
2013
2014 /* Turn on MMX builtins for -msse. */
2015 if (TARGET_SSE)
2016 {
2017 target_flags |= MASK_MMX & ~target_flags_explicit;
2018 x86_prefetch_sse = true;
2019 }
2020
2021 /* Turn on MMX builtins for 3Dnow. */
2022 if (TARGET_3DNOW)
2023 target_flags |= MASK_MMX;
2024
2025 if (TARGET_64BIT)
2026 {
2027 if (TARGET_ALIGN_DOUBLE)
2028 error ("-malign-double makes no sense in the 64bit mode");
2029 if (TARGET_RTD)
2030 error ("-mrtd calling convention not supported in the 64bit mode");
2031
2032 /* Enable by default the SSE and MMX builtins. Do allow the user to
--- 7209 unchanged lines hidden (view full) ---
9242 {
9243 op0 = gen_lowpart (V16QImode, op0);
9244 op1 = gen_lowpart (V16QImode, op1);
9245 emit_insn (gen_sse2_movdqu (op0, op1));
9246 return;
9247 }
9248
9249 if (TARGET_SSE2 && mode == V2DFmode)
9250 {
9251 rtx zero;
9252
9253 /* When SSE registers are split into halves, we can avoid
9254 writing to the top half twice. */
9255 if (TARGET_SSE_SPLIT_REGS)
9256 {
9257 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
9258 zero = op0;
9259 }
9260 else
--- 10 unchanged lines hidden (view full) ---
9271 }
9272
9273 m = adjust_address (op1, DFmode, 0);
9274 emit_insn (gen_sse2_loadlpd (op0, zero, m));
9275 m = adjust_address (op1, DFmode, 8);
9276 emit_insn (gen_sse2_loadhpd (op0, op0, m));
9277 }
9278 else
9279 {
9280 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
9281 emit_move_insn (op0, CONST0_RTX (mode));
9282 else
9283 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
9284
9285 if (mode != V4SFmode)
9286 op0 = gen_lowpart (V4SFmode, op0);
9287 m = adjust_address (op1, V2SFmode, 0);
--- 4540 unchanged lines hidden (view full) ---
13828 case PROCESSOR_PENTIUM:
13829 case PROCESSOR_K6:
13830 return 2;
13831
13832 case PROCESSOR_PENTIUMPRO:
13833 case PROCESSOR_PENTIUM4:
13834 case PROCESSOR_ATHLON:
13835 case PROCESSOR_K8:
13836 case PROCESSOR_NOCONA:
13837 case PROCESSOR_GENERIC32:
13838 case PROCESSOR_GENERIC64:
13839 return 3;
13840
13841 case PROCESSOR_CORE2:
13842 return 4;
13843
--- 182 unchanged lines hidden (view full) ---
14026 cost -= 2;
14027 else
14028 cost = 1;
14029 }
14030 break;
14031
14032 case PROCESSOR_ATHLON:
14033 case PROCESSOR_K8:
14034 case PROCESSOR_GENERIC32:
14035 case PROCESSOR_GENERIC64:
14036 memory = get_attr_memory (insn);
14037
14038 /* Show ability of reorder buffer to hide latency of load by executing
14039 in parallel with previous instruction in case
14040 previous instruction is not needed to compute the address. */
14041 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
--- 697 unchanged lines hidden (view full) ---
14739 IX86_BUILTIN_PSIGNB128,
14740 IX86_BUILTIN_PSIGNW128,
14741 IX86_BUILTIN_PSIGND128,
14742 IX86_BUILTIN_PALIGNR128,
14743 IX86_BUILTIN_PABSB128,
14744 IX86_BUILTIN_PABSW128,
14745 IX86_BUILTIN_PABSD128,
14746
14747 IX86_BUILTIN_VEC_INIT_V2SI,
14748 IX86_BUILTIN_VEC_INIT_V4HI,
14749 IX86_BUILTIN_VEC_INIT_V8QI,
14750 IX86_BUILTIN_VEC_EXT_V2DF,
14751 IX86_BUILTIN_VEC_EXT_V2DI,
14752 IX86_BUILTIN_VEC_EXT_V4SF,
14753 IX86_BUILTIN_VEC_EXT_V4SI,
14754 IX86_BUILTIN_VEC_EXT_V8HI,
--- 708 unchanged lines hidden (view full) ---
15463 tree int_ftype_v16qi
15464 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
15465 tree v16qi_ftype_pcchar
15466 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
15467 tree void_ftype_pchar_v16qi
15468 = build_function_type_list (void_type_node,
15469 pchar_type_node, V16QI_type_node, NULL_TREE);
15470
15471 tree float80_type;
15472 tree float128_type;
15473 tree ftype;
15474
15475 /* The __float80 type. */
15476 if (TYPE_MODE (long_double_type_node) == XFmode)
15477 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
15478 "__float80");
--- 320 unchanged lines hidden (view full) ---
15799 v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
15800
15801 /* SSSE3. */
15802 def_builtin (MASK_SSSE3, "__builtin_ia32_palignr128",
15803 v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PALIGNR128);
15804 def_builtin (MASK_SSSE3, "__builtin_ia32_palignr", di_ftype_di_di_int,
15805 IX86_BUILTIN_PALIGNR);
15806
15807 /* Access to the vec_init patterns. */
15808 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
15809 integer_type_node, NULL_TREE);
15810 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v2si",
15811 ftype, IX86_BUILTIN_VEC_INIT_V2SI);
15812
15813 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
15814 short_integer_type_node,
--- 480 unchanged lines hidden (view full) ---
16295 enum machine_mode mode ATTRIBUTE_UNUSED,
16296 int ignore ATTRIBUTE_UNUSED)
16297{
16298 const struct builtin_description *d;
16299 size_t i;
16300 enum insn_code icode;
16301 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
16302 tree arglist = TREE_OPERAND (exp, 1);
16303 tree arg0, arg1, arg2;
16304 rtx op0, op1, op2, pat;
16305 enum machine_mode tmode, mode0, mode1, mode2, mode3;
16306 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
16307
16308 switch (fcode)
16309 {
16310 case IX86_BUILTIN_EMMS:
16311 emit_insn (gen_mmx_emms ());
16312 return 0;
16313
--- 499 unchanged lines hidden (view full) ---
16813 target = gen_reg_rtx (mode);
16814 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, mode, 0),
16815 op0, op1, op2);
16816 if (! pat)
16817 return 0;
16818 emit_insn (pat);
16819 return target;
16820
16821 case IX86_BUILTIN_VEC_INIT_V2SI:
16822 case IX86_BUILTIN_VEC_INIT_V4HI:
16823 case IX86_BUILTIN_VEC_INIT_V8QI:
16824 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
16825
16826 case IX86_BUILTIN_VEC_EXT_V2DF:
16827 case IX86_BUILTIN_VEC_EXT_V2DI:
16828 case IX86_BUILTIN_VEC_EXT_V4SF:
--- 2671 unchanged lines hidden ---
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
--- 5 unchanged lines hidden (view full) ---
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING. If not, write to
19the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20Boston, MA 02110-1301, USA. */
21
22/* $FreeBSD: head/contrib/gcc/config/i386/i386.c 237021 2012-06-13 20:21:08Z pfg $ */
23
24#include "config.h"
25#include "system.h"
26#include "coretypes.h"
27#include "tm.h"
28#include "rtl.h"
29#include "tree.h"
30#include "tm_p.h"
--- 512 unchanged lines hidden (view full) ---
543 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
544 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
545 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
546 COSTS_N_INSNS (2), /* cost of FABS instruction. */
547 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
548 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
549};
550
551static const
552struct processor_costs pentium4_cost = {
553 COSTS_N_INSNS (1), /* cost of an add instruction */
554 COSTS_N_INSNS (3), /* cost of a lea instruction */
555 COSTS_N_INSNS (4), /* variable shift costs */
556 COSTS_N_INSNS (4), /* constant shift costs */
557 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
558 COSTS_N_INSNS (15), /* HI */
--- 270 unchanged lines hidden (view full) ---
829#define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
830#define m_GEODE (1<<PROCESSOR_GEODE)
831#define m_K6_GEODE (m_K6 | m_GEODE)
832#define m_K6 (1<<PROCESSOR_K6)
833#define m_ATHLON (1<<PROCESSOR_ATHLON)
834#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
835#define m_K8 (1<<PROCESSOR_K8)
836#define m_ATHLON_K8 (m_K8 | m_ATHLON)
837#define m_NOCONA (1<<PROCESSOR_NOCONA)
838#define m_CORE2 (1<<PROCESSOR_CORE2)
839#define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
840#define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
841#define m_GENERIC (m_GENERIC32 | m_GENERIC64)
842
843/* Generic instruction choice should be common subset of supported CPUs
844 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
845
846/* Leave is not affecting Nocona SPEC2000 results negatively, so enabling for
847 Generic64 seems like good code size tradeoff. We can't enable it for 32bit
848 generic because it is not working well with PPro base chips. */
849const int x86_use_leave = m_386 | m_K6_GEODE | m_ATHLON_K8 | m_CORE2 | m_GENERIC64;
850const int x86_push_memory = m_386 | m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
851const int x86_zero_extend_with_and = m_486 | m_PENT;
852const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */;
853const int x86_double_with_add = ~m_386;
854const int x86_use_bit_test = m_386;
855const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_CORE2 | m_GENERIC;
856const int x86_cmove = m_PPRO | m_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
857const int x86_3dnow_a = m_ATHLON_K8;
858const int x86_deep_branch = m_PPRO | m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
859/* Branch hints were put in P4 based on simulation result. But
860 after P4 was made, no performance benefit was observed with
861 branch hints. It also increases the code size. As the result,
862 icc never generates branch hints. */
863const int x86_branch_hints = 0;
864const int x86_use_sahf = m_PPRO | m_K6_GEODE | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_GENERIC | m_ATHLON_K8 ? */
865/* We probably ought to watch for partial register stalls on Generic32
866 compilation setting as well. However in current implementation the
867 partial register stalls are not eliminated very well - they can
868 be introduced via subregs synthesized by combine and can happen
869 in caller/callee saving sequences.
870 Because this option pays back little on PPro based chips and is in conflict
871 with partial reg. dependencies used by Athlon/P4 based chips, it is better
872 to leave it off for generic32 for now. */
873const int x86_partial_reg_stall = m_PPRO;
874const int x86_partial_flag_reg_stall = m_CORE2 | m_GENERIC;
875const int x86_use_himode_fiop = m_386 | m_486 | m_K6_GEODE;
876const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_CORE2 | m_GENERIC);
877const int x86_use_mov0 = m_K6;
878const int x86_use_cltd = ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC);
879const int x86_read_modify_write = ~m_PENT;
880const int x86_read_modify = ~(m_PENT | m_PPRO);
881const int x86_split_long_moves = m_PPRO;
882const int x86_promote_QImode = m_K6_GEODE | m_PENT | m_386 | m_486 | m_ATHLON_K8 | m_CORE2 | m_GENERIC; /* m_PENT4 ? */
883const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
884const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
885const int x86_qimode_math = ~(0);
886const int x86_promote_qi_regs = 0;
887/* On PPro this flag is meant to avoid partial register stalls. Just like
888 the x86_partial_reg_stall this option might be considered for Generic32
889 if our scheme for avoiding partial stalls was more effective. */
890const int x86_himode_math = ~(m_PPRO);
891const int x86_promote_hi_regs = m_PPRO;
892const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
893const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
894const int x86_add_esp_4 = m_ATHLON_K8 | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
895const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6_GEODE | m_386 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
896const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_GEODE);
897const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
898const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
899const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
900const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC;
901const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC;
902const int x86_shift1 = ~m_486;
903const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
904/* In Generic model we have an conflict here in between PPro/Pentium4 based chips
905 that thread 128bit SSE registers as single units versus K8 based chips that
906 divide SSE registers to two 64bit halves.
907 x86_sse_partial_reg_dependency promote all store destinations to be 128bit
908 to allow register renaming on 128bit SSE units, but usually results in one
909 extra microop on 64bit SSE units. Experimental results shows that disabling
910 this option on P4 brings over 20% SPECfp regression, while enabling it on
911 K8 brings roughly 2.4% regression that can be partly masked by careful scheduling
912 of moves. */
913const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
914/* Set for machines where the type and dependencies are resolved on SSE
915 register parts instead of whole registers, so we may maintain just
916 lower part of scalar values in proper format leaving the upper part
917 undefined. */
918const int x86_sse_split_regs = m_ATHLON_K8;
919const int x86_sse_typeless_stores = m_ATHLON_K8;
920const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
921const int x86_use_ffreep = m_ATHLON_K8;
922const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6_GEODE | m_CORE2;
923const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC);
924
925/* ??? Allowing interunit moves makes it all too easy for the compiler to put
926 integer data in xmm registers. Which results in pretty abysmal code. */
927const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */;
928
929const int x86_ext_80387_constants = m_K6_GEODE | m_ATHLON | m_PENT4 | m_NOCONA | m_CORE2 | m_PPRO | m_GENERIC32;
930/* Some CPU cores are not able to predict more than 4 branch instructions in
931 the 16 byte window. */
932const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
933const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC;
934const int x86_use_bt = m_ATHLON_K8;
935/* Compare and exchange was added for 80486. */
936const int x86_cmpxchg = ~m_386;
937/* Compare and exchange 8 bytes was added for pentium. */
938const int x86_cmpxchg8b = ~(m_386 | m_486);
939/* Compare and exchange 16 bytes was added for nocona. */
940const int x86_cmpxchg16b = m_NOCONA | m_CORE2;
941/* Exchange and add was added for 80486. */
942const int x86_xadd = ~m_386;
943const int x86_pad_returns = m_ATHLON_K8 | m_CORE2 | m_GENERIC;
944
945/* In case the average insn count for single function invocation is
946 lower than this constant, emit fast (but longer) prologue and
947 epilogue code. */
948#define FAST_PROLOGUE_INSN_COUNT 20
949
950/* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
951static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
--- 200 unchanged lines hidden (view full) ---
1152/* Which cpu are we scheduling for. */
1153enum processor_type ix86_tune;
1154/* Which instruction set architecture to use. */
1155enum processor_type ix86_arch;
1156
1157/* true if sse prefetch instruction is not NOOP. */
1158int x86_prefetch_sse;
1159
1160/* ix86_regparm_string as a number */
1161static int ix86_regparm;
1162
1163/* -mstackrealign option */
1164extern int ix86_force_align_arg_pointer;
1165static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer";
1166
1167/* Preferred alignment for stack boundary in bits. */
--- 338 unchanged lines hidden (view full) ---
1506 target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
1507 target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
1508 }
1509 return true;
1510
1511 case OPT_msse:
1512 if (!value)
1513 {
1514 target_flags &= ~(MASK_SSE2 | MASK_SSE3 | MASK_SSSE3);
1515 target_flags_explicit |= MASK_SSE2 | MASK_SSE3 | MASK_SSSE3;
1516 }
1517 return true;
1518
1519 case OPT_msse2:
1520 if (!value)
1521 {
1522 target_flags &= ~(MASK_SSE3 | MASK_SSSE3);
1523 target_flags_explicit |= MASK_SSE3 | MASK_SSSE3;
1524 }
1525 return true;
1526
1527 case OPT_msse3:
1528 if (!value)
1529 {
1530 target_flags &= ~MASK_SSSE3;
1531 target_flags_explicit |= MASK_SSSE3;
1532 }
1533 return true;
1534
1535 default:
1536 return true;
1537 }
1538}
1539
--- 35 unchanged lines hidden (view full) ---
1575 {&geode_cost, 0, 0, 0, 0, 0, 0, 0},
1576 {&k6_cost, 0, 0, 32, 7, 32, 7, 32},
1577 {&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
1578 {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
1579 {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
1580 {&nocona_cost, 0, 0, 0, 0, 0, 0, 0},
1581 {&core2_cost, 0, 0, 16, 7, 16, 7, 16},
1582 {&generic32_cost, 0, 0, 16, 7, 16, 7, 16},
1583 {&generic64_cost, 0, 0, 16, 7, 16, 7, 16}
1584 };
1585
1586 static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
1587 static struct pta
1588 {
1589 const char *const name; /* processor name or nickname. */
1590 const enum processor_type processor;
1591 const enum pta_flags
1592 {
1593 PTA_SSE = 1,
1594 PTA_SSE2 = 2,
1595 PTA_SSE3 = 4,
1596 PTA_MMX = 8,
1597 PTA_PREFETCH_SSE = 16,
1598 PTA_3DNOW = 32,
1599 PTA_3DNOW_A = 64,
1600 PTA_64BIT = 128,
1601 PTA_SSSE3 = 256
1602 } flags;
1603 }
1604 const processor_alias_table[] =
1605 {
1606 {"i386", PROCESSOR_I386, 0},
1607 {"i486", PROCESSOR_I486, 0},
1608 {"i586", PROCESSOR_PENTIUM, 0},
1609 {"pentium", PROCESSOR_PENTIUM, 0},
--- 10 unchanged lines hidden (view full) ---
1620 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE | PTA_SSE2},
1621 {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1622 | PTA_MMX | PTA_PREFETCH_SSE},
1623 {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1624 | PTA_MMX | PTA_PREFETCH_SSE},
1625 {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
1626 | PTA_MMX | PTA_PREFETCH_SSE},
1627 {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
1628 | PTA_MMX | PTA_PREFETCH_SSE},
1629 {"core2", PROCESSOR_CORE2, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
1630 | PTA_64BIT | PTA_MMX
1631 | PTA_PREFETCH_SSE},
1632 {"geode", PROCESSOR_GEODE, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1633 | PTA_3DNOW_A},
1634 {"k6", PROCESSOR_K6, PTA_MMX},
1635 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1636 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1637 {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1638 | PTA_3DNOW_A},
1639 {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
--- 18 unchanged lines hidden (view full) ---
1658 | PTA_SSE3 },
1659 {"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1660 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1661 {"athlon64-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1662 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
1663 | PTA_SSE3 },
1664 {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1665 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1666 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
1667 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
1668 };
1669
1670 int const pta_size = ARRAY_SIZE (processor_alias_table);
1671
1672#ifdef SUBTARGET_OVERRIDE_OPTIONS
1673 SUBTARGET_OVERRIDE_OPTIONS;
--- 146 unchanged lines hidden (view full) ---
1820 if (processor_alias_table[i].flags & PTA_SSE3
1821 && !(target_flags_explicit & MASK_SSE3))
1822 target_flags |= MASK_SSE3;
1823 if (processor_alias_table[i].flags & PTA_SSSE3
1824 && !(target_flags_explicit & MASK_SSSE3))
1825 target_flags |= MASK_SSSE3;
1826 if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
1827 x86_prefetch_sse = true;
1828 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1829 error ("CPU you selected does not support x86-64 "
1830 "instruction set");
1831 break;
1832 }
1833
1834 if (i == pta_size)
1835 error ("bad value (%s) for -march= switch", ix86_arch_string);
--- 162 unchanged lines hidden (view full) ---
1998 software floating point, don't use 387 inline intrinsics. */
1999 if (!TARGET_80387)
2000 target_flags |= MASK_NO_FANCY_MATH_387;
2001
2002 /* Turn on SSE3 builtins for -mssse3. */
2003 if (TARGET_SSSE3)
2004 target_flags |= MASK_SSE3;
2005
2006 /* Turn on SSE2 builtins for -msse3. */
2007 if (TARGET_SSE3)
2008 target_flags |= MASK_SSE2;
2009
2010 /* Turn on SSE builtins for -msse2. */
2011 if (TARGET_SSE2)
2012 target_flags |= MASK_SSE;
2013
2014 /* Turn on MMX builtins for -msse. */
2015 if (TARGET_SSE)
2016 {
2017 target_flags |= MASK_MMX & ~target_flags_explicit;
2018 x86_prefetch_sse = true;
2019 }
2020
2021 /* Turn on MMX builtins for 3Dnow. */
2022 if (TARGET_3DNOW)
2023 target_flags |= MASK_MMX;
2024
2025 if (TARGET_64BIT)
2026 {
2027 if (TARGET_ALIGN_DOUBLE)
2028 error ("-malign-double makes no sense in the 64bit mode");
2029 if (TARGET_RTD)
2030 error ("-mrtd calling convention not supported in the 64bit mode");
2031
2032 /* Enable by default the SSE and MMX builtins. Do allow the user to
--- 7209 unchanged lines hidden (view full) ---
9242 {
9243 op0 = gen_lowpart (V16QImode, op0);
9244 op1 = gen_lowpart (V16QImode, op1);
9245 emit_insn (gen_sse2_movdqu (op0, op1));
9246 return;
9247 }
9248
9249 if (TARGET_SSE2 && mode == V2DFmode)
9250 {
9251 rtx zero;
9252
9253 /* When SSE registers are split into halves, we can avoid
9254 writing to the top half twice. */
9255 if (TARGET_SSE_SPLIT_REGS)
9256 {
9257 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
9258 zero = op0;
9259 }
9260 else
--- 10 unchanged lines hidden (view full) ---
9271 }
9272
9273 m = adjust_address (op1, DFmode, 0);
9274 emit_insn (gen_sse2_loadlpd (op0, zero, m));
9275 m = adjust_address (op1, DFmode, 8);
9276 emit_insn (gen_sse2_loadhpd (op0, op0, m));
9277 }
9278 else
9279 {
9280 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
9281 emit_move_insn (op0, CONST0_RTX (mode));
9282 else
9283 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
9284
9285 if (mode != V4SFmode)
9286 op0 = gen_lowpart (V4SFmode, op0);
9287 m = adjust_address (op1, V2SFmode, 0);
--- 4540 unchanged lines hidden (view full) ---
13828 case PROCESSOR_PENTIUM:
13829 case PROCESSOR_K6:
13830 return 2;
13831
13832 case PROCESSOR_PENTIUMPRO:
13833 case PROCESSOR_PENTIUM4:
13834 case PROCESSOR_ATHLON:
13835 case PROCESSOR_K8:
13836 case PROCESSOR_NOCONA:
13837 case PROCESSOR_GENERIC32:
13838 case PROCESSOR_GENERIC64:
13839 return 3;
13840
13841 case PROCESSOR_CORE2:
13842 return 4;
13843
--- 182 unchanged lines hidden (view full) ---
14026 cost -= 2;
14027 else
14028 cost = 1;
14029 }
14030 break;
14031
14032 case PROCESSOR_ATHLON:
14033 case PROCESSOR_K8:
14034 case PROCESSOR_GENERIC32:
14035 case PROCESSOR_GENERIC64:
14036 memory = get_attr_memory (insn);
14037
14038 /* Show ability of reorder buffer to hide latency of load by executing
14039 in parallel with previous instruction in case
14040 previous instruction is not needed to compute the address. */
14041 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
--- 697 unchanged lines hidden (view full) ---
14739 IX86_BUILTIN_PSIGNB128,
14740 IX86_BUILTIN_PSIGNW128,
14741 IX86_BUILTIN_PSIGND128,
14742 IX86_BUILTIN_PALIGNR128,
14743 IX86_BUILTIN_PABSB128,
14744 IX86_BUILTIN_PABSW128,
14745 IX86_BUILTIN_PABSD128,
14746
14747 IX86_BUILTIN_VEC_INIT_V2SI,
14748 IX86_BUILTIN_VEC_INIT_V4HI,
14749 IX86_BUILTIN_VEC_INIT_V8QI,
14750 IX86_BUILTIN_VEC_EXT_V2DF,
14751 IX86_BUILTIN_VEC_EXT_V2DI,
14752 IX86_BUILTIN_VEC_EXT_V4SF,
14753 IX86_BUILTIN_VEC_EXT_V4SI,
14754 IX86_BUILTIN_VEC_EXT_V8HI,
--- 708 unchanged lines hidden (view full) ---
15463 tree int_ftype_v16qi
15464 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
15465 tree v16qi_ftype_pcchar
15466 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
15467 tree void_ftype_pchar_v16qi
15468 = build_function_type_list (void_type_node,
15469 pchar_type_node, V16QI_type_node, NULL_TREE);
15470
15471 tree float80_type;
15472 tree float128_type;
15473 tree ftype;
15474
15475 /* The __float80 type. */
15476 if (TYPE_MODE (long_double_type_node) == XFmode)
15477 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
15478 "__float80");
--- 320 unchanged lines hidden (view full) ---
15799 v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
15800
15801 /* SSSE3. */
15802 def_builtin (MASK_SSSE3, "__builtin_ia32_palignr128",
15803 v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PALIGNR128);
15804 def_builtin (MASK_SSSE3, "__builtin_ia32_palignr", di_ftype_di_di_int,
15805 IX86_BUILTIN_PALIGNR);
15806
15807 /* Access to the vec_init patterns. */
15808 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
15809 integer_type_node, NULL_TREE);
15810 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v2si",
15811 ftype, IX86_BUILTIN_VEC_INIT_V2SI);
15812
15813 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
15814 short_integer_type_node,
--- 480 unchanged lines hidden (view full) ---
16295 enum machine_mode mode ATTRIBUTE_UNUSED,
16296 int ignore ATTRIBUTE_UNUSED)
16297{
16298 const struct builtin_description *d;
16299 size_t i;
16300 enum insn_code icode;
16301 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
16302 tree arglist = TREE_OPERAND (exp, 1);
16303 tree arg0, arg1, arg2;
16304 rtx op0, op1, op2, pat;
16305 enum machine_mode tmode, mode0, mode1, mode2, mode3;
16306 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
16307
16308 switch (fcode)
16309 {
16310 case IX86_BUILTIN_EMMS:
16311 emit_insn (gen_mmx_emms ());
16312 return 0;
16313
--- 499 unchanged lines hidden (view full) ---
16813 target = gen_reg_rtx (mode);
16814 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, mode, 0),
16815 op0, op1, op2);
16816 if (! pat)
16817 return 0;
16818 emit_insn (pat);
16819 return target;
16820
16821 case IX86_BUILTIN_VEC_INIT_V2SI:
16822 case IX86_BUILTIN_VEC_INIT_V4HI:
16823 case IX86_BUILTIN_VEC_INIT_V8QI:
16824 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
16825
16826 case IX86_BUILTIN_VEC_EXT_V2DF:
16827 case IX86_BUILTIN_VEC_EXT_V2DI:
16828 case IX86_BUILTIN_VEC_EXT_V4SF:
--- 2671 unchanged lines hidden ---