| 12007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124341)
2
3 * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of
4 'AMD Family 10 core'.
5
|
12007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339)
2
3 * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3
4 and athlon64-sse3 as improved versions of k8, opteron and athlon64
5 with SSE3 instruction set support.
6 * doc/invoke.texi: Likewise.
7
| 62007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339)
7
8 * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3
9 and athlon64-sse3 as improved versions of k8, opteron and athlon64
10 with SSE3 instruction set support.
11 * doc/invoke.texi: Likewise.
12
|
| 132007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330)
14
15 * config/i386/i386.c (override_options): Tuning 32-byte loop
16 alignment for amdfam10 architecture. Increasing the max loop
17 alignment to 24 bytes.
18
|
82007-04-12 Richard Guenther <rguenther@suse.de> (r123736)
9
10 PR tree-optimization/24689
11 PR tree-optimization/31307
12 * fold-const.c (operand_equal_p): Compare INTEGER_CST array
13 indices by value.
14 * gimplify.c (canonicalize_addr_expr): To be consistent with
15 gimplify_compound_lval only set operands two and three of
16 ARRAY_REFs if they are not gimple_min_invariant. This makes
17 it never at this place.
18 * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise.
19
202007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639)
21
22 * config/i386/i386.c (ix86_handle_option): Handle SSSE3.
23
| 192007-04-12 Richard Guenther <rguenther@suse.de> (r123736)
20
21 PR tree-optimization/24689
22 PR tree-optimization/31307
23 * fold-const.c (operand_equal_p): Compare INTEGER_CST array
24 indices by value.
25 * gimplify.c (canonicalize_addr_expr): To be consistent with
26 gimplify_compound_lval only set operands two and three of
27 ARRAY_REFs if they are not gimple_min_invariant. This makes
28 it never at this place.
29 * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise.
30
312007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639)
32
33 * config/i386/i386.c (ix86_handle_option): Handle SSSE3.
34
|
| 352007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313)
36
37 * config.gcc: Accept barcelona as a variant of amdfam10.
38 * config/i386/i386.c (override_options): Likewise.
39 * doc/invoke.texi: Likewise.
40
412007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763)
42
43 * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10.
44 (bit_SSE4a): New.
45
|
242007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726)
25
26 * config/i386/xmmintrin.h: Make inclusion of emmintrin.h
27 conditional to __SSE2__.
28 (Entries below should have been added to first ChangeLog
29 entry for amdfam10 dated 2007-02-05)
30 * config/i386/emmintrin.h: Generate #error if __SSE2__ is not
31 defined.
32 * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not
33 defined.
34 * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not
35 defined.
36
372007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687)
38
39 * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2.
40
| 462007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726)
47
48 * config/i386/xmmintrin.h: Make inclusion of emmintrin.h
49 conditional to __SSE2__.
50 (Entries below should have been added to first ChangeLog
51 entry for amdfam10 dated 2007-02-05)
52 * config/i386/emmintrin.h: Generate #error if __SSE2__ is not
53 defined.
54 * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not
55 defined.
56 * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not
57 defined.
58
592007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687)
60
61 * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2.
62
|
| 632007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
64
65 * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8,
66 athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov,
67 athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul,
68 athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn,
69 athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8,
70 athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load,
71 athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8,
72 athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10.
73
742007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
75
76 * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse,
77 cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387,
78 swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse,
79 fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse,
80 x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed,
81 floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse,
82 floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1,
83 mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn,
84 umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn,
85 umuldi3_highpart_rex64, umulsi3_highpart_insn,
86 umulsi3_highpart_zext, smuldi3_highpart_rex64,
87 smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld,
88 x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse,
89 sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387,
90 sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387,
91 sqrtextenddfxf2_i387): Added amdfam10_decode.
92
93 * config/i386/athlon.md (athlon_idirect_amdfam10,
94 athlon_ivector_amdfam10, athlon_idirect_load_amdfam10,
95 athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10,
96 athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10,
97 athlon_ivector_store_amdfam10): New define_insn_reservation.
98 (athlon_idirect_loadmov, athlon_idirect_movstore): Added
99 amdfam10.
100
1012007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
102
103 * config/i386/athlon.md (athlon_call_amdfam10,
104 athlon_pop_amdfam10, athlon_lea_amdfam10): New
105 define_insn_reservation.
106 (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8,
107 athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI,
108 athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10.
109
1102007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
111
112 * config/i386/athlon.md (athlon_sseld_amdfam10,
113 athlon_mmxld_amdfam10, athlon_ssest_amdfam10,
114 athlon_mmxssest_short_amdfam10): New define_insn_reservation.
115
1162007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
117
118 * config/i386/athlon.md (athlon_sseins_amdfam10): New
119 define_insn_reservation.
120 * config/i386/i386.md (sseins): Added sseins to define_attr type
121 and define_attr unit.
122 * config/i386/sse.md: Set type attribute to sseins for insertq
123 and insertqi.
124
1252007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
126
127 * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10,
128 ssecmpvector_load_amdfam10, ssecmpvector_amdfam10,
129 ssecomi_load_amdfam10, ssecomi_amdfam10,
130 sseaddvector_load_amdfam10, sseaddvector_amdfam10): New
131 define_insn_reservation.
132 (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10.
133
1342007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
135
136 * config/i386/athlon.md (cvtss2sd_load_amdfam10,
137 cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10,
138 cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10,
139 cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10,
140 cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10,
141 cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New
142 define_insn_reservation.
143
144 * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si,
145 cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq,
146 cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq,
147 cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd,
148 cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute.
149
1502007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
151
152 * config/i386/athlon.md (athlon_ssedivvector_amdfam10,
153 athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10,
154 athlon_ssemulvector_load_amdfam10): New define_insn_reservation.
155 (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul,
156 athlon_ssemul_load_k8): Added amdfam10.
157
1582007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
159
160 * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro.
161 (x86_sse_unaligned_move_optimal): New variable.
162
163 * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for
164 m_AMDFAM10.
165 (ix86_expand_vector_move_misalign): Add code to generate movupd/movups
166 for unaligned vector SSE double/single precision loads for AMDFAM10.
167
1682007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
169
170 * config/i386/i386.h (TARGET_AMDFAM10): New macro.
171 (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10.
172 Define TARGET_CPU_DEFAULT_amdfam10.
173 (TARGET_CPU_DEFAULT_NAMES): Add amdfam10.
174 (processor_type): Add PROCESSOR_AMDFAM10.
175
176 * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match
177 processor_type in config/i386/i386.h.
178 Enable imul peepholes for TARGET_AMDFAM10.
179
180 * config.gcc: Add support for --with-cpu option for amdfam10.
181
182 * config/i386/i386.c (amdfam10_cost): New variable.
183 (m_AMDFAM10): New macro.
184 (m_ATHLON_K8_AMDFAM10): New macro.
185 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
186 x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop,
187 x86_promote_QImode, x86_integer_DFmode_moves,
188 x86_partial_reg_dependency, x86_memory_mismatch_stall,
189 x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387,
190 x86_sse_partial_reg_dependency, x86_sse_typeless_stores,
191 x86_use_ffreep, x86_use_incdec, x86_four_jump_limit,
192 x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns):
193 Enable/disable for amdfam10.
194 (override_options): Add amdfam10_cost to processor_target_table.
195 Set up PROCESSOR_AMDFAM10 for amdfam10 entry in
196 processor_alias_table.
197 (ix86_issue_rate): Add PROCESSOR_AMDFAM10.
198 (ix86_adjust_cost): Add code for amdfam10.
199
2002007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
201
202 * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm)
203 instruction set feature flag. Add new (-mpopcnt) flag for popcnt
204 instruction. Add new SSE4A (-msse4a) instruction set feature flag.
205 * config/i386/i386.h: Add builtin definition for SSE4A.
206 * config/i386/i386.md: Add support for ABM instructions
207 (popcnt and lzcnt).
208 * config/i386/sse.md: Add support for SSE4A instructions
209 (movntss, movntsd, extrq, insertq).
210 * config/i386/i386.c: Add support for ABM and SSE4A builtins.
211 Add -march=amdfam10 flag.
212 * config/i386/ammintrin.h: Add support for SSE4A intrinsics.
213 * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt
214 and amdfam10.
215 * doc/extend.texi: Add documentation for SSE4A builtins.
216
2172007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140)
218
219 * config/i386/i386.h (x86_cmpxchg16b): Remove const.
220 (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b.
221 * config/i386/i386.c (x86_cmpxchg16b): Remove const.
222 (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b
223 for CPUs that have PTA_CX16 set.
224
|
412007-01-17 Eric Christopher <echristo@apple.com> (r120846)
42
43 * config.gcc: Support core2 processor.
44
452006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial)
46
47 PR target/30040
48 * config/i386/driver-i386.c (bit_SSSE3): New.
49
| 2252007-01-17 Eric Christopher <echristo@apple.com> (r120846)
226
227 * config.gcc: Support core2 processor.
228
2292006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial)
230
231 PR target/30040
232 * config/i386/driver-i386.c (bit_SSSE3): New.
233
|
| 2342006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260)
235
236 * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2
237 and m_GENERIC64.
238
|
502006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973)
51
52 * doc/invoke.texi (core2): Add item.
53
54 * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New
55 macros.
56 (TARGET_CPU_CPP_BUILTINS): Add code for core2.
57 (TARGET_CPU_DEFAULT_generic): Change value.
58 (TARGET_CPU_DEFAULT_NAMES): Add core2.
59 (processor_type): Add new constant PROCESSOR_CORE2.
60
61 * config/i386/i386.md (cpu): Add core2.
62
63 * config/i386/i386.c (core2_cost): New initialized variable.
64 (m_CORE2): New macro.
65 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
66 x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop,
67 x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8,
68 x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves,
69 x86_partial_reg_dependency, x86_memory_mismatch_stall,
70 x86_accumulate_outgoing_args, x86_prologue_using_move,
71 x86_epilogue_using_move, x86_arch_always_fancy_math_387,
72 x86_sse_partial_reg_dependency, x86_rep_movl_optimal,
73 x86_use_incdec, x86_four_jump_limit, x86_schedule,
74 x86_pad_returns): Add m_CORE2.
75 (override_options): Add entries for Core2.
76 (ix86_issue_rate): Add case for Core2.
77
782006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090)
79
80 * config/i386/i386.h (TARGET_GEODE):
81 (TARGET_CPU_CPP_BUILTINS): Add code for geode.
82 (TARGET_CPU_DEFAULT_geode): New macro.
83 (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2,
84 TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon,
85 TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8,
86 TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott,
87 TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase
88 the macro values.
89 (TARGET_CPU_DEFAULT_NAMES): Add geode.
90 (processor_type): Add PROCESSOR_GEODE.
91
92 * config/i386/i386.md: Include geode.md.
93 (cpu): Add geode.
94
95 * config/i386/i386.c (geode_cost): New initialized global
96 variable.
97 (m_GEODE, m_K6_GEODE): New macros.
98 (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf,
99 x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4,
100 x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants,
101 x86_schedule): Use m_K6_GEODE instead of m_K6.
102 (x86_movx, x86_cmove): Set up m_GEODE.
103 (x86_integer_DFmode_moves): Clear m_GEODE.
104 (processor_target_table): Add entry for geode.
105 (processor_alias_table): Ditto.
106
107 * config/i386/geode.md: New file.
108
109 * doc/invoke.texi: Add entry about geode processor.
110
1112006-10-24 Richard Guenther <rguenther@suse.de> (r118001)
112
113 PR middle-end/28796
114 * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES
115 and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS
116 for deciding optimizations in consistency with fold-const.c
117 (fold_builtin_unordered_cmp): Likewise.
118
1192006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958)
120
121 * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers.
122 (x86_64-*-*): Likewise.
123
124 * config/i386/i386.c (pta_flags): Add PTA_SSSE3.
125 (override_options): Check SSSE3.
126 (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD,
127 IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD,
128 IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW,
129 IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB,
130 IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND,
131 IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW,
132 IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128,
133 IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128,
134 IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128,
135 IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128,
136 IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128,
137 IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128,
138 IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128,
139 IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and
140 IX86_BUILTIN_PABSD128.
141 (bdesc_2arg): Add SSSE3.
142 (bdesc_1arg): Likewise.
143 (ix86_init_mmx_sse_builtins): Support SSSE3.
144 (ix86_expand_builtin): Likewise.
145 * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise.
146
147 * config/i386/i386.md (UNSPEC_PSHUFB): New.
148 (UNSPEC_PSIGN): Likewise.
149 (UNSPEC_PALIGNR): Likewise.
150 Include mmx.md before sse.md.
151
152 * config/i386/i386.opt: Add -mssse3.
153
154 * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3.
155 (ssse3_phaddwv4hi3): Likewise.
156 (ssse3_phadddv4si3): Likewise.
157 (ssse3_phadddv2si3): Likewise.
158 (ssse3_phaddswv8hi3): Likewise.
159 (ssse3_phaddswv4hi3): Likewise.
160 (ssse3_phsubwv8hi3): Likewise.
161 (ssse3_phsubwv4hi3): Likewise.
162 (ssse3_phsubdv4si3): Likewise.
163 (ssse3_phsubdv2si3): Likewise.
164 (ssse3_phsubswv8hi3): Likewise.
165 (ssse3_phsubswv4hi3): Likewise.
166 (ssse3_pmaddubswv8hi3): Likewise.
167 (ssse3_pmaddubswv4hi3): Likewise.
168 (ssse3_pmulhrswv8hi3): Likewise.
169 (ssse3_pmulhrswv4hi3): Likewise.
170 (ssse3_pshufbv16qi3): Likewise.
171 (ssse3_pshufbv8qi3): Likewise.
172 (ssse3_psign<mode>3): Likewise.
173 (ssse3_psign<mode>3): Likewise.
174 (ssse3_palignrti): Likewise.
175 (ssse3_palignrdi): Likewise.
176 (abs<mode>2): Likewise.
177 (abs<mode>2): Likewise.
178
179 * config/i386/tmmintrin.h: New file.
180
181 * doc/extend.texi: Document SSSE3 built-in functions.
182
183 * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches.
184
| 2392006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973)
240
241 * doc/invoke.texi (core2): Add item.
242
243 * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New
244 macros.
245 (TARGET_CPU_CPP_BUILTINS): Add code for core2.
246 (TARGET_CPU_DEFAULT_generic): Change value.
247 (TARGET_CPU_DEFAULT_NAMES): Add core2.
248 (processor_type): Add new constant PROCESSOR_CORE2.
249
250 * config/i386/i386.md (cpu): Add core2.
251
252 * config/i386/i386.c (core2_cost): New initialized variable.
253 (m_CORE2): New macro.
254 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
255 x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop,
256 x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8,
257 x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves,
258 x86_partial_reg_dependency, x86_memory_mismatch_stall,
259 x86_accumulate_outgoing_args, x86_prologue_using_move,
260 x86_epilogue_using_move, x86_arch_always_fancy_math_387,
261 x86_sse_partial_reg_dependency, x86_rep_movl_optimal,
262 x86_use_incdec, x86_four_jump_limit, x86_schedule,
263 x86_pad_returns): Add m_CORE2.
264 (override_options): Add entries for Core2.
265 (ix86_issue_rate): Add case for Core2.
266
2672006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090)
268
269 * config/i386/i386.h (TARGET_GEODE):
270 (TARGET_CPU_CPP_BUILTINS): Add code for geode.
271 (TARGET_CPU_DEFAULT_geode): New macro.
272 (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2,
273 TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon,
274 TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8,
275 TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott,
276 TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase
277 the macro values.
278 (TARGET_CPU_DEFAULT_NAMES): Add geode.
279 (processor_type): Add PROCESSOR_GEODE.
280
281 * config/i386/i386.md: Include geode.md.
282 (cpu): Add geode.
283
284 * config/i386/i386.c (geode_cost): New initialized global
285 variable.
286 (m_GEODE, m_K6_GEODE): New macros.
287 (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf,
288 x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4,
289 x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants,
290 x86_schedule): Use m_K6_GEODE instead of m_K6.
291 (x86_movx, x86_cmove): Set up m_GEODE.
292 (x86_integer_DFmode_moves): Clear m_GEODE.
293 (processor_target_table): Add entry for geode.
294 (processor_alias_table): Ditto.
295
296 * config/i386/geode.md: New file.
297
298 * doc/invoke.texi: Add entry about geode processor.
299
3002006-10-24 Richard Guenther <rguenther@suse.de> (r118001)
301
302 PR middle-end/28796
303 * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES
304 and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS
305 for deciding optimizations in consistency with fold-const.c
306 (fold_builtin_unordered_cmp): Likewise.
307
3082006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958)
309
310 * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers.
311 (x86_64-*-*): Likewise.
312
313 * config/i386/i386.c (pta_flags): Add PTA_SSSE3.
314 (override_options): Check SSSE3.
315 (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD,
316 IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD,
317 IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW,
318 IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB,
319 IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND,
320 IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW,
321 IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128,
322 IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128,
323 IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128,
324 IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128,
325 IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128,
326 IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128,
327 IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128,
328 IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and
329 IX86_BUILTIN_PABSD128.
330 (bdesc_2arg): Add SSSE3.
331 (bdesc_1arg): Likewise.
332 (ix86_init_mmx_sse_builtins): Support SSSE3.
333 (ix86_expand_builtin): Likewise.
334 * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise.
335
336 * config/i386/i386.md (UNSPEC_PSHUFB): New.
337 (UNSPEC_PSIGN): Likewise.
338 (UNSPEC_PALIGNR): Likewise.
339 Include mmx.md before sse.md.
340
341 * config/i386/i386.opt: Add -mssse3.
342
343 * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3.
344 (ssse3_phaddwv4hi3): Likewise.
345 (ssse3_phadddv4si3): Likewise.
346 (ssse3_phadddv2si3): Likewise.
347 (ssse3_phaddswv8hi3): Likewise.
348 (ssse3_phaddswv4hi3): Likewise.
349 (ssse3_phsubwv8hi3): Likewise.
350 (ssse3_phsubwv4hi3): Likewise.
351 (ssse3_phsubdv4si3): Likewise.
352 (ssse3_phsubdv2si3): Likewise.
353 (ssse3_phsubswv8hi3): Likewise.
354 (ssse3_phsubswv4hi3): Likewise.
355 (ssse3_pmaddubswv8hi3): Likewise.
356 (ssse3_pmaddubswv4hi3): Likewise.
357 (ssse3_pmulhrswv8hi3): Likewise.
358 (ssse3_pmulhrswv4hi3): Likewise.
359 (ssse3_pshufbv16qi3): Likewise.
360 (ssse3_pshufbv8qi3): Likewise.
361 (ssse3_psign<mode>3): Likewise.
362 (ssse3_psign<mode>3): Likewise.
363 (ssse3_palignrti): Likewise.
364 (ssse3_palignrdi): Likewise.
365 (abs<mode>2): Likewise.
366 (abs<mode>2): Likewise.
367
368 * config/i386/tmmintrin.h: New file.
369
370 * doc/extend.texi: Document SSSE3 built-in functions.
371
372 * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches.
373
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1852006-10-22 H.J. Lu
| 3742006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959)
|
186
187 * config/i386/tmmintrin.h: Remove the duplicated content.
188
1892006-10-21 Richard Guenther <rguenther@suse.de> (r117932)
190
191 PR tree-optimization/3511
192 * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that
193 got new invariant arguments during PHI translation.
194
1952006-10-21 Richard Guenther <rguenther@suse.de> (r117929)
196
197 * builtins.c (fold_builtin_classify): Fix typo.
198
| 375
376 * config/i386/tmmintrin.h: Remove the duplicated content.
377
3782006-10-21 Richard Guenther <rguenther@suse.de> (r117932)
379
380 PR tree-optimization/3511
381 * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that
382 got new invariant arguments during PHI translation.
383
3842006-10-21 Richard Guenther <rguenther@suse.de> (r117929)
385
386 * builtins.c (fold_builtin_classify): Fix typo.
387
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