12007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124341)
2
3 * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of
4 'AMD Family 10 core'.
5
62007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339)
7
8 * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3
9 and athlon64-sse3 as improved versions of k8, opteron and athlon64
10 with SSE3 instruction set support.
11 * doc/invoke.texi: Likewise.
12
132007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330)
14
15 * config/i386/i386.c (override_options): Tuning 32-byte loop
16 alignment for amdfam10 architecture. Increasing the max loop
17 alignment to 24 bytes.
18
192007-04-12 Richard Guenther <rguenther@suse.de> (r123736)
20
21 PR tree-optimization/24689
22 PR tree-optimization/31307
23 * fold-const.c (operand_equal_p): Compare INTEGER_CST array
24 indices by value.
25 * gimplify.c (canonicalize_addr_expr): To be consistent with
26 gimplify_compound_lval only set operands two and three of
27 ARRAY_REFs if they are not gimple_min_invariant. This makes
28 it never at this place.
29 * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise.
30
312007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639)
32
33 * config/i386/i386.c (ix86_handle_option): Handle SSSE3.
34
352007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313)
36
37 * config.gcc: Accept barcelona as a variant of amdfam10.
38 * config/i386/i386.c (override_options): Likewise.
39 * doc/invoke.texi: Likewise.
40
412007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763)
42
43 * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10.
44 (bit_SSE4a): New.
45
462007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726)
47
48 * config/i386/xmmintrin.h: Make inclusion of emmintrin.h
49 conditional to __SSE2__.
50 (Entries below should have been added to first ChangeLog
51 entry for amdfam10 dated 2007-02-05)
52 * config/i386/emmintrin.h: Generate #error if __SSE2__ is not
53 defined.
54 * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not
55 defined.
56 * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not
57 defined.
58
592007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687)
60
61 * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2.
62
632007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
64
65 * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8,
66 athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov,
67 athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul,
68 athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn,
69 athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8,
70 athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load,
71 athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8,
72 athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10.
73
742007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
75
76 * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse,
77 cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387,
78 swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse,
79 fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse,
80 x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed,
81 floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse,
82 floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1,
83 mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn,
84 umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn,
85 umuldi3_highpart_rex64, umulsi3_highpart_insn,
86 umulsi3_highpart_zext, smuldi3_highpart_rex64,
87 smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld,
88 x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse,
89 sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387,
90 sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387,
91 sqrtextenddfxf2_i387): Added amdfam10_decode.
92
93 * config/i386/athlon.md (athlon_idirect_amdfam10,
94 athlon_ivector_amdfam10, athlon_idirect_load_amdfam10,
95 athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10,
96 athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10,
97 athlon_ivector_store_amdfam10): New define_insn_reservation.
98 (athlon_idirect_loadmov, athlon_idirect_movstore): Added
99 amdfam10.
100
1012007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
102
103 * config/i386/athlon.md (athlon_call_amdfam10,
104 athlon_pop_amdfam10, athlon_lea_amdfam10): New
105 define_insn_reservation.
106 (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8,
107 athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI,
108 athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10.
109
1102007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
111
112 * config/i386/athlon.md (athlon_sseld_amdfam10,
113 athlon_mmxld_amdfam10, athlon_ssest_amdfam10,
114 athlon_mmxssest_short_amdfam10): New define_insn_reservation.
115
1162007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
117
118 * config/i386/athlon.md (athlon_sseins_amdfam10): New
119 define_insn_reservation.
120 * config/i386/i386.md (sseins): Added sseins to define_attr type
121 and define_attr unit.
122 * config/i386/sse.md: Set type attribute to sseins for insertq
123 and insertqi.
124
1252007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
126
127 * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10,
128 ssecmpvector_load_amdfam10, ssecmpvector_amdfam10,
129 ssecomi_load_amdfam10, ssecomi_amdfam10,
130 sseaddvector_load_amdfam10, sseaddvector_amdfam10): New
131 define_insn_reservation.
132 (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10.
133
1342007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
135
136 * config/i386/athlon.md (cvtss2sd_load_amdfam10,
137 cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10,
138 cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10,
139 cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10,
140 cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10,
141 cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New
142 define_insn_reservation.
143
144 * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si,
145 cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq,
146 cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq,
147 cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd,
148 cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute.
149
1502007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
151
152 * config/i386/athlon.md (athlon_ssedivvector_amdfam10,
153 athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10,
154 athlon_ssemulvector_load_amdfam10): New define_insn_reservation.
155 (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul,
156 athlon_ssemul_load_k8): Added amdfam10.
157
1582007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
159
160 * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro.
161 (x86_sse_unaligned_move_optimal): New variable.
162
163 * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for
164 m_AMDFAM10.
165 (ix86_expand_vector_move_misalign): Add code to generate movupd/movups
166 for unaligned vector SSE double/single precision loads for AMDFAM10.
167
1682007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
169
170 * config/i386/i386.h (TARGET_AMDFAM10): New macro.
171 (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10.
172 Define TARGET_CPU_DEFAULT_amdfam10.
173 (TARGET_CPU_DEFAULT_NAMES): Add amdfam10.
174 (processor_type): Add PROCESSOR_AMDFAM10.
175
176 * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match
177 processor_type in config/i386/i386.h.
178 Enable imul peepholes for TARGET_AMDFAM10.
179
180 * config.gcc: Add support for --with-cpu option for amdfam10.
181
182 * config/i386/i386.c (amdfam10_cost): New variable.
183 (m_AMDFAM10): New macro.
184 (m_ATHLON_K8_AMDFAM10): New macro.
185 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
186 x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop,
187 x86_promote_QImode, x86_integer_DFmode_moves,
188 x86_partial_reg_dependency, x86_memory_mismatch_stall,
189 x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387,
190 x86_sse_partial_reg_dependency, x86_sse_typeless_stores,
191 x86_use_ffreep, x86_use_incdec, x86_four_jump_limit,
192 x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns):
193 Enable/disable for amdfam10.
194 (override_options): Add amdfam10_cost to processor_target_table.
195 Set up PROCESSOR_AMDFAM10 for amdfam10 entry in
196 processor_alias_table.
197 (ix86_issue_rate): Add PROCESSOR_AMDFAM10.
198 (ix86_adjust_cost): Add code for amdfam10.
199
2002007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
201
202 * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm)
203 instruction set feature flag. Add new (-mpopcnt) flag for popcnt
204 instruction. Add new SSE4A (-msse4a) instruction set feature flag.
205 * config/i386/i386.h: Add builtin definition for SSE4A.
206 * config/i386/i386.md: Add support for ABM instructions
207 (popcnt and lzcnt).
208 * config/i386/sse.md: Add support for SSE4A instructions
209 (movntss, movntsd, extrq, insertq).
210 * config/i386/i386.c: Add support for ABM and SSE4A builtins.
211 Add -march=amdfam10 flag.
212 * config/i386/ammintrin.h: Add support for SSE4A intrinsics.
213 * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt
214 and amdfam10.
215 * doc/extend.texi: Add documentation for SSE4A builtins.
216
2172007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140)
218
219 * config/i386/i386.h (x86_cmpxchg16b): Remove const.
220 (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b.
221 * config/i386/i386.c (x86_cmpxchg16b): Remove const.
222 (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b
223 for CPUs that have PTA_CX16 set.
224
2252007-01-17 Eric Christopher <echristo@apple.com> (r120846)
226
227 * config.gcc: Support core2 processor.
228
2292006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial)
230
231 PR target/30040
232 * config/i386/driver-i386.c (bit_SSSE3): New.
233
2342006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260)
235
236 * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2
237 and m_GENERIC64.
238
2392006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973)
240
241 * doc/invoke.texi (core2): Add item.
242
243 * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New
244 macros.
245 (TARGET_CPU_CPP_BUILTINS): Add code for core2.
246 (TARGET_CPU_DEFAULT_generic): Change value.
--- 119 unchanged lines hidden (view full) ---
366 (abs<mode>2): Likewise.
367
368 * config/i386/tmmintrin.h: New file.
369
370 * doc/extend.texi: Document SSSE3 built-in functions.
371
372 * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches.
373
3742006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959)
375
376 * config/i386/tmmintrin.h: Remove the duplicated content.
377
3782006-10-21 Richard Guenther <rguenther@suse.de> (r117932)
379
380 PR tree-optimization/3511
381 * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that
382 got new invariant arguments during PHI translation.
383
3842006-10-21 Richard Guenther <rguenther@suse.de> (r117929)
385
386 * builtins.c (fold_builtin_classify): Fix typo.
387
2
3 * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of
4 'AMD Family 10 core'.
5
62007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339)
7
8 * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3
9 and athlon64-sse3 as improved versions of k8, opteron and athlon64
10 with SSE3 instruction set support.
11 * doc/invoke.texi: Likewise.
12
132007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330)
14
15 * config/i386/i386.c (override_options): Tuning 32-byte loop
16 alignment for amdfam10 architecture. Increasing the max loop
17 alignment to 24 bytes.
18
192007-04-12 Richard Guenther <rguenther@suse.de> (r123736)
20
21 PR tree-optimization/24689
22 PR tree-optimization/31307
23 * fold-const.c (operand_equal_p): Compare INTEGER_CST array
24 indices by value.
25 * gimplify.c (canonicalize_addr_expr): To be consistent with
26 gimplify_compound_lval only set operands two and three of
27 ARRAY_REFs if they are not gimple_min_invariant. This makes
28 it never at this place.
29 * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise.
30
312007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639)
32
33 * config/i386/i386.c (ix86_handle_option): Handle SSSE3.
34
352007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313)
36
37 * config.gcc: Accept barcelona as a variant of amdfam10.
38 * config/i386/i386.c (override_options): Likewise.
39 * doc/invoke.texi: Likewise.
40
412007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763)
42
43 * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10.
44 (bit_SSE4a): New.
45
462007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726)
47
48 * config/i386/xmmintrin.h: Make inclusion of emmintrin.h
49 conditional to __SSE2__.
50 (Entries below should have been added to first ChangeLog
51 entry for amdfam10 dated 2007-02-05)
52 * config/i386/emmintrin.h: Generate #error if __SSE2__ is not
53 defined.
54 * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not
55 defined.
56 * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not
57 defined.
58
592007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687)
60
61 * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2.
62
632007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
64
65 * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8,
66 athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov,
67 athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul,
68 athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn,
69 athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8,
70 athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load,
71 athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8,
72 athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10.
73
742007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
75
76 * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse,
77 cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387,
78 swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse,
79 fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse,
80 x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed,
81 floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse,
82 floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1,
83 mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn,
84 umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn,
85 umuldi3_highpart_rex64, umulsi3_highpart_insn,
86 umulsi3_highpart_zext, smuldi3_highpart_rex64,
87 smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld,
88 x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse,
89 sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387,
90 sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387,
91 sqrtextenddfxf2_i387): Added amdfam10_decode.
92
93 * config/i386/athlon.md (athlon_idirect_amdfam10,
94 athlon_ivector_amdfam10, athlon_idirect_load_amdfam10,
95 athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10,
96 athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10,
97 athlon_ivector_store_amdfam10): New define_insn_reservation.
98 (athlon_idirect_loadmov, athlon_idirect_movstore): Added
99 amdfam10.
100
1012007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
102
103 * config/i386/athlon.md (athlon_call_amdfam10,
104 athlon_pop_amdfam10, athlon_lea_amdfam10): New
105 define_insn_reservation.
106 (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8,
107 athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI,
108 athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10.
109
1102007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
111
112 * config/i386/athlon.md (athlon_sseld_amdfam10,
113 athlon_mmxld_amdfam10, athlon_ssest_amdfam10,
114 athlon_mmxssest_short_amdfam10): New define_insn_reservation.
115
1162007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
117
118 * config/i386/athlon.md (athlon_sseins_amdfam10): New
119 define_insn_reservation.
120 * config/i386/i386.md (sseins): Added sseins to define_attr type
121 and define_attr unit.
122 * config/i386/sse.md: Set type attribute to sseins for insertq
123 and insertqi.
124
1252007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
126
127 * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10,
128 ssecmpvector_load_amdfam10, ssecmpvector_amdfam10,
129 ssecomi_load_amdfam10, ssecomi_amdfam10,
130 sseaddvector_load_amdfam10, sseaddvector_amdfam10): New
131 define_insn_reservation.
132 (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10.
133
1342007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
135
136 * config/i386/athlon.md (cvtss2sd_load_amdfam10,
137 cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10,
138 cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10,
139 cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10,
140 cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10,
141 cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New
142 define_insn_reservation.
143
144 * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si,
145 cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq,
146 cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq,
147 cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd,
148 cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute.
149
1502007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
151
152 * config/i386/athlon.md (athlon_ssedivvector_amdfam10,
153 athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10,
154 athlon_ssemulvector_load_amdfam10): New define_insn_reservation.
155 (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul,
156 athlon_ssemul_load_k8): Added amdfam10.
157
1582007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
159
160 * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro.
161 (x86_sse_unaligned_move_optimal): New variable.
162
163 * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for
164 m_AMDFAM10.
165 (ix86_expand_vector_move_misalign): Add code to generate movupd/movups
166 for unaligned vector SSE double/single precision loads for AMDFAM10.
167
1682007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
169
170 * config/i386/i386.h (TARGET_AMDFAM10): New macro.
171 (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10.
172 Define TARGET_CPU_DEFAULT_amdfam10.
173 (TARGET_CPU_DEFAULT_NAMES): Add amdfam10.
174 (processor_type): Add PROCESSOR_AMDFAM10.
175
176 * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match
177 processor_type in config/i386/i386.h.
178 Enable imul peepholes for TARGET_AMDFAM10.
179
180 * config.gcc: Add support for --with-cpu option for amdfam10.
181
182 * config/i386/i386.c (amdfam10_cost): New variable.
183 (m_AMDFAM10): New macro.
184 (m_ATHLON_K8_AMDFAM10): New macro.
185 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
186 x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop,
187 x86_promote_QImode, x86_integer_DFmode_moves,
188 x86_partial_reg_dependency, x86_memory_mismatch_stall,
189 x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387,
190 x86_sse_partial_reg_dependency, x86_sse_typeless_stores,
191 x86_use_ffreep, x86_use_incdec, x86_four_jump_limit,
192 x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns):
193 Enable/disable for amdfam10.
194 (override_options): Add amdfam10_cost to processor_target_table.
195 Set up PROCESSOR_AMDFAM10 for amdfam10 entry in
196 processor_alias_table.
197 (ix86_issue_rate): Add PROCESSOR_AMDFAM10.
198 (ix86_adjust_cost): Add code for amdfam10.
199
2002007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
201
202 * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm)
203 instruction set feature flag. Add new (-mpopcnt) flag for popcnt
204 instruction. Add new SSE4A (-msse4a) instruction set feature flag.
205 * config/i386/i386.h: Add builtin definition for SSE4A.
206 * config/i386/i386.md: Add support for ABM instructions
207 (popcnt and lzcnt).
208 * config/i386/sse.md: Add support for SSE4A instructions
209 (movntss, movntsd, extrq, insertq).
210 * config/i386/i386.c: Add support for ABM and SSE4A builtins.
211 Add -march=amdfam10 flag.
212 * config/i386/ammintrin.h: Add support for SSE4A intrinsics.
213 * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt
214 and amdfam10.
215 * doc/extend.texi: Add documentation for SSE4A builtins.
216
2172007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140)
218
219 * config/i386/i386.h (x86_cmpxchg16b): Remove const.
220 (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b.
221 * config/i386/i386.c (x86_cmpxchg16b): Remove const.
222 (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b
223 for CPUs that have PTA_CX16 set.
224
2252007-01-17 Eric Christopher <echristo@apple.com> (r120846)
226
227 * config.gcc: Support core2 processor.
228
2292006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial)
230
231 PR target/30040
232 * config/i386/driver-i386.c (bit_SSSE3): New.
233
2342006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260)
235
236 * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2
237 and m_GENERIC64.
238
2392006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973)
240
241 * doc/invoke.texi (core2): Add item.
242
243 * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New
244 macros.
245 (TARGET_CPU_CPP_BUILTINS): Add code for core2.
246 (TARGET_CPU_DEFAULT_generic): Change value.
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366 (abs<mode>2): Likewise.
367
368 * config/i386/tmmintrin.h: New file.
369
370 * doc/extend.texi: Document SSSE3 built-in functions.
371
372 * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches.
373
3742006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959)
375
376 * config/i386/tmmintrin.h: Remove the duplicated content.
377
3782006-10-21 Richard Guenther <rguenther@suse.de> (r117932)
379
380 PR tree-optimization/3511
381 * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that
382 got new invariant arguments during PHI translation.
383
3842006-10-21 Richard Guenther <rguenther@suse.de> (r117929)
385
386 * builtins.c (fold_builtin_classify): Fix typo.
387