34#endif /* not lint */
35
36#include <sys/types.h>
37
38#include <err.h>
39#include <stdio.h>
40#include <sys/agpio.h>
41#include <sys/pciio.h>
42
43#include <dev/agp/agpreg.h>
44#include <dev/pci/pcireg.h>
45
46#include "pciconf.h"
47
48static void list_ecaps(int fd, struct pci_conf *p);
49
50static void
51cap_power(int fd, struct pci_conf *p, uint8_t ptr)
52{
53 uint16_t cap, status;
54
55 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2);
56 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2);
57 printf("powerspec %d supports D0%s%s D3 current D%d",
58 cap & PCIM_PCAP_SPEC,
59 cap & PCIM_PCAP_D1SUPP ? " D1" : "",
60 cap & PCIM_PCAP_D2SUPP ? " D2" : "",
61 status & PCIM_PSTAT_DMASK);
62}
63
64static void
65cap_agp(int fd, struct pci_conf *p, uint8_t ptr)
66{
67 uint32_t status, command;
68
69 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4);
70 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4);
71 printf("AGP ");
72 if (AGP_MODE_GET_MODE_3(status)) {
73 printf("v3 ");
74 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x)
75 printf("8x ");
76 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x)
77 printf("4x ");
78 } else {
79 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x)
80 printf("4x ");
81 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x)
82 printf("2x ");
83 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x)
84 printf("1x ");
85 }
86 if (AGP_MODE_GET_SBA(status))
87 printf("SBA ");
88 if (AGP_MODE_GET_AGP(command)) {
89 printf("enabled at ");
90 if (AGP_MODE_GET_MODE_3(command)) {
91 printf("v3 ");
92 switch (AGP_MODE_GET_RATE(command)) {
93 case AGP_MODE_V3_RATE_8x:
94 printf("8x ");
95 break;
96 case AGP_MODE_V3_RATE_4x:
97 printf("4x ");
98 break;
99 }
100 } else
101 switch (AGP_MODE_GET_RATE(command)) {
102 case AGP_MODE_V2_RATE_4x:
103 printf("4x ");
104 break;
105 case AGP_MODE_V2_RATE_2x:
106 printf("2x ");
107 break;
108 case AGP_MODE_V2_RATE_1x:
109 printf("1x ");
110 break;
111 }
112 if (AGP_MODE_GET_SBA(command))
113 printf("SBA ");
114 } else
115 printf("disabled");
116}
117
118static void
119cap_vpd(int fd, struct pci_conf *p, uint8_t ptr)
120{
121
122 printf("VPD");
123}
124
125static void
126cap_msi(int fd, struct pci_conf *p, uint8_t ptr)
127{
128 uint16_t ctrl;
129 int msgnum;
130
131 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2);
132 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
133 printf("MSI supports %d message%s%s%s ", msgnum,
134 (msgnum == 1) ? "" : "s",
135 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
136 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : "");
137 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) {
138 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4);
139 printf("enabled with %d message%s", msgnum,
140 (msgnum == 1) ? "" : "s");
141 }
142}
143
144static void
145cap_pcix(int fd, struct pci_conf *p, uint8_t ptr)
146{
147 uint32_t status;
148 int comma, max_splits, max_burst_read;
149
150 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4);
151 printf("PCI-X ");
152 if (status & PCIXM_STATUS_64BIT)
153 printf("64-bit ");
154 if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
155 printf("bridge ");
156 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP |
157 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0)
158 printf("supports");
159 comma = 0;
160 if (status & PCIXM_STATUS_133CAP) {
161 printf("%s 133MHz", comma ? "," : "");
162 comma = 1;
163 }
164 if (status & PCIXM_STATUS_266CAP) {
165 printf("%s 266MHz", comma ? "," : "");
166 comma = 1;
167 }
168 if (status & PCIXM_STATUS_533CAP) {
169 printf("%s 533MHz", comma ? "," : "");
170 comma = 1;
171 }
172 if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
173 return;
174 switch (status & PCIXM_STATUS_MAX_READ) {
175 case PCIXM_STATUS_MAX_READ_512:
176 max_burst_read = 512;
177 break;
178 case PCIXM_STATUS_MAX_READ_1024:
179 max_burst_read = 1024;
180 break;
181 case PCIXM_STATUS_MAX_READ_2048:
182 max_burst_read = 2048;
183 break;
184 case PCIXM_STATUS_MAX_READ_4096:
185 max_burst_read = 4096;
186 break;
187 }
188 switch (status & PCIXM_STATUS_MAX_SPLITS) {
189 case PCIXM_STATUS_MAX_SPLITS_1:
190 max_splits = 1;
191 break;
192 case PCIXM_STATUS_MAX_SPLITS_2:
193 max_splits = 2;
194 break;
195 case PCIXM_STATUS_MAX_SPLITS_3:
196 max_splits = 3;
197 break;
198 case PCIXM_STATUS_MAX_SPLITS_4:
199 max_splits = 4;
200 break;
201 case PCIXM_STATUS_MAX_SPLITS_8:
202 max_splits = 8;
203 break;
204 case PCIXM_STATUS_MAX_SPLITS_12:
205 max_splits = 12;
206 break;
207 case PCIXM_STATUS_MAX_SPLITS_16:
208 max_splits = 16;
209 break;
210 case PCIXM_STATUS_MAX_SPLITS_32:
211 max_splits = 32;
212 break;
213 }
214 printf("%s %d burst read, %d split transaction%s", comma ? "," : "",
215 max_burst_read, max_splits, max_splits == 1 ? "" : "s");
216}
217
218static void
219cap_ht(int fd, struct pci_conf *p, uint8_t ptr)
220{
221 uint32_t reg;
222 uint16_t command;
223
224 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2);
225 printf("HT ");
226 if ((command & 0xe000) == PCIM_HTCAP_SLAVE)
227 printf("slave");
228 else if ((command & 0xe000) == PCIM_HTCAP_HOST)
229 printf("host");
230 else
231 switch (command & PCIM_HTCMD_CAP_MASK) {
232 case PCIM_HTCAP_SWITCH:
233 printf("switch");
234 break;
235 case PCIM_HTCAP_INTERRUPT:
236 printf("interrupt");
237 break;
238 case PCIM_HTCAP_REVISION_ID:
239 printf("revision ID");
240 break;
241 case PCIM_HTCAP_UNITID_CLUMPING:
242 printf("unit ID clumping");
243 break;
244 case PCIM_HTCAP_EXT_CONFIG_SPACE:
245 printf("extended config space");
246 break;
247 case PCIM_HTCAP_ADDRESS_MAPPING:
248 printf("address mapping");
249 break;
250 case PCIM_HTCAP_MSI_MAPPING:
251 printf("MSI %saddress window %s at 0x",
252 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "",
253 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" :
254 "disabled");
255 if (command & PCIM_HTCMD_MSI_FIXED)
256 printf("fee00000");
257 else {
258 reg = read_config(fd, &p->pc_sel,
259 ptr + PCIR_HTMSI_ADDRESS_HI, 4);
260 if (reg != 0)
261 printf("%08x", reg);
262 reg = read_config(fd, &p->pc_sel,
263 ptr + PCIR_HTMSI_ADDRESS_LO, 4);
264 printf("%08x", reg);
265 }
266 break;
267 case PCIM_HTCAP_DIRECT_ROUTE:
268 printf("direct route");
269 break;
270 case PCIM_HTCAP_VCSET:
271 printf("VC set");
272 break;
273 case PCIM_HTCAP_RETRY_MODE:
274 printf("retry mode");
275 break;
276 case PCIM_HTCAP_X86_ENCODING:
277 printf("X86 encoding");
278 break;
279 default:
280 printf("unknown %02x", command);
281 break;
282 }
283}
284
285static void
286cap_vendor(int fd, struct pci_conf *p, uint8_t ptr)
287{
288 uint8_t length;
289
290 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1);
291 printf("vendor (length %d)", length);
292 if (p->pc_vendor == 0x8086) {
293 /* Intel */
294 uint8_t version;
295
296 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA,
297 1);
298 printf(" Intel cap %d version %d", version >> 4, version & 0xf);
299 if (version >> 4 == 1 && length == 12) {
300 /* Feature Detection */
301 uint32_t fvec;
302 int comma;
303
304 comma = 0;
305 fvec = read_config(fd, &p->pc_sel, ptr +
306 PCIR_VENDOR_DATA + 5, 4);
307 printf("\n\t\t features:");
308 if (fvec & (1 << 0)) {
309 printf(" AMT");
310 comma = 1;
311 }
312 fvec = read_config(fd, &p->pc_sel, ptr +
313 PCIR_VENDOR_DATA + 1, 4);
314 if (fvec & (1 << 21)) {
315 printf("%s Quick Resume", comma ? "," : "");
316 comma = 1;
317 }
318 if (fvec & (1 << 18)) {
319 printf("%s SATA RAID-5", comma ? "," : "");
320 comma = 1;
321 }
322 if (fvec & (1 << 9)) {
323 printf("%s Mobile", comma ? "," : "");
324 comma = 1;
325 }
326 if (fvec & (1 << 7)) {
327 printf("%s 6 PCI-e x1 slots", comma ? "," : "");
328 comma = 1;
329 } else {
330 printf("%s 4 PCI-e x1 slots", comma ? "," : "");
331 comma = 1;
332 }
333 if (fvec & (1 << 5)) {
334 printf("%s SATA RAID-0/1/10", comma ? "," : "");
335 comma = 1;
336 }
337 if (fvec & (1 << 3)) {
338 printf("%s SATA AHCI", comma ? "," : "");
339 comma = 1;
340 }
341 }
342 }
343}
344
345static void
346cap_debug(int fd, struct pci_conf *p, uint8_t ptr)
347{
348 uint16_t debug_port;
349
350 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2);
351 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port &
352 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13));
353}
354
355static void
356cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr)
357{
358 uint32_t id;
359
360 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4);
361 printf("PCI Bridge card=0x%08x", id);
362}
363
364#define MAX_PAYLOAD(field) (128 << (field))
365
366static void
367cap_express(int fd, struct pci_conf *p, uint8_t ptr)
368{
369 uint32_t val;
370 uint16_t flags;
371
372 flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_FLAGS, 2);
373 printf("PCI-Express %d ", flags & PCIM_EXP_FLAGS_VERSION);
374 switch (flags & PCIM_EXP_FLAGS_TYPE) {
375 case PCIM_EXP_TYPE_ENDPOINT:
376 printf("endpoint");
377 break;
378 case PCIM_EXP_TYPE_LEGACY_ENDPOINT:
379 printf("legacy endpoint");
380 break;
381 case PCIM_EXP_TYPE_ROOT_PORT:
382 printf("root port");
383 break;
384 case PCIM_EXP_TYPE_UPSTREAM_PORT:
385 printf("upstream port");
386 break;
387 case PCIM_EXP_TYPE_DOWNSTREAM_PORT:
388 printf("downstream port");
389 break;
390 case PCIM_EXP_TYPE_PCI_BRIDGE:
391 printf("PCI bridge");
392 break;
393 case PCIM_EXP_TYPE_PCIE_BRIDGE:
394 printf("PCI to PCIe bridge");
395 break;
396 case PCIM_EXP_TYPE_ROOT_INT_EP:
397 printf("root endpoint");
398 break;
399 case PCIM_EXP_TYPE_ROOT_EC:
400 printf("event collector");
401 break;
402 default:
403 printf("type %d", (flags & PCIM_EXP_FLAGS_TYPE) >> 4);
404 break;
405 }
406 if (flags & PCIM_EXP_FLAGS_IRQ)
407 printf(" IRQ %d", (flags & PCIM_EXP_FLAGS_IRQ) >> 8);
408 val = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_DEVICE_CAP, 4);
409 flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_DEVICE_CTL, 2);
410 printf(" max data %d(%d)",
411 MAX_PAYLOAD((flags & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5),
412 MAX_PAYLOAD(val & PCIM_EXP_CAP_MAX_PAYLOAD));
413 val = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_LINK_CAP, 4);
414 flags = read_config(fd, &p->pc_sel, ptr+ PCIR_EXPRESS_LINK_STA, 2);
415 printf(" link x%d(x%d)", (flags & PCIM_LINK_STA_WIDTH) >> 4,
416 (val & PCIM_LINK_CAP_MAX_WIDTH) >> 4);
417}
418
419static void
420cap_msix(int fd, struct pci_conf *p, uint8_t ptr)
421{
422 uint32_t val;
423 uint16_t ctrl;
424 int msgnum, table_bar, pba_bar;
425
426 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2);
427 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
428 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4);
429 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
430 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4);
431 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
432 printf("MSI-X supports %d message%s ", msgnum,
433 (msgnum == 1) ? "" : "s");
434 if (table_bar == pba_bar)
435 printf("in map 0x%x", table_bar);
436 else
437 printf("in maps 0x%x and 0x%x", table_bar, pba_bar);
438 if (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE)
439 printf(" enabled");
440}
441
442static void
443cap_sata(int fd, struct pci_conf *p, uint8_t ptr)
444{
445
446 printf("SATA Index-Data Pair");
447}
448
449static void
450cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr)
451{
452 uint8_t cap;
453
454 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1);
455 printf("PCI Advanced Features:%s%s",
456 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "",
457 cap & PCIM_PCIAFCAP_TP ? " TP" : "");
458}
459
460void
461list_caps(int fd, struct pci_conf *p)
462{
| 34#endif /* not lint */
35
36#include <sys/types.h>
37
38#include <err.h>
39#include <stdio.h>
40#include <sys/agpio.h>
41#include <sys/pciio.h>
42
43#include <dev/agp/agpreg.h>
44#include <dev/pci/pcireg.h>
45
46#include "pciconf.h"
47
48static void list_ecaps(int fd, struct pci_conf *p);
49
50static void
51cap_power(int fd, struct pci_conf *p, uint8_t ptr)
52{
53 uint16_t cap, status;
54
55 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2);
56 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2);
57 printf("powerspec %d supports D0%s%s D3 current D%d",
58 cap & PCIM_PCAP_SPEC,
59 cap & PCIM_PCAP_D1SUPP ? " D1" : "",
60 cap & PCIM_PCAP_D2SUPP ? " D2" : "",
61 status & PCIM_PSTAT_DMASK);
62}
63
64static void
65cap_agp(int fd, struct pci_conf *p, uint8_t ptr)
66{
67 uint32_t status, command;
68
69 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4);
70 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4);
71 printf("AGP ");
72 if (AGP_MODE_GET_MODE_3(status)) {
73 printf("v3 ");
74 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x)
75 printf("8x ");
76 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x)
77 printf("4x ");
78 } else {
79 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x)
80 printf("4x ");
81 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x)
82 printf("2x ");
83 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x)
84 printf("1x ");
85 }
86 if (AGP_MODE_GET_SBA(status))
87 printf("SBA ");
88 if (AGP_MODE_GET_AGP(command)) {
89 printf("enabled at ");
90 if (AGP_MODE_GET_MODE_3(command)) {
91 printf("v3 ");
92 switch (AGP_MODE_GET_RATE(command)) {
93 case AGP_MODE_V3_RATE_8x:
94 printf("8x ");
95 break;
96 case AGP_MODE_V3_RATE_4x:
97 printf("4x ");
98 break;
99 }
100 } else
101 switch (AGP_MODE_GET_RATE(command)) {
102 case AGP_MODE_V2_RATE_4x:
103 printf("4x ");
104 break;
105 case AGP_MODE_V2_RATE_2x:
106 printf("2x ");
107 break;
108 case AGP_MODE_V2_RATE_1x:
109 printf("1x ");
110 break;
111 }
112 if (AGP_MODE_GET_SBA(command))
113 printf("SBA ");
114 } else
115 printf("disabled");
116}
117
118static void
119cap_vpd(int fd, struct pci_conf *p, uint8_t ptr)
120{
121
122 printf("VPD");
123}
124
125static void
126cap_msi(int fd, struct pci_conf *p, uint8_t ptr)
127{
128 uint16_t ctrl;
129 int msgnum;
130
131 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2);
132 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
133 printf("MSI supports %d message%s%s%s ", msgnum,
134 (msgnum == 1) ? "" : "s",
135 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
136 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : "");
137 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) {
138 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4);
139 printf("enabled with %d message%s", msgnum,
140 (msgnum == 1) ? "" : "s");
141 }
142}
143
144static void
145cap_pcix(int fd, struct pci_conf *p, uint8_t ptr)
146{
147 uint32_t status;
148 int comma, max_splits, max_burst_read;
149
150 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4);
151 printf("PCI-X ");
152 if (status & PCIXM_STATUS_64BIT)
153 printf("64-bit ");
154 if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
155 printf("bridge ");
156 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP |
157 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0)
158 printf("supports");
159 comma = 0;
160 if (status & PCIXM_STATUS_133CAP) {
161 printf("%s 133MHz", comma ? "," : "");
162 comma = 1;
163 }
164 if (status & PCIXM_STATUS_266CAP) {
165 printf("%s 266MHz", comma ? "," : "");
166 comma = 1;
167 }
168 if (status & PCIXM_STATUS_533CAP) {
169 printf("%s 533MHz", comma ? "," : "");
170 comma = 1;
171 }
172 if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
173 return;
174 switch (status & PCIXM_STATUS_MAX_READ) {
175 case PCIXM_STATUS_MAX_READ_512:
176 max_burst_read = 512;
177 break;
178 case PCIXM_STATUS_MAX_READ_1024:
179 max_burst_read = 1024;
180 break;
181 case PCIXM_STATUS_MAX_READ_2048:
182 max_burst_read = 2048;
183 break;
184 case PCIXM_STATUS_MAX_READ_4096:
185 max_burst_read = 4096;
186 break;
187 }
188 switch (status & PCIXM_STATUS_MAX_SPLITS) {
189 case PCIXM_STATUS_MAX_SPLITS_1:
190 max_splits = 1;
191 break;
192 case PCIXM_STATUS_MAX_SPLITS_2:
193 max_splits = 2;
194 break;
195 case PCIXM_STATUS_MAX_SPLITS_3:
196 max_splits = 3;
197 break;
198 case PCIXM_STATUS_MAX_SPLITS_4:
199 max_splits = 4;
200 break;
201 case PCIXM_STATUS_MAX_SPLITS_8:
202 max_splits = 8;
203 break;
204 case PCIXM_STATUS_MAX_SPLITS_12:
205 max_splits = 12;
206 break;
207 case PCIXM_STATUS_MAX_SPLITS_16:
208 max_splits = 16;
209 break;
210 case PCIXM_STATUS_MAX_SPLITS_32:
211 max_splits = 32;
212 break;
213 }
214 printf("%s %d burst read, %d split transaction%s", comma ? "," : "",
215 max_burst_read, max_splits, max_splits == 1 ? "" : "s");
216}
217
218static void
219cap_ht(int fd, struct pci_conf *p, uint8_t ptr)
220{
221 uint32_t reg;
222 uint16_t command;
223
224 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2);
225 printf("HT ");
226 if ((command & 0xe000) == PCIM_HTCAP_SLAVE)
227 printf("slave");
228 else if ((command & 0xe000) == PCIM_HTCAP_HOST)
229 printf("host");
230 else
231 switch (command & PCIM_HTCMD_CAP_MASK) {
232 case PCIM_HTCAP_SWITCH:
233 printf("switch");
234 break;
235 case PCIM_HTCAP_INTERRUPT:
236 printf("interrupt");
237 break;
238 case PCIM_HTCAP_REVISION_ID:
239 printf("revision ID");
240 break;
241 case PCIM_HTCAP_UNITID_CLUMPING:
242 printf("unit ID clumping");
243 break;
244 case PCIM_HTCAP_EXT_CONFIG_SPACE:
245 printf("extended config space");
246 break;
247 case PCIM_HTCAP_ADDRESS_MAPPING:
248 printf("address mapping");
249 break;
250 case PCIM_HTCAP_MSI_MAPPING:
251 printf("MSI %saddress window %s at 0x",
252 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "",
253 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" :
254 "disabled");
255 if (command & PCIM_HTCMD_MSI_FIXED)
256 printf("fee00000");
257 else {
258 reg = read_config(fd, &p->pc_sel,
259 ptr + PCIR_HTMSI_ADDRESS_HI, 4);
260 if (reg != 0)
261 printf("%08x", reg);
262 reg = read_config(fd, &p->pc_sel,
263 ptr + PCIR_HTMSI_ADDRESS_LO, 4);
264 printf("%08x", reg);
265 }
266 break;
267 case PCIM_HTCAP_DIRECT_ROUTE:
268 printf("direct route");
269 break;
270 case PCIM_HTCAP_VCSET:
271 printf("VC set");
272 break;
273 case PCIM_HTCAP_RETRY_MODE:
274 printf("retry mode");
275 break;
276 case PCIM_HTCAP_X86_ENCODING:
277 printf("X86 encoding");
278 break;
279 default:
280 printf("unknown %02x", command);
281 break;
282 }
283}
284
285static void
286cap_vendor(int fd, struct pci_conf *p, uint8_t ptr)
287{
288 uint8_t length;
289
290 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1);
291 printf("vendor (length %d)", length);
292 if (p->pc_vendor == 0x8086) {
293 /* Intel */
294 uint8_t version;
295
296 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA,
297 1);
298 printf(" Intel cap %d version %d", version >> 4, version & 0xf);
299 if (version >> 4 == 1 && length == 12) {
300 /* Feature Detection */
301 uint32_t fvec;
302 int comma;
303
304 comma = 0;
305 fvec = read_config(fd, &p->pc_sel, ptr +
306 PCIR_VENDOR_DATA + 5, 4);
307 printf("\n\t\t features:");
308 if (fvec & (1 << 0)) {
309 printf(" AMT");
310 comma = 1;
311 }
312 fvec = read_config(fd, &p->pc_sel, ptr +
313 PCIR_VENDOR_DATA + 1, 4);
314 if (fvec & (1 << 21)) {
315 printf("%s Quick Resume", comma ? "," : "");
316 comma = 1;
317 }
318 if (fvec & (1 << 18)) {
319 printf("%s SATA RAID-5", comma ? "," : "");
320 comma = 1;
321 }
322 if (fvec & (1 << 9)) {
323 printf("%s Mobile", comma ? "," : "");
324 comma = 1;
325 }
326 if (fvec & (1 << 7)) {
327 printf("%s 6 PCI-e x1 slots", comma ? "," : "");
328 comma = 1;
329 } else {
330 printf("%s 4 PCI-e x1 slots", comma ? "," : "");
331 comma = 1;
332 }
333 if (fvec & (1 << 5)) {
334 printf("%s SATA RAID-0/1/10", comma ? "," : "");
335 comma = 1;
336 }
337 if (fvec & (1 << 3)) {
338 printf("%s SATA AHCI", comma ? "," : "");
339 comma = 1;
340 }
341 }
342 }
343}
344
345static void
346cap_debug(int fd, struct pci_conf *p, uint8_t ptr)
347{
348 uint16_t debug_port;
349
350 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2);
351 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port &
352 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13));
353}
354
355static void
356cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr)
357{
358 uint32_t id;
359
360 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4);
361 printf("PCI Bridge card=0x%08x", id);
362}
363
364#define MAX_PAYLOAD(field) (128 << (field))
365
366static void
367cap_express(int fd, struct pci_conf *p, uint8_t ptr)
368{
369 uint32_t val;
370 uint16_t flags;
371
372 flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_FLAGS, 2);
373 printf("PCI-Express %d ", flags & PCIM_EXP_FLAGS_VERSION);
374 switch (flags & PCIM_EXP_FLAGS_TYPE) {
375 case PCIM_EXP_TYPE_ENDPOINT:
376 printf("endpoint");
377 break;
378 case PCIM_EXP_TYPE_LEGACY_ENDPOINT:
379 printf("legacy endpoint");
380 break;
381 case PCIM_EXP_TYPE_ROOT_PORT:
382 printf("root port");
383 break;
384 case PCIM_EXP_TYPE_UPSTREAM_PORT:
385 printf("upstream port");
386 break;
387 case PCIM_EXP_TYPE_DOWNSTREAM_PORT:
388 printf("downstream port");
389 break;
390 case PCIM_EXP_TYPE_PCI_BRIDGE:
391 printf("PCI bridge");
392 break;
393 case PCIM_EXP_TYPE_PCIE_BRIDGE:
394 printf("PCI to PCIe bridge");
395 break;
396 case PCIM_EXP_TYPE_ROOT_INT_EP:
397 printf("root endpoint");
398 break;
399 case PCIM_EXP_TYPE_ROOT_EC:
400 printf("event collector");
401 break;
402 default:
403 printf("type %d", (flags & PCIM_EXP_FLAGS_TYPE) >> 4);
404 break;
405 }
406 if (flags & PCIM_EXP_FLAGS_IRQ)
407 printf(" IRQ %d", (flags & PCIM_EXP_FLAGS_IRQ) >> 8);
408 val = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_DEVICE_CAP, 4);
409 flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_DEVICE_CTL, 2);
410 printf(" max data %d(%d)",
411 MAX_PAYLOAD((flags & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5),
412 MAX_PAYLOAD(val & PCIM_EXP_CAP_MAX_PAYLOAD));
413 val = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_LINK_CAP, 4);
414 flags = read_config(fd, &p->pc_sel, ptr+ PCIR_EXPRESS_LINK_STA, 2);
415 printf(" link x%d(x%d)", (flags & PCIM_LINK_STA_WIDTH) >> 4,
416 (val & PCIM_LINK_CAP_MAX_WIDTH) >> 4);
417}
418
419static void
420cap_msix(int fd, struct pci_conf *p, uint8_t ptr)
421{
422 uint32_t val;
423 uint16_t ctrl;
424 int msgnum, table_bar, pba_bar;
425
426 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2);
427 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
428 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4);
429 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
430 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4);
431 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
432 printf("MSI-X supports %d message%s ", msgnum,
433 (msgnum == 1) ? "" : "s");
434 if (table_bar == pba_bar)
435 printf("in map 0x%x", table_bar);
436 else
437 printf("in maps 0x%x and 0x%x", table_bar, pba_bar);
438 if (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE)
439 printf(" enabled");
440}
441
442static void
443cap_sata(int fd, struct pci_conf *p, uint8_t ptr)
444{
445
446 printf("SATA Index-Data Pair");
447}
448
449static void
450cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr)
451{
452 uint8_t cap;
453
454 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1);
455 printf("PCI Advanced Features:%s%s",
456 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "",
457 cap & PCIM_PCIAFCAP_TP ? " TP" : "");
458}
459
460void
461list_caps(int fd, struct pci_conf *p)
462{
|
477 ptr = PCIR_CAP_PTR_2;
478 break;
479 default:
480 errx(1, "list_caps: bad header type");
481 }
482
483 /* Walk the capability list. */
484 ptr = read_config(fd, &p->pc_sel, ptr, 1);
485 while (ptr != 0 && ptr != 0xff) {
486 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
487 printf(" cap %02x[%02x] = ", cap, ptr);
488 switch (cap) {
489 case PCIY_PMG:
490 cap_power(fd, p, ptr);
491 break;
492 case PCIY_AGP:
493 cap_agp(fd, p, ptr);
494 break;
495 case PCIY_VPD:
496 cap_vpd(fd, p, ptr);
497 break;
498 case PCIY_MSI:
499 cap_msi(fd, p, ptr);
500 break;
501 case PCIY_PCIX:
502 cap_pcix(fd, p, ptr);
503 break;
504 case PCIY_HT:
505 cap_ht(fd, p, ptr);
506 break;
507 case PCIY_VENDOR:
508 cap_vendor(fd, p, ptr);
509 break;
510 case PCIY_DEBUG:
511 cap_debug(fd, p, ptr);
512 break;
513 case PCIY_SUBVENDOR:
514 cap_subvendor(fd, p, ptr);
515 break;
516 case PCIY_EXPRESS:
517 cap_express(fd, p, ptr);
518 break;
519 case PCIY_MSIX:
520 cap_msix(fd, p, ptr);
521 break;
522 case PCIY_SATA:
523 cap_sata(fd, p, ptr);
524 break;
525 case PCIY_PCIAF:
526 cap_pciaf(fd, p, ptr);
527 break;
528 default:
529 printf("unknown");
530 break;
531 }
532 printf("\n");
533 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);
534 }
535
536 list_ecaps(fd, p);
537}
538
539/* From <sys/systm.h>. */
540static __inline uint32_t
541bitcount32(uint32_t x)
542{
543
544 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1);
545 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2);
546 x = (x + (x >> 4)) & 0x0f0f0f0f;
547 x = (x + (x >> 8));
548 x = (x + (x >> 16)) & 0x000000ff;
549 return (x);
550}
551
552static void
553ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
554{
555 uint32_t sta, mask;
556
557 printf("AER %d", ver);
558 if (ver != 1)
559 return;
560 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4);
561 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4);
562 printf(" %d fatal", bitcount32(sta & mask));
563 printf(" %d non-fatal", bitcount32(sta & ~mask));
564 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4);
565 printf(" %d corrected", bitcount32(sta));
566}
567
568static void
569ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
570{
571 uint32_t cap1;
572
573 printf("VC %d", ver);
574 if (ver != 1)
575 return;
576 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4);
577 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT);
578 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0)
579 printf(" lowpri VC0-VC%d",
580 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4);
581}
582
583static void
584ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
585{
586 uint32_t high, low;
587
588 printf("Serial %d", ver);
589 if (ver != 1)
590 return;
591 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4);
592 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4);
593 printf(" %08x%08x", high, low);
594}
595
596static void
597list_ecaps(int fd, struct pci_conf *p)
598{
599 uint32_t ecap;
600 uint16_t ptr;
601
602 ptr = PCIR_EXTCAP;
603 ecap = read_config(fd, &p->pc_sel, ptr, 4);
604 if (ecap == 0xffffffff || ecap == 0)
605 return;
606 for (;;) {
607 printf("ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr);
608 switch (PCI_EXTCAP_ID(ecap)) {
609 case PCIZ_AER:
610 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap));
611 break;
612 case PCIZ_VC:
613 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap));
614 break;
615 case PCIZ_SERNUM:
616 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap));
617 break;
618 default:
619 printf("unknown %d", PCI_EXTCAP_VER(ecap));
620 break;
621 }
622 printf("\n");
623 ptr = PCI_EXTCAP_NEXTPTR(ecap);
624 if (ptr == 0)
625 break;
626 ecap = read_config(fd, &p->pc_sel, ptr, 4);
627 }
628}
| 477 ptr = PCIR_CAP_PTR_2;
478 break;
479 default:
480 errx(1, "list_caps: bad header type");
481 }
482
483 /* Walk the capability list. */
484 ptr = read_config(fd, &p->pc_sel, ptr, 1);
485 while (ptr != 0 && ptr != 0xff) {
486 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
487 printf(" cap %02x[%02x] = ", cap, ptr);
488 switch (cap) {
489 case PCIY_PMG:
490 cap_power(fd, p, ptr);
491 break;
492 case PCIY_AGP:
493 cap_agp(fd, p, ptr);
494 break;
495 case PCIY_VPD:
496 cap_vpd(fd, p, ptr);
497 break;
498 case PCIY_MSI:
499 cap_msi(fd, p, ptr);
500 break;
501 case PCIY_PCIX:
502 cap_pcix(fd, p, ptr);
503 break;
504 case PCIY_HT:
505 cap_ht(fd, p, ptr);
506 break;
507 case PCIY_VENDOR:
508 cap_vendor(fd, p, ptr);
509 break;
510 case PCIY_DEBUG:
511 cap_debug(fd, p, ptr);
512 break;
513 case PCIY_SUBVENDOR:
514 cap_subvendor(fd, p, ptr);
515 break;
516 case PCIY_EXPRESS:
517 cap_express(fd, p, ptr);
518 break;
519 case PCIY_MSIX:
520 cap_msix(fd, p, ptr);
521 break;
522 case PCIY_SATA:
523 cap_sata(fd, p, ptr);
524 break;
525 case PCIY_PCIAF:
526 cap_pciaf(fd, p, ptr);
527 break;
528 default:
529 printf("unknown");
530 break;
531 }
532 printf("\n");
533 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);
534 }
535
536 list_ecaps(fd, p);
537}
538
539/* From <sys/systm.h>. */
540static __inline uint32_t
541bitcount32(uint32_t x)
542{
543
544 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1);
545 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2);
546 x = (x + (x >> 4)) & 0x0f0f0f0f;
547 x = (x + (x >> 8));
548 x = (x + (x >> 16)) & 0x000000ff;
549 return (x);
550}
551
552static void
553ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
554{
555 uint32_t sta, mask;
556
557 printf("AER %d", ver);
558 if (ver != 1)
559 return;
560 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4);
561 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4);
562 printf(" %d fatal", bitcount32(sta & mask));
563 printf(" %d non-fatal", bitcount32(sta & ~mask));
564 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4);
565 printf(" %d corrected", bitcount32(sta));
566}
567
568static void
569ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
570{
571 uint32_t cap1;
572
573 printf("VC %d", ver);
574 if (ver != 1)
575 return;
576 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4);
577 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT);
578 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0)
579 printf(" lowpri VC0-VC%d",
580 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4);
581}
582
583static void
584ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
585{
586 uint32_t high, low;
587
588 printf("Serial %d", ver);
589 if (ver != 1)
590 return;
591 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4);
592 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4);
593 printf(" %08x%08x", high, low);
594}
595
596static void
597list_ecaps(int fd, struct pci_conf *p)
598{
599 uint32_t ecap;
600 uint16_t ptr;
601
602 ptr = PCIR_EXTCAP;
603 ecap = read_config(fd, &p->pc_sel, ptr, 4);
604 if (ecap == 0xffffffff || ecap == 0)
605 return;
606 for (;;) {
607 printf("ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr);
608 switch (PCI_EXTCAP_ID(ecap)) {
609 case PCIZ_AER:
610 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap));
611 break;
612 case PCIZ_VC:
613 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap));
614 break;
615 case PCIZ_SERNUM:
616 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap));
617 break;
618 default:
619 printf("unknown %d", PCI_EXTCAP_VER(ecap));
620 break;
621 }
622 printf("\n");
623 ptr = PCI_EXTCAP_NEXTPTR(ecap);
624 if (ptr == 0)
625 break;
626 ecap = read_config(fd, &p->pc_sel, ptr, 4);
627 }
628}
|