370 for (i = 0; i < sc->ports; i++) {
371 sc->port[i].ie = 0;
372 sc->port[i].is = 0;
373 ahci_port_reset(&sc->port[i]);
374 }
375}
376
377static void
378ata_string(uint8_t *dest, const char *src, int len)
379{
380 int i;
381
382 for (i = 0; i < len; i++) {
383 if (*src)
384 dest[i ^ 1] = *src++;
385 else
386 dest[i ^ 1] = ' ';
387 }
388}
389
390static void
391atapi_string(uint8_t *dest, const char *src, int len)
392{
393 int i;
394
395 for (i = 0; i < len; i++) {
396 if (*src)
397 dest[i] = *src++;
398 else
399 dest[i] = ' ';
400 }
401}
402
403static void
404ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
405 int seek)
406{
407 struct ahci_ioreq *aior;
408 struct blockif_req *breq;
409 struct pci_ahci_softc *sc;
410 struct ahci_prdt_entry *prdt;
411 struct ahci_cmd_hdr *hdr;
412 uint64_t lba;
413 uint32_t len;
414 int i, err, iovcnt, ncq, readop;
415
416 sc = p->pr_sc;
417 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
418 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
419 ncq = 0;
420 readop = 1;
421
422 prdt += seek;
423 if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
424 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
425 readop = 0;
426
427 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
428 cfis[2] == ATA_READ_FPDMA_QUEUED) {
429 lba = ((uint64_t)cfis[10] << 40) |
430 ((uint64_t)cfis[9] << 32) |
431 ((uint64_t)cfis[8] << 24) |
432 ((uint64_t)cfis[6] << 16) |
433 ((uint64_t)cfis[5] << 8) |
434 cfis[4];
435 len = cfis[11] << 8 | cfis[3];
436 if (!len)
437 len = 65536;
438 ncq = 1;
439 } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
440 lba = ((uint64_t)cfis[10] << 40) |
441 ((uint64_t)cfis[9] << 32) |
442 ((uint64_t)cfis[8] << 24) |
443 ((uint64_t)cfis[6] << 16) |
444 ((uint64_t)cfis[5] << 8) |
445 cfis[4];
446 len = cfis[13] << 8 | cfis[12];
447 if (!len)
448 len = 65536;
449 } else {
450 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
451 (cfis[5] << 8) | cfis[4];
452 len = cfis[12];
453 if (!len)
454 len = 256;
455 }
456 lba *= blockif_sectsz(p->bctx);
457 len *= blockif_sectsz(p->bctx);
458
459 /*
460 * Pull request off free list
461 */
462 aior = STAILQ_FIRST(&p->iofhd);
463 assert(aior != NULL);
464 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
465 aior->cfis = cfis;
466 aior->slot = slot;
467 aior->len = len;
468 aior->done = done;
469 breq = &aior->io_req;
470 breq->br_offset = lba + done;
471 iovcnt = hdr->prdtl - seek;
472 if (iovcnt > BLOCKIF_IOV_MAX) {
473 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
474 iovcnt = BLOCKIF_IOV_MAX;
475 /*
476 * Mark this command in-flight.
477 */
478 p->pending |= 1 << slot;
479 } else
480 aior->prdtl = 0;
481 breq->br_iovcnt = iovcnt;
482
483 /*
484 * Build up the iovec based on the prdt
485 */
486 for (i = 0; i < iovcnt; i++) {
487 uint32_t dbcsz;
488
489 dbcsz = (prdt->dbc & DBCMASK) + 1;
490 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
491 prdt->dba, dbcsz);
492 breq->br_iov[i].iov_len = dbcsz;
493 aior->done += dbcsz;
494 prdt++;
495 }
496 if (readop)
497 err = blockif_read(p->bctx, breq);
498 else
499 err = blockif_write(p->bctx, breq);
500 assert(err == 0);
501
502 if (ncq)
503 p->ci &= ~(1 << slot);
504}
505
506static void
507ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
508{
509 struct ahci_ioreq *aior;
510 struct blockif_req *breq;
511 int err;
512
513 /*
514 * Pull request off free list
515 */
516 aior = STAILQ_FIRST(&p->iofhd);
517 assert(aior != NULL);
518 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
519 aior->cfis = cfis;
520 aior->slot = slot;
521 aior->len = 0;
522 aior->done = 0;
523 aior->prdtl = 0;
524 breq = &aior->io_req;
525
526 err = blockif_flush(p->bctx, breq);
527 assert(err == 0);
528}
529
530static inline void
531write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
532 void *buf, int size)
533{
534 struct ahci_cmd_hdr *hdr;
535 struct ahci_prdt_entry *prdt;
536 void *from;
537 int i, len;
538
539 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
540 len = size;
541 from = buf;
542 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
543 for (i = 0; i < hdr->prdtl && len; i++) {
544 uint8_t *ptr;
545 uint32_t dbcsz;
546 int sublen;
547
548 dbcsz = (prdt->dbc & DBCMASK) + 1;
549 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
550 sublen = len < dbcsz ? len : dbcsz;
551 memcpy(ptr, from, sublen);
552 len -= sublen;
553 from += sublen;
554 prdt++;
555 }
556 hdr->prdbc = size - len;
557}
558
559static void
560handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
561{
562 struct ahci_cmd_hdr *hdr;
563
564 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
565 if (p->atapi || hdr->prdtl == 0) {
566 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
567 p->is |= AHCI_P_IX_TFE;
568 } else {
569 uint16_t buf[256];
570 uint64_t sectors;
571
572 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
573 memset(buf, 0, sizeof(buf));
574 buf[0] = 0x0040;
575 /* TODO emulate different serial? */
576 ata_string((uint8_t *)(buf+10), "123456", 20);
577 ata_string((uint8_t *)(buf+23), "001", 8);
578 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
579 buf[47] = (0x8000 | 128);
580 buf[48] = 0x1;
581 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
582 buf[50] = (1 << 14);
583 buf[53] = (1 << 1 | 1 << 2);
584 if (p->mult_sectors)
585 buf[59] = (0x100 | p->mult_sectors);
586 buf[60] = sectors;
587 buf[61] = (sectors >> 16);
588 buf[63] = 0x7;
589 if (p->xfermode & ATA_WDMA0)
590 buf[63] |= (1 << ((p->xfermode & 7) + 8));
591 buf[64] = 0x3;
592 buf[65] = 100;
593 buf[66] = 100;
594 buf[67] = 100;
595 buf[68] = 100;
596 buf[75] = 31;
597 buf[76] = (1 << 8 | 1 << 2);
598 buf[80] = 0x1f0;
599 buf[81] = 0x28;
600 buf[82] = (1 << 5 | 1 << 14);
601 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14);
602 buf[84] = (1 << 14);
603 buf[85] = (1 << 5 | 1 << 14);
604 buf[86] = (1 << 10 | 1 << 12 | 1 << 13);
605 buf[87] = (1 << 14);
606 buf[88] = 0x7f;
607 if (p->xfermode & ATA_UDMA0)
608 buf[88] |= (1 << ((p->xfermode & 7) + 8));
609 buf[93] = (1 | 1 <<14);
610 buf[100] = sectors;
611 buf[101] = (sectors >> 16);
612 buf[102] = (sectors >> 32);
613 buf[103] = (sectors >> 48);
614 ahci_write_fis_piosetup(p);
615 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
616 p->tfd = ATA_S_DSC | ATA_S_READY;
617 p->is |= AHCI_P_IX_DP;
618 }
619 p->ci &= ~(1 << slot);
620 ahci_generate_intr(p->pr_sc);
621}
622
623static void
624handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
625{
626 if (!p->atapi) {
627 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
628 p->is |= AHCI_P_IX_TFE;
629 } else {
630 uint16_t buf[256];
631
632 memset(buf, 0, sizeof(buf));
633 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
634 /* TODO emulate different serial? */
635 ata_string((uint8_t *)(buf+10), "123456", 20);
636 ata_string((uint8_t *)(buf+23), "001", 8);
637 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
638 buf[49] = (1 << 9 | 1 << 8);
639 buf[50] = (1 << 14 | 1);
640 buf[53] = (1 << 2 | 1 << 1);
641 buf[62] = 0x3f;
642 buf[63] = 7;
643 buf[64] = 3;
644 buf[65] = 100;
645 buf[66] = 100;
646 buf[67] = 100;
647 buf[68] = 100;
648 buf[76] = (1 << 2 | 1 << 1);
649 buf[78] = (1 << 5);
650 buf[80] = (0x1f << 4);
651 buf[82] = (1 << 4);
652 buf[83] = (1 << 14);
653 buf[84] = (1 << 14);
654 buf[85] = (1 << 4);
655 buf[87] = (1 << 14);
656 buf[88] = (1 << 14 | 0x7f);
657 ahci_write_fis_piosetup(p);
658 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
659 p->tfd = ATA_S_DSC | ATA_S_READY;
660 p->is |= AHCI_P_IX_DHR;
661 }
662 p->ci &= ~(1 << slot);
663 ahci_generate_intr(p->pr_sc);
664}
665
666static void
667atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
668{
669 uint8_t buf[36];
670 uint8_t *acmd;
671 int len;
672
673 acmd = cfis + 0x40;
674
675 buf[0] = 0x05;
676 buf[1] = 0x80;
677 buf[2] = 0x00;
678 buf[3] = 0x21;
679 buf[4] = 31;
680 buf[5] = 0;
681 buf[6] = 0;
682 buf[7] = 0;
683 atapi_string(buf + 8, "BHYVE", 8);
684 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
685 atapi_string(buf + 32, "001", 4);
686
687 len = sizeof(buf);
688 if (len > acmd[4])
689 len = acmd[4];
690 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
691 write_prdt(p, slot, cfis, buf, len);
692 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
693}
694
695static void
696atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
697{
698 uint8_t buf[8];
699 uint64_t sectors;
700
701 sectors = blockif_size(p->bctx) / 2048;
702 be32enc(buf, sectors - 1);
703 be32enc(buf + 4, 2048);
704 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
705 write_prdt(p, slot, cfis, buf, sizeof(buf));
706 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
707}
708
709static void
710atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
711{
712 uint8_t *acmd;
713 uint8_t format;
714 int len;
715
716 acmd = cfis + 0x40;
717
718 len = be16dec(acmd + 7);
719 format = acmd[9] >> 6;
720 switch (format) {
721 case 0:
722 {
723 int msf, size;
724 uint64_t sectors;
725 uint8_t start_track, buf[20], *bp;
726
727 msf = (acmd[1] >> 1) & 1;
728 start_track = acmd[6];
729 if (start_track > 1 && start_track != 0xaa) {
730 uint32_t tfd;
731 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
732 p->asc = 0x24;
733 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
734 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
735 ahci_write_fis_d2h(p, slot, cfis, tfd);
736 return;
737 }
738 bp = buf + 2;
739 *bp++ = 1;
740 *bp++ = 1;
741 if (start_track <= 1) {
742 *bp++ = 0;
743 *bp++ = 0x14;
744 *bp++ = 1;
745 *bp++ = 0;
746 if (msf) {
747 *bp++ = 0;
748 lba_to_msf(bp, 0);
749 bp += 3;
750 } else {
751 *bp++ = 0;
752 *bp++ = 0;
753 *bp++ = 0;
754 *bp++ = 0;
755 }
756 }
757 *bp++ = 0;
758 *bp++ = 0x14;
759 *bp++ = 0xaa;
760 *bp++ = 0;
761 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
762 sectors >>= 2;
763 if (msf) {
764 *bp++ = 0;
765 lba_to_msf(bp, sectors);
766 bp += 3;
767 } else {
768 be32enc(bp, sectors);
769 bp += 4;
770 }
771 size = bp - buf;
772 be16enc(buf, size - 2);
773 if (len > size)
774 len = size;
775 write_prdt(p, slot, cfis, buf, len);
776 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
777 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
778 break;
779 }
780 case 1:
781 {
782 uint8_t buf[12];
783
784 memset(buf, 0, sizeof(buf));
785 buf[1] = 0xa;
786 buf[2] = 0x1;
787 buf[3] = 0x1;
788 if (len > sizeof(buf))
789 len = sizeof(buf);
790 write_prdt(p, slot, cfis, buf, len);
791 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
792 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
793 break;
794 }
795 case 2:
796 {
797 int msf, size;
798 uint64_t sectors;
799 uint8_t start_track, *bp, buf[50];
800
801 msf = (acmd[1] >> 1) & 1;
802 start_track = acmd[6];
803 bp = buf + 2;
804 *bp++ = 1;
805 *bp++ = 1;
806
807 *bp++ = 1;
808 *bp++ = 0x14;
809 *bp++ = 0;
810 *bp++ = 0xa0;
811 *bp++ = 0;
812 *bp++ = 0;
813 *bp++ = 0;
814 *bp++ = 0;
815 *bp++ = 1;
816 *bp++ = 0;
817 *bp++ = 0;
818
819 *bp++ = 1;
820 *bp++ = 0x14;
821 *bp++ = 0;
822 *bp++ = 0xa1;
823 *bp++ = 0;
824 *bp++ = 0;
825 *bp++ = 0;
826 *bp++ = 0;
827 *bp++ = 1;
828 *bp++ = 0;
829 *bp++ = 0;
830
831 *bp++ = 1;
832 *bp++ = 0x14;
833 *bp++ = 0;
834 *bp++ = 0xa2;
835 *bp++ = 0;
836 *bp++ = 0;
837 *bp++ = 0;
838 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
839 sectors >>= 2;
840 if (msf) {
841 *bp++ = 0;
842 lba_to_msf(bp, sectors);
843 bp += 3;
844 } else {
845 be32enc(bp, sectors);
846 bp += 4;
847 }
848
849 *bp++ = 1;
850 *bp++ = 0x14;
851 *bp++ = 0;
852 *bp++ = 1;
853 *bp++ = 0;
854 *bp++ = 0;
855 *bp++ = 0;
856 if (msf) {
857 *bp++ = 0;
858 lba_to_msf(bp, 0);
859 bp += 3;
860 } else {
861 *bp++ = 0;
862 *bp++ = 0;
863 *bp++ = 0;
864 *bp++ = 0;
865 }
866
867 size = bp - buf;
868 be16enc(buf, size - 2);
869 if (len > size)
870 len = size;
871 write_prdt(p, slot, cfis, buf, len);
872 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
873 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
874 break;
875 }
876 default:
877 {
878 uint32_t tfd;
879
880 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
881 p->asc = 0x24;
882 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
883 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
884 ahci_write_fis_d2h(p, slot, cfis, tfd);
885 break;
886 }
887 }
888}
889
890static void
891atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
892 uint32_t done, int seek)
893{
894 struct ahci_ioreq *aior;
895 struct ahci_cmd_hdr *hdr;
896 struct ahci_prdt_entry *prdt;
897 struct blockif_req *breq;
898 struct pci_ahci_softc *sc;
899 uint8_t *acmd;
900 uint64_t lba;
901 uint32_t len;
902 int i, err, iovcnt;
903
904 sc = p->pr_sc;
905 acmd = cfis + 0x40;
906 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
907 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
908
909 prdt += seek;
910 lba = be32dec(acmd + 2);
911 if (acmd[0] == READ_10)
912 len = be16dec(acmd + 7);
913 else
914 len = be32dec(acmd + 6);
915 if (len == 0) {
916 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
917 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
918 }
919 lba *= 2048;
920 len *= 2048;
921
922 /*
923 * Pull request off free list
924 */
925 aior = STAILQ_FIRST(&p->iofhd);
926 assert(aior != NULL);
927 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
928 aior->cfis = cfis;
929 aior->slot = slot;
930 aior->len = len;
931 aior->done = done;
932 breq = &aior->io_req;
933 breq->br_offset = lba + done;
934 iovcnt = hdr->prdtl - seek;
935 if (iovcnt > BLOCKIF_IOV_MAX) {
936 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
937 iovcnt = BLOCKIF_IOV_MAX;
938 } else
939 aior->prdtl = 0;
940 breq->br_iovcnt = iovcnt;
941
942 /*
943 * Build up the iovec based on the prdt
944 */
945 for (i = 0; i < iovcnt; i++) {
946 uint32_t dbcsz;
947
948 dbcsz = (prdt->dbc & DBCMASK) + 1;
949 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
950 prdt->dba, dbcsz);
951 breq->br_iov[i].iov_len = dbcsz;
952 aior->done += dbcsz;
953 prdt++;
954 }
955 err = blockif_read(p->bctx, breq);
956 assert(err == 0);
957}
958
959static void
960atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
961{
962 uint8_t buf[64];
963 uint8_t *acmd;
964 int len;
965
966 acmd = cfis + 0x40;
967 len = acmd[4];
968 if (len > sizeof(buf))
969 len = sizeof(buf);
970 memset(buf, 0, len);
971 buf[0] = 0x70 | (1 << 7);
972 buf[2] = p->sense_key;
973 buf[7] = 10;
974 buf[12] = p->asc;
975 write_prdt(p, slot, cfis, buf, len);
976 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
977 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
978}
979
980static void
981atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
982{
983 uint8_t *acmd = cfis + 0x40;
984 uint32_t tfd;
985
986 switch (acmd[4] & 3) {
987 case 0:
988 case 1:
989 case 3:
990 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
991 tfd = ATA_S_READY | ATA_S_DSC;
992 break;
993 case 2:
994 /* TODO eject media */
995 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
996 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
997 p->asc = 0x53;
998 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
999 break;
1000 }
1001 ahci_write_fis_d2h(p, slot, cfis, tfd);
1002}
1003
1004static void
1005atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1006{
1007 uint8_t *acmd;
1008 uint32_t tfd;
1009 uint8_t pc, code;
1010 int len;
1011
1012 acmd = cfis + 0x40;
1013 len = be16dec(acmd + 7);
1014 pc = acmd[2] >> 6;
1015 code = acmd[2] & 0x3f;
1016
1017 switch (pc) {
1018 case 0:
1019 switch (code) {
1020 case MODEPAGE_RW_ERROR_RECOVERY:
1021 {
1022 uint8_t buf[16];
1023
1024 if (len > sizeof(buf))
1025 len = sizeof(buf);
1026
1027 memset(buf, 0, sizeof(buf));
1028 be16enc(buf, 16 - 2);
1029 buf[2] = 0x70;
1030 buf[8] = 0x01;
1031 buf[9] = 16 - 10;
1032 buf[11] = 0x05;
1033 write_prdt(p, slot, cfis, buf, len);
1034 tfd = ATA_S_READY | ATA_S_DSC;
1035 break;
1036 }
1037 case MODEPAGE_CD_CAPABILITIES:
1038 {
1039 uint8_t buf[30];
1040
1041 if (len > sizeof(buf))
1042 len = sizeof(buf);
1043
1044 memset(buf, 0, sizeof(buf));
1045 be16enc(buf, 30 - 2);
1046 buf[2] = 0x70;
1047 buf[8] = 0x2A;
1048 buf[9] = 30 - 10;
1049 buf[10] = 0x08;
1050 buf[12] = 0x71;
1051 be16enc(&buf[18], 2);
1052 be16enc(&buf[20], 512);
1053 write_prdt(p, slot, cfis, buf, len);
1054 tfd = ATA_S_READY | ATA_S_DSC;
1055 break;
1056 }
1057 default:
1058 goto error;
1059 break;
1060 }
1061 break;
1062 case 3:
1063 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1064 p->asc = 0x39;
1065 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1066 break;
1067error:
1068 case 1:
1069 case 2:
1070 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1071 p->asc = 0x24;
1072 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1073 break;
1074 }
1075 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1076 ahci_write_fis_d2h(p, slot, cfis, tfd);
1077}
1078
1079static void
1080atapi_get_event_status_notification(struct ahci_port *p, int slot,
1081 uint8_t *cfis)
1082{
1083 uint8_t *acmd;
1084 uint32_t tfd;
1085
1086 acmd = cfis + 0x40;
1087
1088 /* we don't support asynchronous operation */
1089 if (!(acmd[1] & 1)) {
1090 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1091 p->asc = 0x24;
1092 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1093 } else {
1094 uint8_t buf[8];
1095 int len;
1096
1097 len = be16dec(acmd + 7);
1098 if (len > sizeof(buf))
1099 len = sizeof(buf);
1100
1101 memset(buf, 0, sizeof(buf));
1102 be16enc(buf, 8 - 2);
1103 buf[2] = 0x04;
1104 buf[3] = 0x10;
1105 buf[5] = 0x02;
1106 write_prdt(p, slot, cfis, buf, len);
1107 tfd = ATA_S_READY | ATA_S_DSC;
1108 }
1109 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1110 ahci_write_fis_d2h(p, slot, cfis, tfd);
1111}
1112
1113static void
1114handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1115{
1116 uint8_t *acmd;
1117
1118 acmd = cfis + 0x40;
1119
1120#ifdef AHCI_DEBUG
1121 {
1122 int i;
1123 DPRINTF("ACMD:");
1124 for (i = 0; i < 16; i++)
1125 DPRINTF("%02x ", acmd[i]);
1126 DPRINTF("\n");
1127 }
1128#endif
1129
1130 switch (acmd[0]) {
1131 case TEST_UNIT_READY:
1132 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1133 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1134 break;
1135 case INQUIRY:
1136 atapi_inquiry(p, slot, cfis);
1137 break;
1138 case READ_CAPACITY:
1139 atapi_read_capacity(p, slot, cfis);
1140 break;
1141 case PREVENT_ALLOW:
1142 /* TODO */
1143 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1144 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1145 break;
1146 case READ_TOC:
1147 atapi_read_toc(p, slot, cfis);
1148 break;
1149 case READ_10:
1150 case READ_12:
1151 atapi_read(p, slot, cfis, 0, 0);
1152 break;
1153 case REQUEST_SENSE:
1154 atapi_request_sense(p, slot, cfis);
1155 break;
1156 case START_STOP_UNIT:
1157 atapi_start_stop_unit(p, slot, cfis);
1158 break;
1159 case MODE_SENSE_10:
1160 atapi_mode_sense(p, slot, cfis);
1161 break;
1162 case GET_EVENT_STATUS_NOTIFICATION:
1163 atapi_get_event_status_notification(p, slot, cfis);
1164 break;
1165 default:
1166 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1167 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1168 p->asc = 0x20;
1169 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1170 ATA_S_READY | ATA_S_ERROR);
1171 break;
1172 }
1173}
1174
1175static void
1176ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1177{
1178
1179 switch (cfis[2]) {
1180 case ATA_ATA_IDENTIFY:
1181 handle_identify(p, slot, cfis);
1182 break;
1183 case ATA_SETFEATURES:
1184 {
1185 switch (cfis[3]) {
1186 case ATA_SF_ENAB_SATA_SF:
1187 switch (cfis[12]) {
1188 case ATA_SATA_SF_AN:
1189 p->tfd = ATA_S_DSC | ATA_S_READY;
1190 break;
1191 default:
1192 p->tfd = ATA_S_ERROR | ATA_S_READY;
1193 p->tfd |= (ATA_ERROR_ABORT << 8);
1194 break;
1195 }
1196 break;
1197 case ATA_SF_ENAB_WCACHE:
1198 case ATA_SF_DIS_WCACHE:
1199 case ATA_SF_ENAB_RCACHE:
1200 case ATA_SF_DIS_RCACHE:
1201 p->tfd = ATA_S_DSC | ATA_S_READY;
1202 break;
1203 case ATA_SF_SETXFER:
1204 {
1205 switch (cfis[12] & 0xf8) {
1206 case ATA_PIO:
1207 case ATA_PIO0:
1208 break;
1209 case ATA_WDMA0:
1210 case ATA_UDMA0:
1211 p->xfermode = (cfis[12] & 0x7);
1212 break;
1213 }
1214 p->tfd = ATA_S_DSC | ATA_S_READY;
1215 break;
1216 }
1217 default:
1218 p->tfd = ATA_S_ERROR | ATA_S_READY;
1219 p->tfd |= (ATA_ERROR_ABORT << 8);
1220 break;
1221 }
1222 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1223 break;
1224 }
1225 case ATA_SET_MULTI:
1226 if (cfis[12] != 0 &&
1227 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1228 p->tfd = ATA_S_ERROR | ATA_S_READY;
1229 p->tfd |= (ATA_ERROR_ABORT << 8);
1230 } else {
1231 p->mult_sectors = cfis[12];
1232 p->tfd = ATA_S_DSC | ATA_S_READY;
1233 }
1234 p->is |= AHCI_P_IX_DP;
1235 p->ci &= ~(1 << slot);
1236 ahci_generate_intr(p->pr_sc);
1237 break;
1238 case ATA_READ_DMA:
1239 case ATA_WRITE_DMA:
1240 case ATA_READ_DMA48:
1241 case ATA_WRITE_DMA48:
1242 case ATA_READ_FPDMA_QUEUED:
1243 case ATA_WRITE_FPDMA_QUEUED:
1244 ahci_handle_dma(p, slot, cfis, 0, 0);
1245 break;
1246 case ATA_FLUSHCACHE:
1247 case ATA_FLUSHCACHE48:
1248 ahci_handle_flush(p, slot, cfis);
1249 break;
1250 case ATA_STANDBY_CMD:
1251 break;
1252 case ATA_NOP:
1253 case ATA_STANDBY_IMMEDIATE:
1254 case ATA_IDLE_IMMEDIATE:
1255 case ATA_SLEEP:
1256 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1257 break;
1258 case ATA_ATAPI_IDENTIFY:
1259 handle_atapi_identify(p, slot, cfis);
1260 break;
1261 case ATA_PACKET_CMD:
1262 if (!p->atapi) {
1263 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1264 p->is |= AHCI_P_IX_TFE;
1265 p->ci &= ~(1 << slot);
1266 ahci_generate_intr(p->pr_sc);
1267 } else
1268 handle_packet_cmd(p, slot, cfis);
1269 break;
1270 default:
1271 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1272 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1273 p->is |= AHCI_P_IX_TFE;
1274 p->ci &= ~(1 << slot);
1275 ahci_generate_intr(p->pr_sc);
1276 break;
1277 }
1278}
1279
1280static void
1281ahci_handle_slot(struct ahci_port *p, int slot)
1282{
1283 struct ahci_cmd_hdr *hdr;
1284 struct ahci_prdt_entry *prdt;
1285 struct pci_ahci_softc *sc;
1286 uint8_t *cfis;
1287 int cfl;
1288
1289 sc = p->pr_sc;
1290 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1291 cfl = (hdr->flags & 0x1f) * 4;
1292 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1293 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1294 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1295
1296#ifdef AHCI_DEBUG
1297 DPRINTF("\ncfis:");
1298 for (i = 0; i < cfl; i++) {
1299 if (i % 10 == 0)
1300 DPRINTF("\n");
1301 DPRINTF("%02x ", cfis[i]);
1302 }
1303 DPRINTF("\n");
1304
1305 for (i = 0; i < hdr->prdtl; i++) {
1306 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1307 prdt++;
1308 }
1309#endif
1310
1311 if (cfis[0] != FIS_TYPE_REGH2D) {
1312 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1313 return;
1314 }
1315
1316 if (cfis[1] & 0x80) {
1317 ahci_handle_cmd(p, slot, cfis);
1318 } else {
1319 if (cfis[15] & (1 << 2))
1320 p->reset = 1;
1321 else if (p->reset) {
1322 p->reset = 0;
1323 ahci_port_reset(p);
1324 }
1325 p->ci &= ~(1 << slot);
1326 }
1327}
1328
1329static void
1330ahci_handle_port(struct ahci_port *p)
1331{
1332 int i;
1333
1334 if (!(p->cmd & AHCI_P_CMD_ST))
1335 return;
1336
1337 /*
1338 * Search for any new commands to issue ignoring those that
1339 * are already in-flight.
1340 */
1341 for (i = 0; (i < 32) && p->ci; i++) {
1342 if ((p->ci & (1 << i)) && !(p->pending & (1 << i)))
1343 ahci_handle_slot(p, i);
1344 }
1345}
1346
1347/*
1348 * blockif callback routine - this runs in the context of the blockif
1349 * i/o thread, so the mutex needs to be acquired.
1350 */
1351static void
1352ata_ioreq_cb(struct blockif_req *br, int err)
1353{
1354 struct ahci_cmd_hdr *hdr;
1355 struct ahci_ioreq *aior;
1356 struct ahci_port *p;
1357 struct pci_ahci_softc *sc;
1358 uint32_t tfd;
1359 uint8_t *cfis;
1360 int pending, slot, ncq;
1361
1362 DPRINTF("%s %d\n", __func__, err);
1363
1364 ncq = 0;
1365 aior = br->br_param;
1366 p = aior->io_pr;
1367 cfis = aior->cfis;
1368 slot = aior->slot;
1369 pending = aior->prdtl;
1370 sc = p->pr_sc;
1371 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1372
1373 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1374 cfis[2] == ATA_READ_FPDMA_QUEUED)
1375 ncq = 1;
1376
1377 pthread_mutex_lock(&sc->mtx);
1378
1379 /*
1380 * Move the blockif request back to the free list
1381 */
1382 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1383
1384 if (pending && !err) {
1385 ahci_handle_dma(p, slot, cfis, aior->done,
1386 hdr->prdtl - pending);
1387 goto out;
1388 }
1389
1390 if (!err && aior->done == aior->len) {
1391 tfd = ATA_S_READY | ATA_S_DSC;
1392 if (ncq)
1393 hdr->prdbc = 0;
1394 else
1395 hdr->prdbc = aior->len;
1396 } else {
1397 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1398 hdr->prdbc = 0;
1399 if (ncq)
1400 p->serr |= (1 << slot);
1401 }
1402
1403 /*
1404 * This command is now complete.
1405 */
1406 p->pending &= ~(1 << slot);
1407
1408 if (ncq) {
1409 p->sact &= ~(1 << slot);
1410 ahci_write_fis_sdb(p, slot, tfd);
1411 } else
1412 ahci_write_fis_d2h(p, slot, cfis, tfd);
1413
1414out:
1415 pthread_mutex_unlock(&sc->mtx);
1416 DPRINTF("%s exit\n", __func__);
1417}
1418
1419static void
1420atapi_ioreq_cb(struct blockif_req *br, int err)
1421{
1422 struct ahci_cmd_hdr *hdr;
1423 struct ahci_ioreq *aior;
1424 struct ahci_port *p;
1425 struct pci_ahci_softc *sc;
1426 uint8_t *cfis;
1427 uint32_t tfd;
1428 int pending, slot;
1429
1430 DPRINTF("%s %d\n", __func__, err);
1431
1432 aior = br->br_param;
1433 p = aior->io_pr;
1434 cfis = aior->cfis;
1435 slot = aior->slot;
1436 pending = aior->prdtl;
1437 sc = p->pr_sc;
1438 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1439
1440 pthread_mutex_lock(&sc->mtx);
1441
1442 /*
1443 * Move the blockif request back to the free list
1444 */
1445 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1446
1447 if (pending && !err) {
1448 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1449 goto out;
1450 }
1451
1452 if (!err && aior->done == aior->len) {
1453 tfd = ATA_S_READY | ATA_S_DSC;
1454 hdr->prdbc = aior->len;
1455 } else {
1456 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1457 p->asc = 0x21;
1458 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1459 hdr->prdbc = 0;
1460 }
1461
1462 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1463 ahci_write_fis_d2h(p, slot, cfis, tfd);
1464
1465out:
1466 pthread_mutex_unlock(&sc->mtx);
1467 DPRINTF("%s exit\n", __func__);
1468}
1469
1470static void
1471pci_ahci_ioreq_init(struct ahci_port *pr)
1472{
1473 struct ahci_ioreq *vr;
1474 int i;
1475
1476 pr->ioqsz = blockif_queuesz(pr->bctx);
1477 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1478 STAILQ_INIT(&pr->iofhd);
1479
1480 /*
1481 * Add all i/o request entries to the free queue
1482 */
1483 for (i = 0; i < pr->ioqsz; i++) {
1484 vr = &pr->ioreq[i];
1485 vr->io_pr = pr;
1486 if (!pr->atapi)
1487 vr->io_req.br_callback = ata_ioreq_cb;
1488 else
1489 vr->io_req.br_callback = atapi_ioreq_cb;
1490 vr->io_req.br_param = vr;
1491 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_list);
1492 }
1493}
1494
1495static void
1496pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1497{
1498 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1499 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1500 struct ahci_port *p = &sc->port[port];
1501
1502 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1503 port, offset, value);
1504
1505 switch (offset) {
1506 case AHCI_P_CLB:
1507 p->clb = value;
1508 break;
1509 case AHCI_P_CLBU:
1510 p->clbu = value;
1511 break;
1512 case AHCI_P_FB:
1513 p->fb = value;
1514 break;
1515 case AHCI_P_FBU:
1516 p->fbu = value;
1517 break;
1518 case AHCI_P_IS:
1519 p->is &= ~value;
1520 break;
1521 case AHCI_P_IE:
1522 p->ie = value & 0xFDC000FF;
1523 ahci_generate_intr(sc);
1524 break;
1525 case AHCI_P_CMD:
1526 {
1527 p->cmd = value;
1528
1529 if (!(value & AHCI_P_CMD_ST)) {
1530 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
1531 p->ci = 0;
1532 p->sact = 0;
1533 } else {
1534 uint64_t clb;
1535
1536 p->cmd |= AHCI_P_CMD_CR;
1537 clb = (uint64_t)p->clbu << 32 | p->clb;
1538 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1539 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1540 }
1541
1542 if (value & AHCI_P_CMD_FRE) {
1543 uint64_t fb;
1544
1545 p->cmd |= AHCI_P_CMD_FR;
1546 fb = (uint64_t)p->fbu << 32 | p->fb;
1547 /* we don't support FBSCP, so rfis size is 256Bytes */
1548 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1549 } else {
1550 p->cmd &= ~AHCI_P_CMD_FR;
1551 }
1552
1553 if (value & AHCI_P_CMD_CLO) {
1554 p->tfd = 0;
1555 p->cmd &= ~AHCI_P_CMD_CLO;
1556 }
1557
1558 ahci_handle_port(p);
1559 break;
1560 }
1561 case AHCI_P_TFD:
1562 case AHCI_P_SIG:
1563 case AHCI_P_SSTS:
1564 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1565 break;
1566 case AHCI_P_SCTL:
1567 if (!(p->cmd & AHCI_P_CMD_ST)) {
1568 if (value & ATA_SC_DET_RESET)
1569 ahci_port_reset(p);
1570 p->sctl = value;
1571 }
1572 break;
1573 case AHCI_P_SERR:
1574 p->serr &= ~value;
1575 break;
1576 case AHCI_P_SACT:
1577 p->sact |= value;
1578 break;
1579 case AHCI_P_CI:
1580 p->ci |= value;
1581 ahci_handle_port(p);
1582 break;
1583 case AHCI_P_SNTF:
1584 case AHCI_P_FBS:
1585 default:
1586 break;
1587 }
1588}
1589
1590static void
1591pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1592{
1593 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1594 offset, value);
1595
1596 switch (offset) {
1597 case AHCI_CAP:
1598 case AHCI_PI:
1599 case AHCI_VS:
1600 case AHCI_CAP2:
1601 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1602 break;
1603 case AHCI_GHC:
1604 if (value & AHCI_GHC_HR)
1605 ahci_reset(sc);
1606 else if (value & AHCI_GHC_IE) {
1607 sc->ghc |= AHCI_GHC_IE;
1608 ahci_generate_intr(sc);
1609 }
1610 break;
1611 case AHCI_IS:
1612 sc->is &= ~value;
1613 ahci_generate_intr(sc);
1614 break;
1615 default:
1616 break;
1617 }
1618}
1619
1620static void
1621pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1622 int baridx, uint64_t offset, int size, uint64_t value)
1623{
1624 struct pci_ahci_softc *sc = pi->pi_arg;
1625
1626 assert(baridx == 5);
1627 assert(size == 4);
1628
1629 pthread_mutex_lock(&sc->mtx);
1630
1631 if (offset < AHCI_OFFSET)
1632 pci_ahci_host_write(sc, offset, value);
1633 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1634 pci_ahci_port_write(sc, offset, value);
1635 else
1636 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1637
1638 pthread_mutex_unlock(&sc->mtx);
1639}
1640
1641static uint64_t
1642pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
1643{
1644 uint32_t value;
1645
1646 switch (offset) {
1647 case AHCI_CAP:
1648 case AHCI_GHC:
1649 case AHCI_IS:
1650 case AHCI_PI:
1651 case AHCI_VS:
1652 case AHCI_CCCC:
1653 case AHCI_CCCP:
1654 case AHCI_EM_LOC:
1655 case AHCI_EM_CTL:
1656 case AHCI_CAP2:
1657 {
1658 uint32_t *p = &sc->cap;
1659 p += (offset - AHCI_CAP) / sizeof(uint32_t);
1660 value = *p;
1661 break;
1662 }
1663 default:
1664 value = 0;
1665 break;
1666 }
1667 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
1668 offset, value);
1669
1670 return (value);
1671}
1672
1673static uint64_t
1674pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
1675{
1676 uint32_t value;
1677 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1678 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1679
1680 switch (offset) {
1681 case AHCI_P_CLB:
1682 case AHCI_P_CLBU:
1683 case AHCI_P_FB:
1684 case AHCI_P_FBU:
1685 case AHCI_P_IS:
1686 case AHCI_P_IE:
1687 case AHCI_P_CMD:
1688 case AHCI_P_TFD:
1689 case AHCI_P_SIG:
1690 case AHCI_P_SSTS:
1691 case AHCI_P_SCTL:
1692 case AHCI_P_SERR:
1693 case AHCI_P_SACT:
1694 case AHCI_P_CI:
1695 case AHCI_P_SNTF:
1696 case AHCI_P_FBS:
1697 {
1698 uint32_t *p= &sc->port[port].clb;
1699 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
1700 value = *p;
1701 break;
1702 }
1703 default:
1704 value = 0;
1705 break;
1706 }
1707
1708 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
1709 port, offset, value);
1710
1711 return value;
1712}
1713
1714static uint64_t
1715pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1716 uint64_t offset, int size)
1717{
1718 struct pci_ahci_softc *sc = pi->pi_arg;
1719 uint32_t value;
1720
1721 assert(baridx == 5);
1722 assert(size == 4);
1723
1724 pthread_mutex_lock(&sc->mtx);
1725
1726 if (offset < AHCI_OFFSET)
1727 value = pci_ahci_host_read(sc, offset);
1728 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1729 value = pci_ahci_port_read(sc, offset);
1730 else {
1731 value = 0;
1732 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
1733 }
1734
1735 pthread_mutex_unlock(&sc->mtx);
1736
1737 return (value);
1738}
1739
1740static int
1741pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
1742{
1743 char bident[sizeof("XX:X:X")];
1744 struct blockif_ctxt *bctxt;
1745 struct pci_ahci_softc *sc;
1746 int ret, slots;
1747
1748 ret = 0;
1749
1750 if (opts == NULL) {
1751 fprintf(stderr, "pci_ahci: backing device required\n");
1752 return (1);
1753 }
1754
1755#ifdef AHCI_DEBUG
1756 dbg = fopen("/tmp/log", "w+");
1757#endif
1758
1759 sc = malloc(sizeof(struct pci_ahci_softc));
1760 memset(sc, 0, sizeof(struct pci_ahci_softc));
1761 pi->pi_arg = sc;
1762 sc->asc_pi = pi;
1763 sc->ports = MAX_PORTS;
1764
1765 /*
1766 * Only use port 0 for a backing device. All other ports will be
1767 * marked as unused
1768 */
1769 sc->port[0].atapi = atapi;
1770
1771 /*
1772 * Attempt to open the backing image. Use the PCI
1773 * slot/func for the identifier string.
1774 */
1775 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func);
1776 bctxt = blockif_open(opts, bident);
1777 if (bctxt == NULL) {
1778 ret = 1;
1779 goto open_fail;
1780 }
1781 sc->port[0].bctx = bctxt;
1782 sc->port[0].pr_sc = sc;
1783
1784 /*
1785 * Allocate blockif request structures and add them
1786 * to the free list
1787 */
1788 pci_ahci_ioreq_init(&sc->port[0]);
1789
1790 pthread_mutex_init(&sc->mtx, NULL);
1791
1792 /* Intel ICH8 AHCI */
1793 slots = sc->port[0].ioqsz;
1794 if (slots > 32)
1795 slots = 32;
1796 --slots;
1797 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
1798 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
1799 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
1800 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
1801 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
1802
1803 /* Only port 0 implemented */
1804 sc->pi = 1;
1805 sc->vs = 0x10300;
1806 sc->cap2 = AHCI_CAP2_APST;
1807 ahci_reset(sc);
1808
1809 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
1810 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
1811 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
1812 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
1813 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
1814 pci_emul_add_msicap(pi, 1);
1815 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
1816 AHCI_OFFSET + sc->ports * AHCI_STEP);
1817
| 400 for (i = 0; i < sc->ports; i++) {
401 sc->port[i].ie = 0;
402 sc->port[i].is = 0;
403 ahci_port_reset(&sc->port[i]);
404 }
405}
406
407static void
408ata_string(uint8_t *dest, const char *src, int len)
409{
410 int i;
411
412 for (i = 0; i < len; i++) {
413 if (*src)
414 dest[i ^ 1] = *src++;
415 else
416 dest[i ^ 1] = ' ';
417 }
418}
419
420static void
421atapi_string(uint8_t *dest, const char *src, int len)
422{
423 int i;
424
425 for (i = 0; i < len; i++) {
426 if (*src)
427 dest[i] = *src++;
428 else
429 dest[i] = ' ';
430 }
431}
432
433static void
434ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
435 int seek)
436{
437 struct ahci_ioreq *aior;
438 struct blockif_req *breq;
439 struct pci_ahci_softc *sc;
440 struct ahci_prdt_entry *prdt;
441 struct ahci_cmd_hdr *hdr;
442 uint64_t lba;
443 uint32_t len;
444 int i, err, iovcnt, ncq, readop;
445
446 sc = p->pr_sc;
447 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
448 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
449 ncq = 0;
450 readop = 1;
451
452 prdt += seek;
453 if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
454 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
455 readop = 0;
456
457 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
458 cfis[2] == ATA_READ_FPDMA_QUEUED) {
459 lba = ((uint64_t)cfis[10] << 40) |
460 ((uint64_t)cfis[9] << 32) |
461 ((uint64_t)cfis[8] << 24) |
462 ((uint64_t)cfis[6] << 16) |
463 ((uint64_t)cfis[5] << 8) |
464 cfis[4];
465 len = cfis[11] << 8 | cfis[3];
466 if (!len)
467 len = 65536;
468 ncq = 1;
469 } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
470 lba = ((uint64_t)cfis[10] << 40) |
471 ((uint64_t)cfis[9] << 32) |
472 ((uint64_t)cfis[8] << 24) |
473 ((uint64_t)cfis[6] << 16) |
474 ((uint64_t)cfis[5] << 8) |
475 cfis[4];
476 len = cfis[13] << 8 | cfis[12];
477 if (!len)
478 len = 65536;
479 } else {
480 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
481 (cfis[5] << 8) | cfis[4];
482 len = cfis[12];
483 if (!len)
484 len = 256;
485 }
486 lba *= blockif_sectsz(p->bctx);
487 len *= blockif_sectsz(p->bctx);
488
489 /*
490 * Pull request off free list
491 */
492 aior = STAILQ_FIRST(&p->iofhd);
493 assert(aior != NULL);
494 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
495 aior->cfis = cfis;
496 aior->slot = slot;
497 aior->len = len;
498 aior->done = done;
499 breq = &aior->io_req;
500 breq->br_offset = lba + done;
501 iovcnt = hdr->prdtl - seek;
502 if (iovcnt > BLOCKIF_IOV_MAX) {
503 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
504 iovcnt = BLOCKIF_IOV_MAX;
505 /*
506 * Mark this command in-flight.
507 */
508 p->pending |= 1 << slot;
509 } else
510 aior->prdtl = 0;
511 breq->br_iovcnt = iovcnt;
512
513 /*
514 * Build up the iovec based on the prdt
515 */
516 for (i = 0; i < iovcnt; i++) {
517 uint32_t dbcsz;
518
519 dbcsz = (prdt->dbc & DBCMASK) + 1;
520 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
521 prdt->dba, dbcsz);
522 breq->br_iov[i].iov_len = dbcsz;
523 aior->done += dbcsz;
524 prdt++;
525 }
526 if (readop)
527 err = blockif_read(p->bctx, breq);
528 else
529 err = blockif_write(p->bctx, breq);
530 assert(err == 0);
531
532 if (ncq)
533 p->ci &= ~(1 << slot);
534}
535
536static void
537ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
538{
539 struct ahci_ioreq *aior;
540 struct blockif_req *breq;
541 int err;
542
543 /*
544 * Pull request off free list
545 */
546 aior = STAILQ_FIRST(&p->iofhd);
547 assert(aior != NULL);
548 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
549 aior->cfis = cfis;
550 aior->slot = slot;
551 aior->len = 0;
552 aior->done = 0;
553 aior->prdtl = 0;
554 breq = &aior->io_req;
555
556 err = blockif_flush(p->bctx, breq);
557 assert(err == 0);
558}
559
560static inline void
561write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
562 void *buf, int size)
563{
564 struct ahci_cmd_hdr *hdr;
565 struct ahci_prdt_entry *prdt;
566 void *from;
567 int i, len;
568
569 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
570 len = size;
571 from = buf;
572 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
573 for (i = 0; i < hdr->prdtl && len; i++) {
574 uint8_t *ptr;
575 uint32_t dbcsz;
576 int sublen;
577
578 dbcsz = (prdt->dbc & DBCMASK) + 1;
579 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
580 sublen = len < dbcsz ? len : dbcsz;
581 memcpy(ptr, from, sublen);
582 len -= sublen;
583 from += sublen;
584 prdt++;
585 }
586 hdr->prdbc = size - len;
587}
588
589static void
590handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
591{
592 struct ahci_cmd_hdr *hdr;
593
594 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
595 if (p->atapi || hdr->prdtl == 0) {
596 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
597 p->is |= AHCI_P_IX_TFE;
598 } else {
599 uint16_t buf[256];
600 uint64_t sectors;
601
602 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
603 memset(buf, 0, sizeof(buf));
604 buf[0] = 0x0040;
605 /* TODO emulate different serial? */
606 ata_string((uint8_t *)(buf+10), "123456", 20);
607 ata_string((uint8_t *)(buf+23), "001", 8);
608 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
609 buf[47] = (0x8000 | 128);
610 buf[48] = 0x1;
611 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
612 buf[50] = (1 << 14);
613 buf[53] = (1 << 1 | 1 << 2);
614 if (p->mult_sectors)
615 buf[59] = (0x100 | p->mult_sectors);
616 buf[60] = sectors;
617 buf[61] = (sectors >> 16);
618 buf[63] = 0x7;
619 if (p->xfermode & ATA_WDMA0)
620 buf[63] |= (1 << ((p->xfermode & 7) + 8));
621 buf[64] = 0x3;
622 buf[65] = 100;
623 buf[66] = 100;
624 buf[67] = 100;
625 buf[68] = 100;
626 buf[75] = 31;
627 buf[76] = (1 << 8 | 1 << 2);
628 buf[80] = 0x1f0;
629 buf[81] = 0x28;
630 buf[82] = (1 << 5 | 1 << 14);
631 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14);
632 buf[84] = (1 << 14);
633 buf[85] = (1 << 5 | 1 << 14);
634 buf[86] = (1 << 10 | 1 << 12 | 1 << 13);
635 buf[87] = (1 << 14);
636 buf[88] = 0x7f;
637 if (p->xfermode & ATA_UDMA0)
638 buf[88] |= (1 << ((p->xfermode & 7) + 8));
639 buf[93] = (1 | 1 <<14);
640 buf[100] = sectors;
641 buf[101] = (sectors >> 16);
642 buf[102] = (sectors >> 32);
643 buf[103] = (sectors >> 48);
644 ahci_write_fis_piosetup(p);
645 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
646 p->tfd = ATA_S_DSC | ATA_S_READY;
647 p->is |= AHCI_P_IX_DP;
648 }
649 p->ci &= ~(1 << slot);
650 ahci_generate_intr(p->pr_sc);
651}
652
653static void
654handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
655{
656 if (!p->atapi) {
657 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
658 p->is |= AHCI_P_IX_TFE;
659 } else {
660 uint16_t buf[256];
661
662 memset(buf, 0, sizeof(buf));
663 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
664 /* TODO emulate different serial? */
665 ata_string((uint8_t *)(buf+10), "123456", 20);
666 ata_string((uint8_t *)(buf+23), "001", 8);
667 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
668 buf[49] = (1 << 9 | 1 << 8);
669 buf[50] = (1 << 14 | 1);
670 buf[53] = (1 << 2 | 1 << 1);
671 buf[62] = 0x3f;
672 buf[63] = 7;
673 buf[64] = 3;
674 buf[65] = 100;
675 buf[66] = 100;
676 buf[67] = 100;
677 buf[68] = 100;
678 buf[76] = (1 << 2 | 1 << 1);
679 buf[78] = (1 << 5);
680 buf[80] = (0x1f << 4);
681 buf[82] = (1 << 4);
682 buf[83] = (1 << 14);
683 buf[84] = (1 << 14);
684 buf[85] = (1 << 4);
685 buf[87] = (1 << 14);
686 buf[88] = (1 << 14 | 0x7f);
687 ahci_write_fis_piosetup(p);
688 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
689 p->tfd = ATA_S_DSC | ATA_S_READY;
690 p->is |= AHCI_P_IX_DHR;
691 }
692 p->ci &= ~(1 << slot);
693 ahci_generate_intr(p->pr_sc);
694}
695
696static void
697atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
698{
699 uint8_t buf[36];
700 uint8_t *acmd;
701 int len;
702
703 acmd = cfis + 0x40;
704
705 buf[0] = 0x05;
706 buf[1] = 0x80;
707 buf[2] = 0x00;
708 buf[3] = 0x21;
709 buf[4] = 31;
710 buf[5] = 0;
711 buf[6] = 0;
712 buf[7] = 0;
713 atapi_string(buf + 8, "BHYVE", 8);
714 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
715 atapi_string(buf + 32, "001", 4);
716
717 len = sizeof(buf);
718 if (len > acmd[4])
719 len = acmd[4];
720 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
721 write_prdt(p, slot, cfis, buf, len);
722 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
723}
724
725static void
726atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
727{
728 uint8_t buf[8];
729 uint64_t sectors;
730
731 sectors = blockif_size(p->bctx) / 2048;
732 be32enc(buf, sectors - 1);
733 be32enc(buf + 4, 2048);
734 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
735 write_prdt(p, slot, cfis, buf, sizeof(buf));
736 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
737}
738
739static void
740atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
741{
742 uint8_t *acmd;
743 uint8_t format;
744 int len;
745
746 acmd = cfis + 0x40;
747
748 len = be16dec(acmd + 7);
749 format = acmd[9] >> 6;
750 switch (format) {
751 case 0:
752 {
753 int msf, size;
754 uint64_t sectors;
755 uint8_t start_track, buf[20], *bp;
756
757 msf = (acmd[1] >> 1) & 1;
758 start_track = acmd[6];
759 if (start_track > 1 && start_track != 0xaa) {
760 uint32_t tfd;
761 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
762 p->asc = 0x24;
763 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
764 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
765 ahci_write_fis_d2h(p, slot, cfis, tfd);
766 return;
767 }
768 bp = buf + 2;
769 *bp++ = 1;
770 *bp++ = 1;
771 if (start_track <= 1) {
772 *bp++ = 0;
773 *bp++ = 0x14;
774 *bp++ = 1;
775 *bp++ = 0;
776 if (msf) {
777 *bp++ = 0;
778 lba_to_msf(bp, 0);
779 bp += 3;
780 } else {
781 *bp++ = 0;
782 *bp++ = 0;
783 *bp++ = 0;
784 *bp++ = 0;
785 }
786 }
787 *bp++ = 0;
788 *bp++ = 0x14;
789 *bp++ = 0xaa;
790 *bp++ = 0;
791 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
792 sectors >>= 2;
793 if (msf) {
794 *bp++ = 0;
795 lba_to_msf(bp, sectors);
796 bp += 3;
797 } else {
798 be32enc(bp, sectors);
799 bp += 4;
800 }
801 size = bp - buf;
802 be16enc(buf, size - 2);
803 if (len > size)
804 len = size;
805 write_prdt(p, slot, cfis, buf, len);
806 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
807 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
808 break;
809 }
810 case 1:
811 {
812 uint8_t buf[12];
813
814 memset(buf, 0, sizeof(buf));
815 buf[1] = 0xa;
816 buf[2] = 0x1;
817 buf[3] = 0x1;
818 if (len > sizeof(buf))
819 len = sizeof(buf);
820 write_prdt(p, slot, cfis, buf, len);
821 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
822 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
823 break;
824 }
825 case 2:
826 {
827 int msf, size;
828 uint64_t sectors;
829 uint8_t start_track, *bp, buf[50];
830
831 msf = (acmd[1] >> 1) & 1;
832 start_track = acmd[6];
833 bp = buf + 2;
834 *bp++ = 1;
835 *bp++ = 1;
836
837 *bp++ = 1;
838 *bp++ = 0x14;
839 *bp++ = 0;
840 *bp++ = 0xa0;
841 *bp++ = 0;
842 *bp++ = 0;
843 *bp++ = 0;
844 *bp++ = 0;
845 *bp++ = 1;
846 *bp++ = 0;
847 *bp++ = 0;
848
849 *bp++ = 1;
850 *bp++ = 0x14;
851 *bp++ = 0;
852 *bp++ = 0xa1;
853 *bp++ = 0;
854 *bp++ = 0;
855 *bp++ = 0;
856 *bp++ = 0;
857 *bp++ = 1;
858 *bp++ = 0;
859 *bp++ = 0;
860
861 *bp++ = 1;
862 *bp++ = 0x14;
863 *bp++ = 0;
864 *bp++ = 0xa2;
865 *bp++ = 0;
866 *bp++ = 0;
867 *bp++ = 0;
868 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
869 sectors >>= 2;
870 if (msf) {
871 *bp++ = 0;
872 lba_to_msf(bp, sectors);
873 bp += 3;
874 } else {
875 be32enc(bp, sectors);
876 bp += 4;
877 }
878
879 *bp++ = 1;
880 *bp++ = 0x14;
881 *bp++ = 0;
882 *bp++ = 1;
883 *bp++ = 0;
884 *bp++ = 0;
885 *bp++ = 0;
886 if (msf) {
887 *bp++ = 0;
888 lba_to_msf(bp, 0);
889 bp += 3;
890 } else {
891 *bp++ = 0;
892 *bp++ = 0;
893 *bp++ = 0;
894 *bp++ = 0;
895 }
896
897 size = bp - buf;
898 be16enc(buf, size - 2);
899 if (len > size)
900 len = size;
901 write_prdt(p, slot, cfis, buf, len);
902 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
903 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
904 break;
905 }
906 default:
907 {
908 uint32_t tfd;
909
910 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
911 p->asc = 0x24;
912 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
913 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
914 ahci_write_fis_d2h(p, slot, cfis, tfd);
915 break;
916 }
917 }
918}
919
920static void
921atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
922 uint32_t done, int seek)
923{
924 struct ahci_ioreq *aior;
925 struct ahci_cmd_hdr *hdr;
926 struct ahci_prdt_entry *prdt;
927 struct blockif_req *breq;
928 struct pci_ahci_softc *sc;
929 uint8_t *acmd;
930 uint64_t lba;
931 uint32_t len;
932 int i, err, iovcnt;
933
934 sc = p->pr_sc;
935 acmd = cfis + 0x40;
936 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
937 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
938
939 prdt += seek;
940 lba = be32dec(acmd + 2);
941 if (acmd[0] == READ_10)
942 len = be16dec(acmd + 7);
943 else
944 len = be32dec(acmd + 6);
945 if (len == 0) {
946 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
947 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
948 }
949 lba *= 2048;
950 len *= 2048;
951
952 /*
953 * Pull request off free list
954 */
955 aior = STAILQ_FIRST(&p->iofhd);
956 assert(aior != NULL);
957 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
958 aior->cfis = cfis;
959 aior->slot = slot;
960 aior->len = len;
961 aior->done = done;
962 breq = &aior->io_req;
963 breq->br_offset = lba + done;
964 iovcnt = hdr->prdtl - seek;
965 if (iovcnt > BLOCKIF_IOV_MAX) {
966 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
967 iovcnt = BLOCKIF_IOV_MAX;
968 } else
969 aior->prdtl = 0;
970 breq->br_iovcnt = iovcnt;
971
972 /*
973 * Build up the iovec based on the prdt
974 */
975 for (i = 0; i < iovcnt; i++) {
976 uint32_t dbcsz;
977
978 dbcsz = (prdt->dbc & DBCMASK) + 1;
979 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
980 prdt->dba, dbcsz);
981 breq->br_iov[i].iov_len = dbcsz;
982 aior->done += dbcsz;
983 prdt++;
984 }
985 err = blockif_read(p->bctx, breq);
986 assert(err == 0);
987}
988
989static void
990atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
991{
992 uint8_t buf[64];
993 uint8_t *acmd;
994 int len;
995
996 acmd = cfis + 0x40;
997 len = acmd[4];
998 if (len > sizeof(buf))
999 len = sizeof(buf);
1000 memset(buf, 0, len);
1001 buf[0] = 0x70 | (1 << 7);
1002 buf[2] = p->sense_key;
1003 buf[7] = 10;
1004 buf[12] = p->asc;
1005 write_prdt(p, slot, cfis, buf, len);
1006 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1007 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1008}
1009
1010static void
1011atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1012{
1013 uint8_t *acmd = cfis + 0x40;
1014 uint32_t tfd;
1015
1016 switch (acmd[4] & 3) {
1017 case 0:
1018 case 1:
1019 case 3:
1020 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1021 tfd = ATA_S_READY | ATA_S_DSC;
1022 break;
1023 case 2:
1024 /* TODO eject media */
1025 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1026 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1027 p->asc = 0x53;
1028 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1029 break;
1030 }
1031 ahci_write_fis_d2h(p, slot, cfis, tfd);
1032}
1033
1034static void
1035atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1036{
1037 uint8_t *acmd;
1038 uint32_t tfd;
1039 uint8_t pc, code;
1040 int len;
1041
1042 acmd = cfis + 0x40;
1043 len = be16dec(acmd + 7);
1044 pc = acmd[2] >> 6;
1045 code = acmd[2] & 0x3f;
1046
1047 switch (pc) {
1048 case 0:
1049 switch (code) {
1050 case MODEPAGE_RW_ERROR_RECOVERY:
1051 {
1052 uint8_t buf[16];
1053
1054 if (len > sizeof(buf))
1055 len = sizeof(buf);
1056
1057 memset(buf, 0, sizeof(buf));
1058 be16enc(buf, 16 - 2);
1059 buf[2] = 0x70;
1060 buf[8] = 0x01;
1061 buf[9] = 16 - 10;
1062 buf[11] = 0x05;
1063 write_prdt(p, slot, cfis, buf, len);
1064 tfd = ATA_S_READY | ATA_S_DSC;
1065 break;
1066 }
1067 case MODEPAGE_CD_CAPABILITIES:
1068 {
1069 uint8_t buf[30];
1070
1071 if (len > sizeof(buf))
1072 len = sizeof(buf);
1073
1074 memset(buf, 0, sizeof(buf));
1075 be16enc(buf, 30 - 2);
1076 buf[2] = 0x70;
1077 buf[8] = 0x2A;
1078 buf[9] = 30 - 10;
1079 buf[10] = 0x08;
1080 buf[12] = 0x71;
1081 be16enc(&buf[18], 2);
1082 be16enc(&buf[20], 512);
1083 write_prdt(p, slot, cfis, buf, len);
1084 tfd = ATA_S_READY | ATA_S_DSC;
1085 break;
1086 }
1087 default:
1088 goto error;
1089 break;
1090 }
1091 break;
1092 case 3:
1093 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1094 p->asc = 0x39;
1095 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1096 break;
1097error:
1098 case 1:
1099 case 2:
1100 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1101 p->asc = 0x24;
1102 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1103 break;
1104 }
1105 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1106 ahci_write_fis_d2h(p, slot, cfis, tfd);
1107}
1108
1109static void
1110atapi_get_event_status_notification(struct ahci_port *p, int slot,
1111 uint8_t *cfis)
1112{
1113 uint8_t *acmd;
1114 uint32_t tfd;
1115
1116 acmd = cfis + 0x40;
1117
1118 /* we don't support asynchronous operation */
1119 if (!(acmd[1] & 1)) {
1120 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1121 p->asc = 0x24;
1122 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1123 } else {
1124 uint8_t buf[8];
1125 int len;
1126
1127 len = be16dec(acmd + 7);
1128 if (len > sizeof(buf))
1129 len = sizeof(buf);
1130
1131 memset(buf, 0, sizeof(buf));
1132 be16enc(buf, 8 - 2);
1133 buf[2] = 0x04;
1134 buf[3] = 0x10;
1135 buf[5] = 0x02;
1136 write_prdt(p, slot, cfis, buf, len);
1137 tfd = ATA_S_READY | ATA_S_DSC;
1138 }
1139 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1140 ahci_write_fis_d2h(p, slot, cfis, tfd);
1141}
1142
1143static void
1144handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1145{
1146 uint8_t *acmd;
1147
1148 acmd = cfis + 0x40;
1149
1150#ifdef AHCI_DEBUG
1151 {
1152 int i;
1153 DPRINTF("ACMD:");
1154 for (i = 0; i < 16; i++)
1155 DPRINTF("%02x ", acmd[i]);
1156 DPRINTF("\n");
1157 }
1158#endif
1159
1160 switch (acmd[0]) {
1161 case TEST_UNIT_READY:
1162 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1163 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1164 break;
1165 case INQUIRY:
1166 atapi_inquiry(p, slot, cfis);
1167 break;
1168 case READ_CAPACITY:
1169 atapi_read_capacity(p, slot, cfis);
1170 break;
1171 case PREVENT_ALLOW:
1172 /* TODO */
1173 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1174 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1175 break;
1176 case READ_TOC:
1177 atapi_read_toc(p, slot, cfis);
1178 break;
1179 case READ_10:
1180 case READ_12:
1181 atapi_read(p, slot, cfis, 0, 0);
1182 break;
1183 case REQUEST_SENSE:
1184 atapi_request_sense(p, slot, cfis);
1185 break;
1186 case START_STOP_UNIT:
1187 atapi_start_stop_unit(p, slot, cfis);
1188 break;
1189 case MODE_SENSE_10:
1190 atapi_mode_sense(p, slot, cfis);
1191 break;
1192 case GET_EVENT_STATUS_NOTIFICATION:
1193 atapi_get_event_status_notification(p, slot, cfis);
1194 break;
1195 default:
1196 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1197 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1198 p->asc = 0x20;
1199 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1200 ATA_S_READY | ATA_S_ERROR);
1201 break;
1202 }
1203}
1204
1205static void
1206ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1207{
1208
1209 switch (cfis[2]) {
1210 case ATA_ATA_IDENTIFY:
1211 handle_identify(p, slot, cfis);
1212 break;
1213 case ATA_SETFEATURES:
1214 {
1215 switch (cfis[3]) {
1216 case ATA_SF_ENAB_SATA_SF:
1217 switch (cfis[12]) {
1218 case ATA_SATA_SF_AN:
1219 p->tfd = ATA_S_DSC | ATA_S_READY;
1220 break;
1221 default:
1222 p->tfd = ATA_S_ERROR | ATA_S_READY;
1223 p->tfd |= (ATA_ERROR_ABORT << 8);
1224 break;
1225 }
1226 break;
1227 case ATA_SF_ENAB_WCACHE:
1228 case ATA_SF_DIS_WCACHE:
1229 case ATA_SF_ENAB_RCACHE:
1230 case ATA_SF_DIS_RCACHE:
1231 p->tfd = ATA_S_DSC | ATA_S_READY;
1232 break;
1233 case ATA_SF_SETXFER:
1234 {
1235 switch (cfis[12] & 0xf8) {
1236 case ATA_PIO:
1237 case ATA_PIO0:
1238 break;
1239 case ATA_WDMA0:
1240 case ATA_UDMA0:
1241 p->xfermode = (cfis[12] & 0x7);
1242 break;
1243 }
1244 p->tfd = ATA_S_DSC | ATA_S_READY;
1245 break;
1246 }
1247 default:
1248 p->tfd = ATA_S_ERROR | ATA_S_READY;
1249 p->tfd |= (ATA_ERROR_ABORT << 8);
1250 break;
1251 }
1252 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1253 break;
1254 }
1255 case ATA_SET_MULTI:
1256 if (cfis[12] != 0 &&
1257 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1258 p->tfd = ATA_S_ERROR | ATA_S_READY;
1259 p->tfd |= (ATA_ERROR_ABORT << 8);
1260 } else {
1261 p->mult_sectors = cfis[12];
1262 p->tfd = ATA_S_DSC | ATA_S_READY;
1263 }
1264 p->is |= AHCI_P_IX_DP;
1265 p->ci &= ~(1 << slot);
1266 ahci_generate_intr(p->pr_sc);
1267 break;
1268 case ATA_READ_DMA:
1269 case ATA_WRITE_DMA:
1270 case ATA_READ_DMA48:
1271 case ATA_WRITE_DMA48:
1272 case ATA_READ_FPDMA_QUEUED:
1273 case ATA_WRITE_FPDMA_QUEUED:
1274 ahci_handle_dma(p, slot, cfis, 0, 0);
1275 break;
1276 case ATA_FLUSHCACHE:
1277 case ATA_FLUSHCACHE48:
1278 ahci_handle_flush(p, slot, cfis);
1279 break;
1280 case ATA_STANDBY_CMD:
1281 break;
1282 case ATA_NOP:
1283 case ATA_STANDBY_IMMEDIATE:
1284 case ATA_IDLE_IMMEDIATE:
1285 case ATA_SLEEP:
1286 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1287 break;
1288 case ATA_ATAPI_IDENTIFY:
1289 handle_atapi_identify(p, slot, cfis);
1290 break;
1291 case ATA_PACKET_CMD:
1292 if (!p->atapi) {
1293 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1294 p->is |= AHCI_P_IX_TFE;
1295 p->ci &= ~(1 << slot);
1296 ahci_generate_intr(p->pr_sc);
1297 } else
1298 handle_packet_cmd(p, slot, cfis);
1299 break;
1300 default:
1301 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1302 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1303 p->is |= AHCI_P_IX_TFE;
1304 p->ci &= ~(1 << slot);
1305 ahci_generate_intr(p->pr_sc);
1306 break;
1307 }
1308}
1309
1310static void
1311ahci_handle_slot(struct ahci_port *p, int slot)
1312{
1313 struct ahci_cmd_hdr *hdr;
1314 struct ahci_prdt_entry *prdt;
1315 struct pci_ahci_softc *sc;
1316 uint8_t *cfis;
1317 int cfl;
1318
1319 sc = p->pr_sc;
1320 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1321 cfl = (hdr->flags & 0x1f) * 4;
1322 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1323 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1324 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1325
1326#ifdef AHCI_DEBUG
1327 DPRINTF("\ncfis:");
1328 for (i = 0; i < cfl; i++) {
1329 if (i % 10 == 0)
1330 DPRINTF("\n");
1331 DPRINTF("%02x ", cfis[i]);
1332 }
1333 DPRINTF("\n");
1334
1335 for (i = 0; i < hdr->prdtl; i++) {
1336 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1337 prdt++;
1338 }
1339#endif
1340
1341 if (cfis[0] != FIS_TYPE_REGH2D) {
1342 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1343 return;
1344 }
1345
1346 if (cfis[1] & 0x80) {
1347 ahci_handle_cmd(p, slot, cfis);
1348 } else {
1349 if (cfis[15] & (1 << 2))
1350 p->reset = 1;
1351 else if (p->reset) {
1352 p->reset = 0;
1353 ahci_port_reset(p);
1354 }
1355 p->ci &= ~(1 << slot);
1356 }
1357}
1358
1359static void
1360ahci_handle_port(struct ahci_port *p)
1361{
1362 int i;
1363
1364 if (!(p->cmd & AHCI_P_CMD_ST))
1365 return;
1366
1367 /*
1368 * Search for any new commands to issue ignoring those that
1369 * are already in-flight.
1370 */
1371 for (i = 0; (i < 32) && p->ci; i++) {
1372 if ((p->ci & (1 << i)) && !(p->pending & (1 << i)))
1373 ahci_handle_slot(p, i);
1374 }
1375}
1376
1377/*
1378 * blockif callback routine - this runs in the context of the blockif
1379 * i/o thread, so the mutex needs to be acquired.
1380 */
1381static void
1382ata_ioreq_cb(struct blockif_req *br, int err)
1383{
1384 struct ahci_cmd_hdr *hdr;
1385 struct ahci_ioreq *aior;
1386 struct ahci_port *p;
1387 struct pci_ahci_softc *sc;
1388 uint32_t tfd;
1389 uint8_t *cfis;
1390 int pending, slot, ncq;
1391
1392 DPRINTF("%s %d\n", __func__, err);
1393
1394 ncq = 0;
1395 aior = br->br_param;
1396 p = aior->io_pr;
1397 cfis = aior->cfis;
1398 slot = aior->slot;
1399 pending = aior->prdtl;
1400 sc = p->pr_sc;
1401 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1402
1403 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1404 cfis[2] == ATA_READ_FPDMA_QUEUED)
1405 ncq = 1;
1406
1407 pthread_mutex_lock(&sc->mtx);
1408
1409 /*
1410 * Move the blockif request back to the free list
1411 */
1412 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1413
1414 if (pending && !err) {
1415 ahci_handle_dma(p, slot, cfis, aior->done,
1416 hdr->prdtl - pending);
1417 goto out;
1418 }
1419
1420 if (!err && aior->done == aior->len) {
1421 tfd = ATA_S_READY | ATA_S_DSC;
1422 if (ncq)
1423 hdr->prdbc = 0;
1424 else
1425 hdr->prdbc = aior->len;
1426 } else {
1427 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1428 hdr->prdbc = 0;
1429 if (ncq)
1430 p->serr |= (1 << slot);
1431 }
1432
1433 /*
1434 * This command is now complete.
1435 */
1436 p->pending &= ~(1 << slot);
1437
1438 if (ncq) {
1439 p->sact &= ~(1 << slot);
1440 ahci_write_fis_sdb(p, slot, tfd);
1441 } else
1442 ahci_write_fis_d2h(p, slot, cfis, tfd);
1443
1444out:
1445 pthread_mutex_unlock(&sc->mtx);
1446 DPRINTF("%s exit\n", __func__);
1447}
1448
1449static void
1450atapi_ioreq_cb(struct blockif_req *br, int err)
1451{
1452 struct ahci_cmd_hdr *hdr;
1453 struct ahci_ioreq *aior;
1454 struct ahci_port *p;
1455 struct pci_ahci_softc *sc;
1456 uint8_t *cfis;
1457 uint32_t tfd;
1458 int pending, slot;
1459
1460 DPRINTF("%s %d\n", __func__, err);
1461
1462 aior = br->br_param;
1463 p = aior->io_pr;
1464 cfis = aior->cfis;
1465 slot = aior->slot;
1466 pending = aior->prdtl;
1467 sc = p->pr_sc;
1468 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1469
1470 pthread_mutex_lock(&sc->mtx);
1471
1472 /*
1473 * Move the blockif request back to the free list
1474 */
1475 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1476
1477 if (pending && !err) {
1478 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1479 goto out;
1480 }
1481
1482 if (!err && aior->done == aior->len) {
1483 tfd = ATA_S_READY | ATA_S_DSC;
1484 hdr->prdbc = aior->len;
1485 } else {
1486 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1487 p->asc = 0x21;
1488 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1489 hdr->prdbc = 0;
1490 }
1491
1492 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1493 ahci_write_fis_d2h(p, slot, cfis, tfd);
1494
1495out:
1496 pthread_mutex_unlock(&sc->mtx);
1497 DPRINTF("%s exit\n", __func__);
1498}
1499
1500static void
1501pci_ahci_ioreq_init(struct ahci_port *pr)
1502{
1503 struct ahci_ioreq *vr;
1504 int i;
1505
1506 pr->ioqsz = blockif_queuesz(pr->bctx);
1507 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1508 STAILQ_INIT(&pr->iofhd);
1509
1510 /*
1511 * Add all i/o request entries to the free queue
1512 */
1513 for (i = 0; i < pr->ioqsz; i++) {
1514 vr = &pr->ioreq[i];
1515 vr->io_pr = pr;
1516 if (!pr->atapi)
1517 vr->io_req.br_callback = ata_ioreq_cb;
1518 else
1519 vr->io_req.br_callback = atapi_ioreq_cb;
1520 vr->io_req.br_param = vr;
1521 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_list);
1522 }
1523}
1524
1525static void
1526pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1527{
1528 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1529 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1530 struct ahci_port *p = &sc->port[port];
1531
1532 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1533 port, offset, value);
1534
1535 switch (offset) {
1536 case AHCI_P_CLB:
1537 p->clb = value;
1538 break;
1539 case AHCI_P_CLBU:
1540 p->clbu = value;
1541 break;
1542 case AHCI_P_FB:
1543 p->fb = value;
1544 break;
1545 case AHCI_P_FBU:
1546 p->fbu = value;
1547 break;
1548 case AHCI_P_IS:
1549 p->is &= ~value;
1550 break;
1551 case AHCI_P_IE:
1552 p->ie = value & 0xFDC000FF;
1553 ahci_generate_intr(sc);
1554 break;
1555 case AHCI_P_CMD:
1556 {
1557 p->cmd = value;
1558
1559 if (!(value & AHCI_P_CMD_ST)) {
1560 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
1561 p->ci = 0;
1562 p->sact = 0;
1563 } else {
1564 uint64_t clb;
1565
1566 p->cmd |= AHCI_P_CMD_CR;
1567 clb = (uint64_t)p->clbu << 32 | p->clb;
1568 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1569 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1570 }
1571
1572 if (value & AHCI_P_CMD_FRE) {
1573 uint64_t fb;
1574
1575 p->cmd |= AHCI_P_CMD_FR;
1576 fb = (uint64_t)p->fbu << 32 | p->fb;
1577 /* we don't support FBSCP, so rfis size is 256Bytes */
1578 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1579 } else {
1580 p->cmd &= ~AHCI_P_CMD_FR;
1581 }
1582
1583 if (value & AHCI_P_CMD_CLO) {
1584 p->tfd = 0;
1585 p->cmd &= ~AHCI_P_CMD_CLO;
1586 }
1587
1588 ahci_handle_port(p);
1589 break;
1590 }
1591 case AHCI_P_TFD:
1592 case AHCI_P_SIG:
1593 case AHCI_P_SSTS:
1594 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1595 break;
1596 case AHCI_P_SCTL:
1597 if (!(p->cmd & AHCI_P_CMD_ST)) {
1598 if (value & ATA_SC_DET_RESET)
1599 ahci_port_reset(p);
1600 p->sctl = value;
1601 }
1602 break;
1603 case AHCI_P_SERR:
1604 p->serr &= ~value;
1605 break;
1606 case AHCI_P_SACT:
1607 p->sact |= value;
1608 break;
1609 case AHCI_P_CI:
1610 p->ci |= value;
1611 ahci_handle_port(p);
1612 break;
1613 case AHCI_P_SNTF:
1614 case AHCI_P_FBS:
1615 default:
1616 break;
1617 }
1618}
1619
1620static void
1621pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1622{
1623 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1624 offset, value);
1625
1626 switch (offset) {
1627 case AHCI_CAP:
1628 case AHCI_PI:
1629 case AHCI_VS:
1630 case AHCI_CAP2:
1631 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1632 break;
1633 case AHCI_GHC:
1634 if (value & AHCI_GHC_HR)
1635 ahci_reset(sc);
1636 else if (value & AHCI_GHC_IE) {
1637 sc->ghc |= AHCI_GHC_IE;
1638 ahci_generate_intr(sc);
1639 }
1640 break;
1641 case AHCI_IS:
1642 sc->is &= ~value;
1643 ahci_generate_intr(sc);
1644 break;
1645 default:
1646 break;
1647 }
1648}
1649
1650static void
1651pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1652 int baridx, uint64_t offset, int size, uint64_t value)
1653{
1654 struct pci_ahci_softc *sc = pi->pi_arg;
1655
1656 assert(baridx == 5);
1657 assert(size == 4);
1658
1659 pthread_mutex_lock(&sc->mtx);
1660
1661 if (offset < AHCI_OFFSET)
1662 pci_ahci_host_write(sc, offset, value);
1663 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1664 pci_ahci_port_write(sc, offset, value);
1665 else
1666 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1667
1668 pthread_mutex_unlock(&sc->mtx);
1669}
1670
1671static uint64_t
1672pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
1673{
1674 uint32_t value;
1675
1676 switch (offset) {
1677 case AHCI_CAP:
1678 case AHCI_GHC:
1679 case AHCI_IS:
1680 case AHCI_PI:
1681 case AHCI_VS:
1682 case AHCI_CCCC:
1683 case AHCI_CCCP:
1684 case AHCI_EM_LOC:
1685 case AHCI_EM_CTL:
1686 case AHCI_CAP2:
1687 {
1688 uint32_t *p = &sc->cap;
1689 p += (offset - AHCI_CAP) / sizeof(uint32_t);
1690 value = *p;
1691 break;
1692 }
1693 default:
1694 value = 0;
1695 break;
1696 }
1697 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
1698 offset, value);
1699
1700 return (value);
1701}
1702
1703static uint64_t
1704pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
1705{
1706 uint32_t value;
1707 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1708 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1709
1710 switch (offset) {
1711 case AHCI_P_CLB:
1712 case AHCI_P_CLBU:
1713 case AHCI_P_FB:
1714 case AHCI_P_FBU:
1715 case AHCI_P_IS:
1716 case AHCI_P_IE:
1717 case AHCI_P_CMD:
1718 case AHCI_P_TFD:
1719 case AHCI_P_SIG:
1720 case AHCI_P_SSTS:
1721 case AHCI_P_SCTL:
1722 case AHCI_P_SERR:
1723 case AHCI_P_SACT:
1724 case AHCI_P_CI:
1725 case AHCI_P_SNTF:
1726 case AHCI_P_FBS:
1727 {
1728 uint32_t *p= &sc->port[port].clb;
1729 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
1730 value = *p;
1731 break;
1732 }
1733 default:
1734 value = 0;
1735 break;
1736 }
1737
1738 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
1739 port, offset, value);
1740
1741 return value;
1742}
1743
1744static uint64_t
1745pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1746 uint64_t offset, int size)
1747{
1748 struct pci_ahci_softc *sc = pi->pi_arg;
1749 uint32_t value;
1750
1751 assert(baridx == 5);
1752 assert(size == 4);
1753
1754 pthread_mutex_lock(&sc->mtx);
1755
1756 if (offset < AHCI_OFFSET)
1757 value = pci_ahci_host_read(sc, offset);
1758 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1759 value = pci_ahci_port_read(sc, offset);
1760 else {
1761 value = 0;
1762 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
1763 }
1764
1765 pthread_mutex_unlock(&sc->mtx);
1766
1767 return (value);
1768}
1769
1770static int
1771pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
1772{
1773 char bident[sizeof("XX:X:X")];
1774 struct blockif_ctxt *bctxt;
1775 struct pci_ahci_softc *sc;
1776 int ret, slots;
1777
1778 ret = 0;
1779
1780 if (opts == NULL) {
1781 fprintf(stderr, "pci_ahci: backing device required\n");
1782 return (1);
1783 }
1784
1785#ifdef AHCI_DEBUG
1786 dbg = fopen("/tmp/log", "w+");
1787#endif
1788
1789 sc = malloc(sizeof(struct pci_ahci_softc));
1790 memset(sc, 0, sizeof(struct pci_ahci_softc));
1791 pi->pi_arg = sc;
1792 sc->asc_pi = pi;
1793 sc->ports = MAX_PORTS;
1794
1795 /*
1796 * Only use port 0 for a backing device. All other ports will be
1797 * marked as unused
1798 */
1799 sc->port[0].atapi = atapi;
1800
1801 /*
1802 * Attempt to open the backing image. Use the PCI
1803 * slot/func for the identifier string.
1804 */
1805 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func);
1806 bctxt = blockif_open(opts, bident);
1807 if (bctxt == NULL) {
1808 ret = 1;
1809 goto open_fail;
1810 }
1811 sc->port[0].bctx = bctxt;
1812 sc->port[0].pr_sc = sc;
1813
1814 /*
1815 * Allocate blockif request structures and add them
1816 * to the free list
1817 */
1818 pci_ahci_ioreq_init(&sc->port[0]);
1819
1820 pthread_mutex_init(&sc->mtx, NULL);
1821
1822 /* Intel ICH8 AHCI */
1823 slots = sc->port[0].ioqsz;
1824 if (slots > 32)
1825 slots = 32;
1826 --slots;
1827 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
1828 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
1829 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
1830 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
1831 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
1832
1833 /* Only port 0 implemented */
1834 sc->pi = 1;
1835 sc->vs = 0x10300;
1836 sc->cap2 = AHCI_CAP2_APST;
1837 ahci_reset(sc);
1838
1839 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
1840 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
1841 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
1842 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
1843 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
1844 pci_emul_add_msicap(pi, 1);
1845 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
1846 AHCI_OFFSET + sc->ports * AHCI_STEP);
1847
|