1/*-
2 * Copyright (c) 2004 John Baldwin <jhb@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2004 John Baldwin <jhb@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <sys/cdefs.h>
|
31__FBSDID("$FreeBSD: head/sys/x86/isa/elcr.c 241856 2012-10-22 03:41:14Z eadler $");
| 31__FBSDID("$FreeBSD: head/sys/x86/isa/elcr.c 241885 2012-10-22 13:06:09Z eadler $");
|
32
33/*
34 * The ELCR is a register that controls the trigger mode and polarity of
35 * EISA and ISA interrupts. In FreeBSD 3.x and 4.x, the ELCR was only
36 * consulted for determining the appropriate trigger mode of EISA
37 * interrupts when using an APIC. However, it seems that almost all
38 * systems that include PCI also include an ELCR that manages the ISA
39 * IRQs 0 through 15. Thus, we check for the presence of an ELCR on
40 * every machine by checking to see if the values found at bootup are
41 * sane. Note that the polarity of ISA and EISA IRQs are linked to the
42 * trigger mode. All edge triggered IRQs use active-hi polarity, and
43 * all level triggered interrupts use active-lo polarity.
44 *
45 * The format of the ELCR is simple: it is a 16-bit bitmap where bit 0
46 * controls IRQ 0, bit 1 controls IRQ 1, etc. If the bit is zero, the
47 * associated IRQ is edge triggered. If the bit is one, the IRQ is
48 * level triggered.
49 */
50
51#include <sys/param.h>
52#include <sys/bus.h>
53#include <sys/systm.h>
54#include <machine/intr_machdep.h>
55
56#define ELCR_PORT 0x4d0
57#define ELCR_MASK(irq) (1 << (irq))
58
59static int elcr_status;
60int elcr_found;
61
62/*
63 * Check to see if we have what looks like a valid ELCR. We do this by
64 * verifying that IRQs 0, 1, 2, and 13 are all edge triggered.
65 */
66int
67elcr_probe(void)
68{
69 int i;
70
71 elcr_status = inb(ELCR_PORT) | inb(ELCR_PORT + 1) << 8;
72 if ((elcr_status & (ELCR_MASK(0) | ELCR_MASK(1) | ELCR_MASK(2) |
73 ELCR_MASK(8) | ELCR_MASK(13))) != 0)
74 return (ENXIO);
75 if (bootverbose) {
76 printf("ELCR Found. ISA IRQs programmed as:\n");
77 for (i = 0; i < 16; i++)
78 printf(" %2d", i);
79 printf("\n");
80 for (i = 0; i < 16; i++)
81 if (elcr_status & ELCR_MASK(i))
82 printf(" L");
83 else
84 printf(" E");
85 printf("\n");
86 }
| 32
33/*
34 * The ELCR is a register that controls the trigger mode and polarity of
35 * EISA and ISA interrupts. In FreeBSD 3.x and 4.x, the ELCR was only
36 * consulted for determining the appropriate trigger mode of EISA
37 * interrupts when using an APIC. However, it seems that almost all
38 * systems that include PCI also include an ELCR that manages the ISA
39 * IRQs 0 through 15. Thus, we check for the presence of an ELCR on
40 * every machine by checking to see if the values found at bootup are
41 * sane. Note that the polarity of ISA and EISA IRQs are linked to the
42 * trigger mode. All edge triggered IRQs use active-hi polarity, and
43 * all level triggered interrupts use active-lo polarity.
44 *
45 * The format of the ELCR is simple: it is a 16-bit bitmap where bit 0
46 * controls IRQ 0, bit 1 controls IRQ 1, etc. If the bit is zero, the
47 * associated IRQ is edge triggered. If the bit is one, the IRQ is
48 * level triggered.
49 */
50
51#include <sys/param.h>
52#include <sys/bus.h>
53#include <sys/systm.h>
54#include <machine/intr_machdep.h>
55
56#define ELCR_PORT 0x4d0
57#define ELCR_MASK(irq) (1 << (irq))
58
59static int elcr_status;
60int elcr_found;
61
62/*
63 * Check to see if we have what looks like a valid ELCR. We do this by
64 * verifying that IRQs 0, 1, 2, and 13 are all edge triggered.
65 */
66int
67elcr_probe(void)
68{
69 int i;
70
71 elcr_status = inb(ELCR_PORT) | inb(ELCR_PORT + 1) << 8;
72 if ((elcr_status & (ELCR_MASK(0) | ELCR_MASK(1) | ELCR_MASK(2) |
73 ELCR_MASK(8) | ELCR_MASK(13))) != 0)
74 return (ENXIO);
75 if (bootverbose) {
76 printf("ELCR Found. ISA IRQs programmed as:\n");
77 for (i = 0; i < 16; i++)
78 printf(" %2d", i);
79 printf("\n");
80 for (i = 0; i < 16; i++)
81 if (elcr_status & ELCR_MASK(i))
82 printf(" L");
83 else
84 printf(" E");
85 printf("\n");
86 }
|
| 87 if (resource_disabled("elcr", 0))
88 return (ENXIO);
|
87 elcr_found = 1;
88 return (0);
89}
90
91/*
92 * Returns 1 for level trigger, 0 for edge.
93 */
94enum intr_trigger
95elcr_read_trigger(u_int irq)
96{
97
98 KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
99 KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
100 if (elcr_status & ELCR_MASK(irq))
101 return (INTR_TRIGGER_LEVEL);
102 else
103 return (INTR_TRIGGER_EDGE);
104}
105
106/*
107 * Set the trigger mode for a specified IRQ. Mode of 0 means edge triggered,
108 * and a mode of 1 means level triggered.
109 */
110void
111elcr_write_trigger(u_int irq, enum intr_trigger trigger)
112{
113 int new_status;
114
115 KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
116 KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
117 if (trigger == INTR_TRIGGER_LEVEL)
118 new_status = elcr_status | ELCR_MASK(irq);
119 else
120 new_status = elcr_status & ~ELCR_MASK(irq);
121 if (new_status == elcr_status)
122 return;
123 elcr_status = new_status;
124 if (irq >= 8)
125 outb(ELCR_PORT + 1, elcr_status >> 8);
126 else
127 outb(ELCR_PORT, elcr_status & 0xff);
128}
129
130void
131elcr_resume(void)
132{
133
134 KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
135 outb(ELCR_PORT, elcr_status & 0xff);
136 outb(ELCR_PORT + 1, elcr_status >> 8);
137}
| 89 elcr_found = 1;
90 return (0);
91}
92
93/*
94 * Returns 1 for level trigger, 0 for edge.
95 */
96enum intr_trigger
97elcr_read_trigger(u_int irq)
98{
99
100 KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
101 KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
102 if (elcr_status & ELCR_MASK(irq))
103 return (INTR_TRIGGER_LEVEL);
104 else
105 return (INTR_TRIGGER_EDGE);
106}
107
108/*
109 * Set the trigger mode for a specified IRQ. Mode of 0 means edge triggered,
110 * and a mode of 1 means level triggered.
111 */
112void
113elcr_write_trigger(u_int irq, enum intr_trigger trigger)
114{
115 int new_status;
116
117 KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
118 KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
119 if (trigger == INTR_TRIGGER_LEVEL)
120 new_status = elcr_status | ELCR_MASK(irq);
121 else
122 new_status = elcr_status & ~ELCR_MASK(irq);
123 if (new_status == elcr_status)
124 return;
125 elcr_status = new_status;
126 if (irq >= 8)
127 outb(ELCR_PORT + 1, elcr_status >> 8);
128 else
129 outb(ELCR_PORT, elcr_status & 0xff);
130}
131
132void
133elcr_resume(void)
134{
135
136 KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
137 outb(ELCR_PORT, elcr_status & 0xff);
138 outb(ELCR_PORT + 1, elcr_status >> 8);
139}
|