111#include <sys/pcpu.h>
112#include <sys/reboot.h>
113
114#include <dev/ofw/openfirm.h>
115
116#include <machine/bus.h>
117#include <machine/bus_private.h>
118#include <machine/iommureg.h>
119#include <machine/bus_common.h>
120#include <machine/frame.h>
121#include <machine/intr_machdep.h>
122#include <machine/nexusvar.h>
123#include <machine/ofw_upa.h>
124#include <machine/resource.h>
125
126#include <sys/rman.h>
127
128#include <machine/iommuvar.h>
129
130#include <sparc64/sbus/ofw_sbus.h>
131#include <sparc64/sbus/sbusreg.h>
132#include <sparc64/sbus/sbusvar.h>
133
134
135#ifdef DEBUG
136#define SDB_DVMA 0x1
137#define SDB_INTR 0x2
138int sbus_debug = 0;
139#define DPRINTF(l, s) do { if (sbus_debug & l) printf s; } while (0)
140#else
141#define DPRINTF(l, s)
142#endif
143
144struct sbus_devinfo {
145 int sdi_burstsz;
146 char *sdi_compat;
147 char *sdi_name; /* PROM name */
148 phandle_t sdi_node; /* PROM node */
149 int sdi_slot;
150 char *sdi_type; /* PROM name */
151
152 struct resource_list sdi_rl;
153};
154
155/* Range descriptor, allocated for each sc_range. */
156struct sbus_rd {
157 bus_addr_t rd_poffset;
158 bus_addr_t rd_pend;
159 int rd_slot;
160 bus_addr_t rd_coffset;
161 bus_addr_t rd_cend;
162 struct rman rd_rman;
163 bus_space_handle_t rd_bushandle;
164 struct resource *rd_res;
165};
166
167struct sbus_softc {
168 bus_space_tag_t sc_bustag;
169 bus_space_handle_t sc_bushandle;
170 bus_dma_tag_t sc_dmatag;
171 bus_dma_tag_t sc_cdmatag;
172 bus_space_tag_t sc_cbustag;
173 int sc_clockfreq; /* clock frequency (in Hz) */
174 struct upa_regs *sc_reg;
175 int sc_nreg;
176 int sc_nrange;
177 struct sbus_rd *sc_rd;
178 int sc_burst; /* burst transfer sizes supported */
179 int *sc_intr_compat;/* `intr' property to sbus compat */
180
181 struct resource *sc_sysio_res;
182 int sc_ign; /* Interrupt group number for this sysio */
183 struct iommu_state sc_is; /* IOMMU state, see iommureg.h */
184
185 struct resource *sc_ot_ires;
186 void *sc_ot_ihand;
187 struct resource *sc_pf_ires;
188 void *sc_pf_ihand;
189};
190
191struct sbus_clr {
192 struct sbus_softc *scl_sc;
193 bus_addr_t scl_clr; /* clear register */
194 driver_intr_t *scl_handler; /* handler to call */
195 void *scl_arg; /* argument for the handler */
196 void *scl_cookie; /* interrupt cookie of parent bus */
197};
198
199#define SYSIO_READ8(sc, off) \
200 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off))
201#define SYSIO_WRITE8(sc, off, v) \
202 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v))
203
204static int sbus_probe(device_t dev);
205static int sbus_print_child(device_t dev, device_t child);
206static void sbus_probe_nomatch(device_t dev, device_t child);
207static int sbus_read_ivar(device_t, device_t, int, u_long *);
208static struct resource_list *sbus_get_resource_list(device_t dev,
209 device_t child);
210static int sbus_setup_intr(device_t, device_t, struct resource *, int,
211 driver_intr_t *, void *, void **);
212static int sbus_teardown_intr(device_t, device_t, struct resource *, void *);
213static struct resource *sbus_alloc_resource(device_t, device_t, int, int *,
214 u_long, u_long, u_long, u_int);
215static int sbus_activate_resource(device_t, device_t, int, int,
216 struct resource *);
217static int sbus_deactivate_resource(device_t, device_t, int, int,
218 struct resource *);
219static int sbus_release_resource(device_t, device_t, int, int,
220 struct resource *);
221
222static struct sbus_devinfo * sbus_setup_dinfo(struct sbus_softc *sc,
223 phandle_t node, char *name);
224static void sbus_destroy_dinfo(struct sbus_devinfo *dinfo);
225static void sbus_intr_stub(void *);
226static bus_space_tag_t sbus_alloc_bustag(struct sbus_softc *);
227static void sbus_overtemp(void *);
228static void sbus_pwrfail(void *);
229
230static device_method_t sbus_methods[] = {
231 /* Device interface */
232 DEVMETHOD(device_probe, sbus_probe),
233 DEVMETHOD(device_attach, bus_generic_attach),
234
235 /* Bus interface */
236 DEVMETHOD(bus_print_child, sbus_print_child),
237 DEVMETHOD(bus_probe_nomatch, sbus_probe_nomatch),
238 DEVMETHOD(bus_read_ivar, sbus_read_ivar),
239 DEVMETHOD(bus_setup_intr, sbus_setup_intr),
240 DEVMETHOD(bus_teardown_intr, sbus_teardown_intr),
241 DEVMETHOD(bus_alloc_resource, sbus_alloc_resource),
242 DEVMETHOD(bus_activate_resource, sbus_activate_resource),
243 DEVMETHOD(bus_deactivate_resource, sbus_deactivate_resource),
244 DEVMETHOD(bus_release_resource, sbus_release_resource),
245 DEVMETHOD(bus_get_resource_list, sbus_get_resource_list),
246 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
247
248 { 0, 0 }
249};
250
251static driver_t sbus_driver = {
252 "sbus",
253 sbus_methods,
254 sizeof(struct sbus_softc),
255};
256
257static devclass_t sbus_devclass;
258
259DRIVER_MODULE(sbus, nexus, sbus_driver, sbus_devclass, 0, 0);
260
261#define OFW_SBUS_TYPE "sbus"
262#define OFW_SBUS_NAME "sbus"
263
264static int
265sbus_probe(device_t dev)
266{
267 struct sbus_softc *sc = device_get_softc(dev);
268 struct sbus_devinfo *sdi;
269 struct sbus_ranges *range;
270 struct resource *res;
271 device_t cdev;
272 bus_addr_t phys;
273 bus_size_t size;
274 char *name, *cname, *t;
275 phandle_t child, node = nexus_get_node(dev);
276 u_int64_t mr;
277 int intr, clock, rid, vec, i;
278
279 t = nexus_get_device_type(dev);
280 if (((t == NULL || strcmp(t, OFW_SBUS_TYPE) != 0)) &&
281 strcmp(nexus_get_name(dev), OFW_SBUS_NAME) != 0)
282 return (ENXIO);
283 device_set_desc(dev, "U2S UPA-SBus bridge");
284
285 if ((sc->sc_nreg = OF_getprop_alloc(node, "reg", sizeof(*sc->sc_reg),
286 (void **)&sc->sc_reg)) == -1) {
287 panic("sbus_probe: error getting reg property");
288 }
289 if (sc->sc_nreg < 1)
290 panic("sbus_probe: bogus properties");
291 phys = UPA_REG_PHYS(&sc->sc_reg[0]);
292 size = UPA_REG_SIZE(&sc->sc_reg[0]);
293 rid = 0;
294 sc->sc_sysio_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, phys,
295 phys + size - 1, size, RF_ACTIVE);
296 if (sc->sc_sysio_res == NULL ||
297 rman_get_start(sc->sc_sysio_res) != phys)
298 panic("sbus_probe: can't allocate device memory");
299 sc->sc_bustag = rman_get_bustag(sc->sc_sysio_res);
300 sc->sc_bushandle = rman_get_bushandle(sc->sc_sysio_res);
301
302 if (OF_getprop(node, "interrupts", &intr, sizeof(intr)) == -1)
303 panic("sbus_probe: cannot get IGN");
304 sc->sc_ign = intr & INTMAP_IGN_MASK; /* Find interrupt group no */
305 sc->sc_cbustag = sbus_alloc_bustag(sc);
306
307 /*
308 * Record clock frequency for synchronous SCSI.
309 * IS THIS THE CORRECT DEFAULT??
310 */
311 if (OF_getprop(node, "clock-frequency", &clock, sizeof(clock)) == -1)
312 clock = 25000000;
313 sc->sc_clockfreq = clock;
314 clock /= 1000;
315 device_printf(dev, "clock %d.%03d MHz\n", clock / 1000, clock % 1000);
316
317 /*
318 * Collect address translations from the OBP.
319 */
320 if ((sc->sc_nrange = OF_getprop_alloc(node, "ranges",
321 sizeof(*range), (void **)&range)) == -1) {
322 panic("%s: error getting ranges property",
323 device_get_name(dev));
324 }
325 sc->sc_rd = (struct sbus_rd *)malloc(sizeof(*sc->sc_rd) * sc->sc_nrange,
326 M_DEVBUF, M_NOWAIT);
327 if (sc->sc_rd == NULL)
328 panic("sbus_probe: could not allocate rmans");
329 /*
330 * Preallocate all space that the SBus bridge decodes, so that nothing
331 * else gets in the way; set up rmans etc.
332 */
333 for (i = 0; i < sc->sc_nrange; i++) {
334 phys = range[i].poffset | ((bus_addr_t)range[i].pspace << 32);
335 size = range[i].size;
336 sc->sc_rd[i].rd_slot = range[i].cspace;
337 sc->sc_rd[i].rd_coffset = range[i].coffset;
338 sc->sc_rd[i].rd_cend = sc->sc_rd[i].rd_coffset + size;
339 rid = 0;
340 if ((res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, phys,
341 phys + size - 1, size, RF_ACTIVE)) == NULL)
342 panic("sbus_probe: could not allocate decoded range");
343 sc->sc_rd[i].rd_bushandle = rman_get_bushandle(res);
344 sc->sc_rd[i].rd_rman.rm_type = RMAN_ARRAY;
345 sc->sc_rd[i].rd_rman.rm_descr = "SBus Device Memory";
346 if (rman_init(&sc->sc_rd[i].rd_rman) != 0 ||
347 rman_manage_region(&sc->sc_rd[i].rd_rman, 0, size) != 0)
348 panic("sbus_probe: failed to set up memory rman");
349 sc->sc_rd[i].rd_poffset = phys;
350 sc->sc_rd[i].rd_pend = phys + size;
351 sc->sc_rd[i].rd_res = res;
352 }
353 free(range, M_OFWPROP);
354
355 /*
356 * Get the SBus burst transfer size if burst transfers are supported.
357 * XXX: is the default correct?
358 */
359 if (OF_getprop(node, "burst-sizes", &sc->sc_burst,
360 sizeof(sc->sc_burst)) == -1 || sc->sc_burst == 0)
361 sc->sc_burst = SBUS_BURST_DEF;
362
363 /* initalise the IOMMU */
364
365 /* punch in our copies */
366 sc->sc_is.is_bustag = sc->sc_bustag;
367 sc->sc_is.is_bushandle = sc->sc_bushandle;
368 sc->sc_is.is_iommu = SBR_IOMMU;
369 sc->sc_is.is_dtag = SBR_IOMMU_TLB_TAG_DIAG;
370 sc->sc_is.is_ddram = SBR_IOMMU_TLB_DATA_DIAG;
371 sc->sc_is.is_dqueue = SBR_IOMMU_QUEUE_DIAG;
372 sc->sc_is.is_dva = SBR_IOMMU_SVADIAG;
373 sc->sc_is.is_dtcmp = 0;
374 sc->sc_is.is_sb[0] = SBR_STRBUF;
375 sc->sc_is.is_sb[1] = 0;
376
377 /* give us a nice name.. */
378 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT);
379 if (name == 0)
380 panic("sbus_probe: couldn't malloc iommu name");
381 snprintf(name, 32, "%s dvma", device_get_name(dev));
382
383 /*
384 * Note: the SBus IOMMU ignores the high bits of an address, so a NULL
385 * DMA pointer will be translated by the first page of the IOTSB.
386 * To detect bugs we'll allocate and ignore the first entry.
387 */
388 iommu_init(name, &sc->sc_is, 3, -1, 1);
389
390 /* Create the DMA tag. */
391 sc->sc_dmatag = nexus_get_dmatag(dev);
392 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL,
393 0x3ffffffff, 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_cdmatag) != 0)
394 panic("bus_dma_tag_create failed");
395 /* Customize the tag. */
396 sc->sc_cdmatag->dt_cookie = &sc->sc_is;
397 sc->sc_cdmatag->dt_mt = &iommu_dma_methods;
398 /* XXX: register as root dma tag (kludge). */
399 sparc64_root_dma_tag = sc->sc_cdmatag;
400
401 /* Enable the over-temperature and power-fail intrrupts. */
402 rid = 0;
403 mr = SYSIO_READ8(sc, SBR_THERM_INT_MAP);
404 vec = INTVEC(mr);
405 if ((sc->sc_ot_ires = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, vec,
406 vec, 1, RF_ACTIVE)) == NULL)
407 panic("sbus_probe: failed to get temperature interrupt");
408 bus_setup_intr(dev, sc->sc_ot_ires, INTR_TYPE_MISC | INTR_FAST,
409 sbus_overtemp, sc, &sc->sc_ot_ihand);
410 SYSIO_WRITE8(sc, SBR_THERM_INT_MAP, INTMAP_ENABLE(mr, PCPU_GET(mid)));
411 rid = 0;
412 mr = SYSIO_READ8(sc, SBR_POWER_INT_MAP);
413 vec = INTVEC(mr);
414 if ((sc->sc_pf_ires = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, vec,
415 vec, 1, RF_ACTIVE)) == NULL)
416 panic("sbus_probe: failed to get power fail interrupt");
417 bus_setup_intr(dev, sc->sc_pf_ires, INTR_TYPE_MISC | INTR_FAST,
418 sbus_pwrfail, sc, &sc->sc_pf_ihand);
419 SYSIO_WRITE8(sc, SBR_POWER_INT_MAP, INTMAP_ENABLE(mr, PCPU_GET(mid)));
420
421 /* Initialize the counter-timer. */
422 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, SBR_TC0);
423
424 /*
425 * Loop through ROM children, fixing any relative addresses
426 * and then configuring each device.
427 * `specials' is an array of device names that are treated
428 * specially:
429 */
430 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
431 if ((OF_getprop_alloc(child, "name", 1, (void **)&cname)) == -1)
432 continue;
433
434 if ((sdi = sbus_setup_dinfo(sc, child, cname)) == NULL) {
435 device_printf(dev, "<%s>: incomplete\n", cname);
436 free(cname, M_OFWPROP);
437 continue;
438 }
439 if ((cdev = device_add_child(dev, NULL, -1)) == NULL)
440 panic("sbus_probe: device_add_child failed");
441 device_set_ivars(cdev, sdi);
442 }
443 return (0);
444}
445
446static struct sbus_devinfo *
447sbus_setup_dinfo(struct sbus_softc *sc, phandle_t node, char *name)
448{
449 struct sbus_devinfo *sdi;
450 struct sbus_regs *reg;
451 u_int32_t base, iv, *intr;
452 int i, nreg, nintr, slot, rslot;
453
454 sdi = malloc(sizeof(*sdi), M_DEVBUF, M_ZERO | M_WAITOK);
455 if (sdi == NULL)
456 return (NULL);
457 resource_list_init(&sdi->sdi_rl);
458 sdi->sdi_name = name;
459 sdi->sdi_node = node;
460 OF_getprop_alloc(node, "compatible", 1, (void **)&sdi->sdi_compat);
461 OF_getprop_alloc(node, "device_type", 1, (void **)&sdi->sdi_type);
462 slot = -1;
463 nreg = OF_getprop_alloc(node, "reg", sizeof(*reg), (void **)®);
464 if (nreg == -1) {
465 if (sdi->sdi_type == NULL ||
466 strcmp(sdi->sdi_type, "hierarchical") != 0) {
467 sbus_destroy_dinfo(sdi);
468 return (NULL);
469 }
470 } else {
471 for (i = 0; i < nreg; i++) {
472 base = reg[i].sbr_offset;
473 if (SBUS_ABS(base)) {
474 rslot = SBUS_ABS_TO_SLOT(base);
475 base = SBUS_ABS_TO_OFFSET(base);
476 } else
477 rslot = reg[i].sbr_slot;
478 if (slot != -1 && slot != rslot)
479 panic("sbus_setup_dinfo: multiple slots");
480 slot = rslot;
481
482 resource_list_add(&sdi->sdi_rl, SYS_RES_MEMORY, i,
483 base, base + reg[i].sbr_size, reg[i].sbr_size);
484 }
485 free(reg, M_OFWPROP);
486 }
487 sdi->sdi_slot = slot;
488
489 /*
490 * The `interrupts' property contains the Sbus interrupt level.
491 */
492 nintr = OF_getprop_alloc(node, "interrupts", sizeof(*intr), (void **)&intr);
493 if (nintr != -1) {
494 for (i = 0; i < nintr; i++) {
495 iv = intr[i];
496 /*
497 * Sbus card devices need the slot number encoded into
498 * the vector as this is generally not done.
499 */
500 if ((iv & INTMAP_OBIO_MASK) == 0)
501 iv |= slot << 3;
502 /* Set the ign as appropriate. */
503 iv |= sc->sc_ign;
504 resource_list_add(&sdi->sdi_rl, SYS_RES_IRQ, i,
505 iv, iv, 1);
506 }
507 free(intr, M_OFWPROP);
508 }
509 if (OF_getprop(node, "burst-sizes", &sdi->sdi_burstsz,
510 sizeof(sdi->sdi_burstsz)) == -1)
511 sdi->sdi_burstsz = sc->sc_burst;
512 else
513 sdi->sdi_burstsz &= sc->sc_burst;
514
515 return (sdi);
516}
517
518/* Free everything except sdi_name, which is handled separately. */
519static void
520sbus_destroy_dinfo(struct sbus_devinfo *dinfo)
521{
522
523 resource_list_free(&dinfo->sdi_rl);
524 if (dinfo->sdi_compat != NULL)
525 free(dinfo->sdi_compat, M_OFWPROP);
526 if (dinfo->sdi_type != NULL)
527 free(dinfo->sdi_type, M_OFWPROP);
528 free(dinfo, M_DEVBUF);
529}
530
531static int
532sbus_print_child(device_t dev, device_t child)
533{
534 struct sbus_devinfo *dinfo;
535 struct resource_list *rl;
536 int rv;
537
538 dinfo = device_get_ivars(child);
539 rl = &dinfo->sdi_rl;
540 rv = bus_print_child_header(dev, child);
541 rv += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
542 rv += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
543 rv += bus_print_child_footer(dev, child);
544 return (rv);
545}
546
547static void
548sbus_probe_nomatch(device_t dev, device_t child)
549{
550 char *name;
551 char *type;
552
553 if (BUS_READ_IVAR(dev, child, SBUS_IVAR_NAME,
554 (uintptr_t *)&name) != 0 ||
555 BUS_READ_IVAR(dev, child, SBUS_IVAR_DEVICE_TYPE,
556 (uintptr_t *)&type) != 0)
557 return;
558
559 if (type == NULL)
560 type = "(unknown)";
561 device_printf(dev, "<%s>, type %s (no driver attached)\n",
562 name, type);
563}
564
565static int
566sbus_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
567{
568 struct sbus_softc *sc = device_get_softc(dev);
569 struct sbus_devinfo *dinfo;
570
571 if ((dinfo = device_get_ivars(child)) == NULL)
572 return (ENOENT);
573 switch (which) {
574 case SBUS_IVAR_BURSTSZ:
575 *result = dinfo->sdi_burstsz;
576 break;
577 case SBUS_IVAR_CLOCKFREQ:
578 *result = sc->sc_clockfreq;
579 break;
580 case SBUS_IVAR_COMPAT:
581 *result = (uintptr_t)dinfo->sdi_compat;
582 break;
583 case SBUS_IVAR_NAME:
584 *result = (uintptr_t)dinfo->sdi_name;
585 break;
586 case SBUS_IVAR_NODE:
587 *result = dinfo->sdi_node;
588 break;
589 case SBUS_IVAR_SLOT:
590 *result = dinfo->sdi_slot;
591 break;
592 case SBUS_IVAR_DEVICE_TYPE:
593 *result = (uintptr_t)dinfo->sdi_type;
594 break;
595 default:
596 return (ENOENT);
597 }
598 return 0;
599}
600
601static struct resource_list *
602sbus_get_resource_list(device_t dev, device_t child)
603{
604 struct sbus_devinfo *sdi;
605
606 sdi = device_get_ivars(child);
607 return (&sdi->sdi_rl);
608}
609
610/* Write to the correct clr register, and call the actual handler. */
611static void
612sbus_intr_stub(void *arg)
613{
614 struct sbus_clr *scl;
615
616 scl = (struct sbus_clr *)arg;
617 scl->scl_handler(scl->scl_arg);
618 SYSIO_WRITE8(scl->scl_sc, scl->scl_clr, 0);
619}
620
621static int
622sbus_setup_intr(device_t dev, device_t child,
623 struct resource *ires, int flags, driver_intr_t *intr, void *arg,
624 void **cookiep)
625{
626 struct sbus_softc *sc;
627 struct sbus_clr *scl;
628 bus_addr_t intrmapptr, intrclrptr, intrptr;
629 u_int64_t intrmap;
630 u_int32_t inr, slot;
631 int error, i;
632 long vec = rman_get_start(ires);
633
634 sc = (struct sbus_softc *)device_get_softc(dev);
635 scl = (struct sbus_clr *)malloc(sizeof(*scl), M_DEVBUF, M_NOWAIT);
636 if (scl == NULL)
637 return (0);
638 intrptr = intrmapptr = intrclrptr = 0;
639 intrmap = 0;
640 inr = INTVEC(vec);
641 if ((inr & INTMAP_OBIO_MASK) == 0) {
642 /*
643 * We're in an SBUS slot, register the map and clear
644 * intr registers.
645 */
646 slot = INTSLOT(vec);
647 intrmapptr = SBR_SLOT0_INT_MAP + slot * 8;
648 intrclrptr = SBR_SLOT0_INT_CLR +
649 (slot * 8 * 8) + (INTPRI(vec) * 8);
650 /* Enable the interrupt, insert IGN. */
651 intrmap = inr | sc->sc_ign;
652 } else {
653 intrptr = SBR_SCSI_INT_MAP;
654 /* Insert IGN */
655 inr |= sc->sc_ign;
656 for (i = 0; intrptr <= SBR_RESERVED_INT_MAP &&
657 INTVEC(intrmap = SYSIO_READ8(sc, intrptr)) !=
658 INTVEC(inr); intrptr += 8, i++)
659 ;
660 if (INTVEC(intrmap) == INTVEC(inr)) {
661 /* Register the map and clear intr registers */
662 intrmapptr = intrptr;
663 intrclrptr = SBR_SCSI_INT_CLR + i * 8;
664 /* Enable the interrupt */
665 } else
666 panic("sbus_setup_intr: IRQ not found!");
667 }
668
669 scl->scl_sc = sc;
670 scl->scl_arg = arg;
671 scl->scl_handler = intr;
672 scl->scl_clr = intrclrptr;
673 /* Disable the interrupt while we fiddle with it */
674 SYSIO_WRITE8(sc, intrmapptr, intrmap);
675 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
676 sbus_intr_stub, scl, cookiep);
677 if (error != 0) {
678 free(scl, M_DEVBUF);
679 return (error);
680 }
681 scl->scl_cookie = *cookiep;
682 *cookiep = scl;
683
684 /*
685 * Clear the interrupt, it might have been triggered before it was
686 * set up.
687 */
688 SYSIO_WRITE8(sc, intrclrptr, 0);
689 /*
690 * Enable the interrupt and program the target module now we have the
691 * handler installed.
692 */
693 SYSIO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(intrmap, PCPU_GET(mid)));
694 return (error);
695}
696
697static int
698sbus_teardown_intr(device_t dev, device_t child,
699 struct resource *vec, void *cookie)
700{
701 struct sbus_clr *scl;
702 int error;
703
704 scl = (struct sbus_clr *)cookie;
705 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec,
706 scl->scl_cookie);
707 /*
708 * Don't disable the interrupt for now, so that stray interupts get
709 * detected...
710 */
711 if (error != 0)
712 free(scl, M_DEVBUF);
713 return (error);
714}
715
716/*
717 * There is no need to handle pass-throughs here; there are no bridges to
718 * SBuses.
719 */
720static struct resource *
721sbus_alloc_resource(device_t bus, device_t child, int type, int *rid,
722 u_long start, u_long end, u_long count, u_int flags)
723{
724 struct sbus_softc *sc;
725 struct sbus_devinfo *sdi;
726 struct rman *rm;
727 struct resource *rv;
728 struct resource_list *rl;
729 struct resource_list_entry *rle;
730 bus_space_handle_t bh;
731 bus_addr_t toffs;
732 bus_size_t tend;
733 int i;
734 int isdefault = (start == 0UL && end == ~0UL);
735 int needactivate = flags & RF_ACTIVE;
736
737 sc = (struct sbus_softc *)device_get_softc(bus);
738 sdi = device_get_ivars(child);
739 rl = &sdi->sdi_rl;
740 rle = resource_list_find(rl, type, *rid);
741 if (rle == NULL)
742 return (NULL);
743 if (rle->res != NULL)
744 panic("sbus_alloc_resource: resource entry is busy");
745 if (isdefault) {
746 start = rle->start;
747 count = ulmax(count, rle->count);
748 end = ulmax(rle->end, start + count - 1);
749 }
750 switch (type) {
751 case SYS_RES_IRQ:
752 rv = BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type,
753 rid, start, end, count, flags);
754 if (rv == NULL)
755 return (NULL);
756 break;
757 case SYS_RES_MEMORY:
758 rm = NULL;
759 bh = toffs = tend = 0;
760 for (i = 0; i < sc->sc_nrange; i++) {
761 if (sc->sc_rd[i].rd_slot != sdi->sdi_slot ||
762 start < sc->sc_rd[i].rd_coffset ||
763 start > sc->sc_rd[i].rd_cend)
764 continue;
765 /* Disallow cross-range allocations. */
766 if (end > sc->sc_rd[i].rd_cend)
767 return (NULL);
768 /* We've found the connection to the parent bus */
769 toffs = start - sc->sc_rd[i].rd_coffset;
770 tend = end - sc->sc_rd[i].rd_coffset;
771 rm = &sc->sc_rd[i].rd_rman;
772 bh = sc->sc_rd[i].rd_bushandle;
773 }
774 if (toffs == 0L)
775 return (NULL);
776 flags &= ~RF_ACTIVE;
777 rv = rman_reserve_resource(rm, toffs, tend, count, flags,
778 child);
779 if (rv == NULL)
780 return (NULL);
781 rman_set_bustag(rv, sc->sc_cbustag);
782 rman_set_bushandle(rv, bh + rman_get_start(rv));
783 if (needactivate) {
784 if (bus_activate_resource(child, type, *rid, rv)) {
785 rman_release_resource(rv);
786 return (NULL);
787 }
788 }
789 break;
790 default:
791 return (NULL);
792 }
793 rle->res = rv;
794 return (rv);
795}
796
797static int
798sbus_activate_resource(device_t bus, device_t child, int type, int rid,
799 struct resource *r)
800{
801
802 if (type == SYS_RES_IRQ) {
803 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
804 child, type, rid, r));
805 }
806 return (rman_activate_resource(r));
807}
808
809static int
810sbus_deactivate_resource(device_t bus, device_t child, int type, int rid,
811 struct resource *r)
812{
813
814 if (type == SYS_RES_IRQ) {
815 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus),
816 child, type, rid, r));
817 }
818 return (rman_deactivate_resource(r));
819}
820
821static int
822sbus_release_resource(device_t bus, device_t child, int type, int rid,
823 struct resource *r)
824{
825 struct sbus_devinfo *sdi;
826 struct resource_list_entry *rle;
827 int error = 0;
828
829 if (type == SYS_RES_IRQ)
830 error = BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
831 type, rid, r);
832 else {
833 if ((rman_get_flags(r) & RF_ACTIVE) != 0)
834 error = bus_deactivate_resource(child, type, rid, r);
835 if (error != 0)
836 return (error);
837 error = rman_release_resource(r);
838 }
839 if (error != 0)
840 return (error);
841 sdi = device_get_ivars(child);
842 rle = resource_list_find(&sdi->sdi_rl, type, rid);
843 if (rle == NULL)
844 panic("sbus_release_resource: can't find resource");
845 if (rle->res == NULL)
846 panic("sbus_release_resource: resource entry is not busy");
847 rle->res = NULL;
848 return (0);
849}
850
851/*
852 * Handle an overtemp situation.
853 *
854 * SPARCs have temperature sensors which generate interrupts
855 * if the machine's temperature exceeds a certain threshold.
856 * This handles the interrupt and powers off the machine.
857 * The same needs to be done to PCI controller drivers.
858 */
859static void
860sbus_overtemp(void *arg)
861{
862
863 printf("DANGER: OVER TEMPERATURE detected\nShutting down NOW.\n");
864 shutdown_nice(RB_POWEROFF);
865}
866
867/* Try to shut down in time in case of power failure. */
868static void
869sbus_pwrfail(void *arg)
870{
871
872 printf("Power failure detected\nShutting down NOW.\n");
873 shutdown_nice(0);
874}
875
876static bus_space_tag_t
877sbus_alloc_bustag(struct sbus_softc *sc)
878{
879 bus_space_tag_t sbt;
880
881 sbt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF,
882 M_NOWAIT | M_ZERO);
883 if (sbt == NULL)
884 panic("sbus_alloc_bustag: out of memory");
885
886 bzero(sbt, sizeof *sbt);
887 sbt->bst_cookie = sc;
888 sbt->bst_parent = sc->sc_bustag;
889 sbt->bst_type = SBUS_BUS_SPACE;
890 return (sbt);
891}
|