32
33#include "opt_ofw_pci.h"
34
35#include <sys/param.h>
36#include <sys/bus.h>
37#include <sys/kernel.h>
38#include <sys/libkern.h>
39#include <sys/module.h>
40#include <sys/pciio.h>
41
42#include <dev/ofw/ofw_bus.h>
43#include <dev/ofw/ofw_pci.h>
44#include <dev/ofw/openfirm.h>
45
46#include <machine/bus.h>
47#ifndef SUN4V
48#include <machine/bus_common.h>
49#include <machine/iommureg.h>
50#endif
51#include <machine/resource.h>
52
53#include <dev/pci/pcireg.h>
54#include <dev/pci/pcivar.h>
55#include <dev/pci/pci_private.h>
56
57#include <sparc64/pci/ofw_pci.h>
58
59#include "pcib_if.h"
60#include "pci_if.h"
61
62/* Helper functions */
63static void ofw_pcibus_setup_device(device_t bridge, uint32_t clock,
64 u_int busno, u_int slot, u_int func);
65
66/* Methods */
67static device_probe_t ofw_pcibus_probe;
68static device_attach_t ofw_pcibus_attach;
69static pci_assign_interrupt_t ofw_pcibus_assign_interrupt;
70static ofw_bus_get_devinfo_t ofw_pcibus_get_devinfo;
71static bus_child_pnpinfo_str_t ofw_pcibus_pnpinfo_str;
72
73static device_method_t ofw_pcibus_methods[] = {
74 /* Device interface */
75 DEVMETHOD(device_probe, ofw_pcibus_probe),
76 DEVMETHOD(device_attach, ofw_pcibus_attach),
77
78 /* Bus interface */
79 DEVMETHOD(bus_child_pnpinfo_str, ofw_pcibus_pnpinfo_str),
80
81 /* PCI interface */
82 DEVMETHOD(pci_assign_interrupt, ofw_pcibus_assign_interrupt),
83
84 /* ofw_bus interface */
85 DEVMETHOD(ofw_bus_get_devinfo, ofw_pcibus_get_devinfo),
86 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
87 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
88 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
89 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
90 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
91
92 KOBJMETHOD_END
93};
94
95struct ofw_pcibus_devinfo {
96 struct pci_devinfo opd_dinfo;
97 struct ofw_bus_devinfo opd_obdinfo;
98};
99
100static devclass_t pci_devclass;
101
102DEFINE_CLASS_1(pci, ofw_pcibus_driver, ofw_pcibus_methods, 1 /* no softc */,
103 pci_driver);
| 32
33#include "opt_ofw_pci.h"
34
35#include <sys/param.h>
36#include <sys/bus.h>
37#include <sys/kernel.h>
38#include <sys/libkern.h>
39#include <sys/module.h>
40#include <sys/pciio.h>
41
42#include <dev/ofw/ofw_bus.h>
43#include <dev/ofw/ofw_pci.h>
44#include <dev/ofw/openfirm.h>
45
46#include <machine/bus.h>
47#ifndef SUN4V
48#include <machine/bus_common.h>
49#include <machine/iommureg.h>
50#endif
51#include <machine/resource.h>
52
53#include <dev/pci/pcireg.h>
54#include <dev/pci/pcivar.h>
55#include <dev/pci/pci_private.h>
56
57#include <sparc64/pci/ofw_pci.h>
58
59#include "pcib_if.h"
60#include "pci_if.h"
61
62/* Helper functions */
63static void ofw_pcibus_setup_device(device_t bridge, uint32_t clock,
64 u_int busno, u_int slot, u_int func);
65
66/* Methods */
67static device_probe_t ofw_pcibus_probe;
68static device_attach_t ofw_pcibus_attach;
69static pci_assign_interrupt_t ofw_pcibus_assign_interrupt;
70static ofw_bus_get_devinfo_t ofw_pcibus_get_devinfo;
71static bus_child_pnpinfo_str_t ofw_pcibus_pnpinfo_str;
72
73static device_method_t ofw_pcibus_methods[] = {
74 /* Device interface */
75 DEVMETHOD(device_probe, ofw_pcibus_probe),
76 DEVMETHOD(device_attach, ofw_pcibus_attach),
77
78 /* Bus interface */
79 DEVMETHOD(bus_child_pnpinfo_str, ofw_pcibus_pnpinfo_str),
80
81 /* PCI interface */
82 DEVMETHOD(pci_assign_interrupt, ofw_pcibus_assign_interrupt),
83
84 /* ofw_bus interface */
85 DEVMETHOD(ofw_bus_get_devinfo, ofw_pcibus_get_devinfo),
86 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
87 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
88 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
89 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
90 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
91
92 KOBJMETHOD_END
93};
94
95struct ofw_pcibus_devinfo {
96 struct pci_devinfo opd_dinfo;
97 struct ofw_bus_devinfo opd_obdinfo;
98};
99
100static devclass_t pci_devclass;
101
102DEFINE_CLASS_1(pci, ofw_pcibus_driver, ofw_pcibus_methods, 1 /* no softc */,
103 pci_driver);
|
105MODULE_VERSION(ofw_pcibus, 1);
106MODULE_DEPEND(ofw_pcibus, pci, 1, 1, 1);
107
108static int
109ofw_pcibus_probe(device_t dev)
110{
111
112 if (ofw_bus_get_node(dev) == 0)
113 return (ENXIO);
114 device_set_desc(dev, "OFW PCI bus");
115
116 return (0);
117}
118
119/*
120 * Perform miscellaneous setups the firmware usually does not do for us.
121 */
122static void
123ofw_pcibus_setup_device(device_t bridge, uint32_t clock, u_int busno,
124 u_int slot, u_int func)
125{
126#ifndef SUN4V
127 uint32_t reg;
128
129 /*
130 * Initialize the latency timer register for busmaster devices to
131 * work properly. This is another task which the firmware doesn't
132 * always perform. The Min_Gnt register can be used to compute its
133 * recommended value: it contains the desired latency in units of
134 * 1/4 us assuming a clock rate of 33MHz. To calculate the correct
135 * latency timer value, the clock frequency of the bus (defaulting
136 * to 33MHz) should be used and no wait states assumed.
137 * For bridges, we additionally set up the bridge control and the
138 * secondary latency registers.
139 */
140 if ((PCIB_READ_CONFIG(bridge, busno, slot, func, PCIR_HDRTYPE, 1) &
141 PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) {
142 reg = PCIB_READ_CONFIG(bridge, busno, slot, func,
143 PCIR_BRIDGECTL_1, 1);
144 reg |= PCIB_BCR_MASTER_ABORT_MODE | PCIB_BCR_SERR_ENABLE |
145 PCIB_BCR_PERR_ENABLE;
146#ifdef OFW_PCI_DEBUG
147 device_printf(bridge,
148 "bridge %d/%d/%d: control 0x%x -> 0x%x\n",
149 busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot,
150 func, PCIR_BRIDGECTL_1, 1), reg);
151#endif /* OFW_PCI_DEBUG */
152 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_BRIDGECTL_1,
153 reg, 1);
154
155 reg = OFW_PCI_LATENCY;
156#ifdef OFW_PCI_DEBUG
157 device_printf(bridge,
158 "bridge %d/%d/%d: latency timer %d -> %d\n",
159 busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot,
160 func, PCIR_SECLAT_1, 1), reg);
161#endif /* OFW_PCI_DEBUG */
162 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_SECLAT_1,
163 reg, 1);
164 } else {
165 reg = PCIB_READ_CONFIG(bridge, busno, slot, func,
166 PCIR_MINGNT, 1);
167 if (reg != 0) {
168 switch (clock) {
169 case 33000000:
170 reg *= 8;
171 break;
172 case 66000000:
173 reg *= 4;
174 break;
175 }
176 reg = min(reg, 255);
177 } else
178 reg = OFW_PCI_LATENCY;
179 }
180#ifdef OFW_PCI_DEBUG
181 device_printf(bridge, "device %d/%d/%d: latency timer %d -> %d\n",
182 busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot, func,
183 PCIR_LATTIMER, 1), reg);
184#endif /* OFW_PCI_DEBUG */
185 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_LATTIMER, reg, 1);
186
187 /*
188 * Compute a value to write into the cache line size register.
189 * The role of the streaming cache is unclear in write invalidate
190 * transfers, so it is made sure that it's line size is always
191 * reached. Generally, the cache line size is fixed at 64 bytes
192 * by Fireplane/Safari, JBus and UPA.
193 */
194 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_CACHELNSZ,
195 STRBUF_LINESZ / sizeof(uint32_t), 1);
196#endif
197
198 /*
199 * The preset in the intline register is usually wrong. Reset
200 * it to 255, so that the PCI code will reroute the interrupt if
201 * needed.
202 */
203 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_INTLINE,
204 PCI_INVALID_IRQ, 1);
205}
206
207static int
208ofw_pcibus_attach(device_t dev)
209{
210 device_t pcib;
211 struct ofw_pci_register pcir;
212 struct ofw_pcibus_devinfo *dinfo;
213 phandle_t node, child;
214 uint32_t clock;
215 u_int busno, domain, func, slot;
216
217 pcib = device_get_parent(dev);
218 domain = pcib_get_domain(dev);
219 busno = pcib_get_bus(dev);
220 if (bootverbose)
221 device_printf(dev, "domain=%d, physical bus=%d\n",
222 domain, busno);
223 node = ofw_bus_get_node(dev);
224
225#ifndef SUN4V
226 /* Add the PCI side of the HOST-PCI bridge itself to the bus. */
227 if (strcmp(device_get_name(device_get_parent(pcib)), "nexus") == 0 &&
228 (dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib,
229 domain, busno, 0, 0, sizeof(*dinfo))) != NULL) {
230 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, node) != 0)
231 pci_freecfg((struct pci_devinfo *)dinfo);
232 else
233 pci_add_child(dev, (struct pci_devinfo *)dinfo);
234 }
235#endif
236
237 if (OF_getprop(ofw_bus_get_node(pcib), "clock-frequency", &clock,
238 sizeof(clock)) == -1)
239 clock = 33000000;
240 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
241 if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1)
242 continue;
243 slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
244 func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
245 /* Some OFW device trees contain dupes. */
246 if (pci_find_dbsf(domain, busno, slot, func) != NULL)
247 continue;
248 ofw_pcibus_setup_device(pcib, clock, busno, slot, func);
249 dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib,
250 domain, busno, slot, func, sizeof(*dinfo));
251 if (dinfo == NULL)
252 continue;
253 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) !=
254 0) {
255 pci_freecfg((struct pci_devinfo *)dinfo);
256 continue;
257 }
258 pci_add_child(dev, (struct pci_devinfo *)dinfo);
259 }
260
261 return (bus_generic_attach(dev));
262}
263
264static int
265ofw_pcibus_assign_interrupt(device_t dev, device_t child)
266{
267 ofw_pci_intr_t intr;
268 int isz;
269
270 isz = OF_getprop(ofw_bus_get_node(child), "interrupts", &intr,
271 sizeof(intr));
272 if (isz != sizeof(intr)) {
273 /* No property; our best guess is the intpin. */
274 intr = pci_get_intpin(child);
275#ifndef SUN4V
276 } else if (intr >= 255) {
277 /*
278 * A fully specified interrupt (including IGN), as present on
279 * SPARCengine Ultra AX and E450. Extract the INO and return
280 * it.
281 */
282 return (INTINO(intr));
283#endif
284 }
285 /*
286 * If we got intr from a property, it may or may not be an intpin.
287 * For on-board devices, it frequently is not, and is completely out
288 * of the valid intpin range. For PCI slots, it hopefully is,
289 * otherwise we will have trouble interfacing with non-OFW buses
290 * such as cardbus.
291 * Since we cannot tell which it is without violating layering, we
292 * will always use the route_interrupt method, and treat exceptions
293 * on the level they become apparent.
294 */
295 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr));
296}
297
298static const struct ofw_bus_devinfo *
299ofw_pcibus_get_devinfo(device_t bus, device_t dev)
300{
301 struct ofw_pcibus_devinfo *dinfo;
302
303 dinfo = device_get_ivars(dev);
304 return (&dinfo->opd_obdinfo);
305}
306
307static int
308ofw_pcibus_pnpinfo_str(device_t dev, device_t child, char *buf,
309 size_t buflen)
310{
311
312 pci_child_pnpinfo_str_method(dev, child, buf, buflen);
313 if (ofw_bus_get_node(child) != -1) {
314 strlcat(buf, " ", buflen); /* Separate info. */
315 ofw_bus_gen_child_pnpinfo_str(dev, child, buf, buflen);
316 }
317
318 return (0);
319}
| 106MODULE_VERSION(ofw_pcibus, 1);
107MODULE_DEPEND(ofw_pcibus, pci, 1, 1, 1);
108
109static int
110ofw_pcibus_probe(device_t dev)
111{
112
113 if (ofw_bus_get_node(dev) == 0)
114 return (ENXIO);
115 device_set_desc(dev, "OFW PCI bus");
116
117 return (0);
118}
119
120/*
121 * Perform miscellaneous setups the firmware usually does not do for us.
122 */
123static void
124ofw_pcibus_setup_device(device_t bridge, uint32_t clock, u_int busno,
125 u_int slot, u_int func)
126{
127#ifndef SUN4V
128 uint32_t reg;
129
130 /*
131 * Initialize the latency timer register for busmaster devices to
132 * work properly. This is another task which the firmware doesn't
133 * always perform. The Min_Gnt register can be used to compute its
134 * recommended value: it contains the desired latency in units of
135 * 1/4 us assuming a clock rate of 33MHz. To calculate the correct
136 * latency timer value, the clock frequency of the bus (defaulting
137 * to 33MHz) should be used and no wait states assumed.
138 * For bridges, we additionally set up the bridge control and the
139 * secondary latency registers.
140 */
141 if ((PCIB_READ_CONFIG(bridge, busno, slot, func, PCIR_HDRTYPE, 1) &
142 PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) {
143 reg = PCIB_READ_CONFIG(bridge, busno, slot, func,
144 PCIR_BRIDGECTL_1, 1);
145 reg |= PCIB_BCR_MASTER_ABORT_MODE | PCIB_BCR_SERR_ENABLE |
146 PCIB_BCR_PERR_ENABLE;
147#ifdef OFW_PCI_DEBUG
148 device_printf(bridge,
149 "bridge %d/%d/%d: control 0x%x -> 0x%x\n",
150 busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot,
151 func, PCIR_BRIDGECTL_1, 1), reg);
152#endif /* OFW_PCI_DEBUG */
153 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_BRIDGECTL_1,
154 reg, 1);
155
156 reg = OFW_PCI_LATENCY;
157#ifdef OFW_PCI_DEBUG
158 device_printf(bridge,
159 "bridge %d/%d/%d: latency timer %d -> %d\n",
160 busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot,
161 func, PCIR_SECLAT_1, 1), reg);
162#endif /* OFW_PCI_DEBUG */
163 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_SECLAT_1,
164 reg, 1);
165 } else {
166 reg = PCIB_READ_CONFIG(bridge, busno, slot, func,
167 PCIR_MINGNT, 1);
168 if (reg != 0) {
169 switch (clock) {
170 case 33000000:
171 reg *= 8;
172 break;
173 case 66000000:
174 reg *= 4;
175 break;
176 }
177 reg = min(reg, 255);
178 } else
179 reg = OFW_PCI_LATENCY;
180 }
181#ifdef OFW_PCI_DEBUG
182 device_printf(bridge, "device %d/%d/%d: latency timer %d -> %d\n",
183 busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot, func,
184 PCIR_LATTIMER, 1), reg);
185#endif /* OFW_PCI_DEBUG */
186 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_LATTIMER, reg, 1);
187
188 /*
189 * Compute a value to write into the cache line size register.
190 * The role of the streaming cache is unclear in write invalidate
191 * transfers, so it is made sure that it's line size is always
192 * reached. Generally, the cache line size is fixed at 64 bytes
193 * by Fireplane/Safari, JBus and UPA.
194 */
195 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_CACHELNSZ,
196 STRBUF_LINESZ / sizeof(uint32_t), 1);
197#endif
198
199 /*
200 * The preset in the intline register is usually wrong. Reset
201 * it to 255, so that the PCI code will reroute the interrupt if
202 * needed.
203 */
204 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_INTLINE,
205 PCI_INVALID_IRQ, 1);
206}
207
208static int
209ofw_pcibus_attach(device_t dev)
210{
211 device_t pcib;
212 struct ofw_pci_register pcir;
213 struct ofw_pcibus_devinfo *dinfo;
214 phandle_t node, child;
215 uint32_t clock;
216 u_int busno, domain, func, slot;
217
218 pcib = device_get_parent(dev);
219 domain = pcib_get_domain(dev);
220 busno = pcib_get_bus(dev);
221 if (bootverbose)
222 device_printf(dev, "domain=%d, physical bus=%d\n",
223 domain, busno);
224 node = ofw_bus_get_node(dev);
225
226#ifndef SUN4V
227 /* Add the PCI side of the HOST-PCI bridge itself to the bus. */
228 if (strcmp(device_get_name(device_get_parent(pcib)), "nexus") == 0 &&
229 (dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib,
230 domain, busno, 0, 0, sizeof(*dinfo))) != NULL) {
231 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, node) != 0)
232 pci_freecfg((struct pci_devinfo *)dinfo);
233 else
234 pci_add_child(dev, (struct pci_devinfo *)dinfo);
235 }
236#endif
237
238 if (OF_getprop(ofw_bus_get_node(pcib), "clock-frequency", &clock,
239 sizeof(clock)) == -1)
240 clock = 33000000;
241 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
242 if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1)
243 continue;
244 slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
245 func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
246 /* Some OFW device trees contain dupes. */
247 if (pci_find_dbsf(domain, busno, slot, func) != NULL)
248 continue;
249 ofw_pcibus_setup_device(pcib, clock, busno, slot, func);
250 dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib,
251 domain, busno, slot, func, sizeof(*dinfo));
252 if (dinfo == NULL)
253 continue;
254 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) !=
255 0) {
256 pci_freecfg((struct pci_devinfo *)dinfo);
257 continue;
258 }
259 pci_add_child(dev, (struct pci_devinfo *)dinfo);
260 }
261
262 return (bus_generic_attach(dev));
263}
264
265static int
266ofw_pcibus_assign_interrupt(device_t dev, device_t child)
267{
268 ofw_pci_intr_t intr;
269 int isz;
270
271 isz = OF_getprop(ofw_bus_get_node(child), "interrupts", &intr,
272 sizeof(intr));
273 if (isz != sizeof(intr)) {
274 /* No property; our best guess is the intpin. */
275 intr = pci_get_intpin(child);
276#ifndef SUN4V
277 } else if (intr >= 255) {
278 /*
279 * A fully specified interrupt (including IGN), as present on
280 * SPARCengine Ultra AX and E450. Extract the INO and return
281 * it.
282 */
283 return (INTINO(intr));
284#endif
285 }
286 /*
287 * If we got intr from a property, it may or may not be an intpin.
288 * For on-board devices, it frequently is not, and is completely out
289 * of the valid intpin range. For PCI slots, it hopefully is,
290 * otherwise we will have trouble interfacing with non-OFW buses
291 * such as cardbus.
292 * Since we cannot tell which it is without violating layering, we
293 * will always use the route_interrupt method, and treat exceptions
294 * on the level they become apparent.
295 */
296 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr));
297}
298
299static const struct ofw_bus_devinfo *
300ofw_pcibus_get_devinfo(device_t bus, device_t dev)
301{
302 struct ofw_pcibus_devinfo *dinfo;
303
304 dinfo = device_get_ivars(dev);
305 return (&dinfo->opd_obdinfo);
306}
307
308static int
309ofw_pcibus_pnpinfo_str(device_t dev, device_t child, char *buf,
310 size_t buflen)
311{
312
313 pci_child_pnpinfo_str_method(dev, child, buf, buflen);
314 if (ofw_bus_get_node(child) != -1) {
315 strlcat(buf, " ", buflen); /* Separate info. */
316 ofw_bus_gen_child_pnpinfo_str(dev, child, buf, buflen);
317 }
318
319 return (0);
320}
|